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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_par.html] - Blame information for rev 9

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<HTML>
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<HEAD><TITLE>Place & Route Report</TITLE>
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<!--
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 body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
    margin-bottom: 10px;
    border-bottom: 3px solid #000;    font-size: 1em;
}
h2 {
    font-weight: bold;
    margin-top: 18px;
    margin-bottom: 5px;
    font-size: 0.90em;
}
h3 {
    font-weight: bold;
    margin-top: 12px;
    margin-bottom: 5px;
    font-size: 0.80em;
}
p {
    font-size:78%;
}
P.Table {
    margin-top: 4px;
    margin-bottom: 4px;
    margin-right: 4px;
    margin-left: 4px;
}
table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    border-collapse: collapse;
}
th {
    font-weight:bold;
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    font-size:78%;
}
a {
    color:#013C9A;
    text-decoration:none;
}

a:visited {
    color:#013C9A;
}

a:hover, a:active {
    text-decoration:underline;
    color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
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-->
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 2.2.0.101.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp.   All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
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Copyright (c) 2001 Agere Systems   All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
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Mon Jan  6 06:54:33 2014
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/usr/local/diamond/2.2_x64/ispfpga/bin/lin64/par -f P6809_P6809.p2t
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P6809_P6809_map.ncd P6809_P6809.dir P6809_P6809.prf
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Preference file: P6809_P6809.prf.
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<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
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Level/      Number      Worst       Timing      Run         NCD
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Cost [ncd]  Unrouted    Slack       Score       Time        Status
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----------  --------    -----       --------    -----       ------
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5_1   *     0           1.054       0           27          Complete
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* : Design saved.
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Total (real) run time for 1-seed: 27 secs
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par done!
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Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
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Mon Jan  6 06:54:33 2014
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<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
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PAR: Place And Route Diamond (64-bit) 2.2.0.101.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
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Preference file: P6809_P6809.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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Loading design for application par from file P6809_P6809_map.ncd.
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Design name: CC3_top
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NCD version: 3.2
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Vendor:      LATTICE
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Device:      LCMXO2-7000HE
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Package:     TQFP144
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Performance: 4
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Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
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Package Status:                     Final          Version 1.36
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Performance Hardware Data Status:   Final)         Version 23.4
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License checked out.
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Ignore Preference Error(s):  True
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<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
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   PIO (prelim)   49+4(JTAG)/336     14% used
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                  49+4(JTAG)/115     42% bonded
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   IOLOGIC           10/336           2% used
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   SLICE           1218/3432         35% used
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   GSR                1/1           100% used
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INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
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INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
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Number of Signals: 2816
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Number of Connections: 9541
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Pin Constraint Summary:
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   49 out of 49 pins locked (100% locked).
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The following 1 signal is selected to use the primary clock routing resources:
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    cpu_clkgen (driver: clk40_i, clk load #: 290)
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The following 4 signals are selected to use the secondary clock routing resources:
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    cpu_clk (driver: SLICE_383, clk load #: 0, sr load #: 0, ce load #: 80)
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    cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_689, clk load #: 0, sr load #: 0, ce load #: 16)
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    cpu0/regs/PC_1_sqmuxa_2_RNIDL992 (driver: SLICE_383, clk load #: 0, sr load #: 0, ce load #: 16)
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    cpu0/un1_k_opcode_3_3_RNIC8F8I (driver: cpu0/regs/SLICE_634, clk load #: 0, sr load #: 0, ce load #: 14)
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Signal reset_o_c is selected as Global Set/Reset.
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Starting Placer Phase 0.
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............
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Finished Placer Phase 0.  REAL time: 4 secs
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Starting Placer Phase 1.
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......................
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Finished Placer Phase 1.  REAL time: 12 secs
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Placer score =  881873
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<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
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  PLL        : 0 out of 2 (0%)
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  DCC        : 0 out of 8 (0%)
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Quadrants All (TL, TR, BL, BR) - Global Clocks:
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  SECONDARY "cpu_clk" from Q0 on comp "SLICE_383" on site "R2C25B", clk load = 0, ce load = 80, sr load = 0
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  SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_689" on site "R15C40A", clk load = 0, ce load = 16, sr load = 0
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  PRIMARY  : 1 out of 8 (12%)
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  SECONDARY: 4 out of 8 (50%)
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Edge Clocks:
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  No edge clock selected.
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I/O Usage Summary (final):
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   49 out of 336 (14.6%) PIO sites used.
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   49 out of 115 (42.6%) bonded PIO sites used.
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   Number of PIO comps: 49; differential: 0
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   Number of Vref pins used: 0
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I/O Bank Usage Summary:
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+----------+----------------+------------+-----------+
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| 0        | 12 / 28 ( 42%) | 2.5V       | -         |
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| 2        | 23 / 29 ( 79%) | 2.5V       | -         |
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| 4        | 0 / 10 (  0%)  | -          | -         |
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| 5        | 0 / 10 (  0%)  | -          | -         |
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+----------+----------------+------------+-----------+
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Total placer CPU time: 13 secs
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Dumping design to file P6809_P6809.dir/5_1.ncd.
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Completed router resource preassignment. Real time: 16 secs
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Start NBR router at Mon Jan 06 06:54:49 CET 2014
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*****************************************************************
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Info: NBR allows conflicts(one node used by more than one signal)
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      solve the conflicts while keeping the critical connections
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      routed as short as possible. The routing process is said to
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Note: NBR uses a different method to calculate timing slacks. The
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      worst slack and total negative slack may not be the same as
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      that in TRCE report. You should always run TRCE to verify
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      your design. Thanks.
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*****************************************************************
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Start NBR special constraint process at Mon Jan 06 06:54:49 CET 2014
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Start NBR section for initial routing
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Level 1, iteration 1
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Estimated worst slack/total negative slack: 0.240ns/0.000ns; real time: 18 secs
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Level 2, iteration 1
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14(0.00%) conflicts; 8033(84.19%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack: 0.378ns/0.000ns; real time: 18 secs
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53(0.01%) conflicts; 6834(71.63%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack: 1.074ns/0.000ns; real time: 19 secs
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Level 4, iteration 1
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396(0.10%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Info: Initial congestion area  at 75% usage is 5 (0.50%)
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Start NBR section for normal routing
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Level 1, iteration 1
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13(0.00%) conflicts; 564(5.91%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
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Level 2, iteration 1
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Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
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Level 3, iteration 1
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17(0.00%) conflicts; 541(5.67%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
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Level 4, iteration 1
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192(0.05%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Level 4, iteration 2
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92(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Level 4, iteration 3
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36(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Level 4, iteration 5
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7(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
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Level 4, iteration 6
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4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Level 4, iteration 7
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2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
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Level 4, iteration 8
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1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
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Level 4, iteration 9
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
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Start NBR section for re-routing
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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End NBR router with 0 unrouted connection
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NBR Summary
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  Number of unrouted connections : 0 (0.00%)
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  Estimated worst slack : 1.054ns
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  Timing score : 0
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-----------
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Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
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Hold time optimization iteration 0:
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All hold time violations have been successfully corrected in speed grade M
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Total CPU time 26 secs
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Total REAL time: 27 secs
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End of route.  9541 routed (100.00%); 0 unrouted.
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No errors found.
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Hold time timing score: 0, hold timing errors: 0
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Timing score: 0
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Dumping design to file P6809_P6809.dir/5_1.ncd.
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All signals are completely routed.
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PAR_SUMMARY::Run status = completed
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PAR_SUMMARY::Worst  slack<setup/<ns>> = 1.054
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PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
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PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
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Total CPU  time to completion: 27 secs
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Total REAL time to completion: 27 secs
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par done!
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp.   All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
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Copyright (c) 2001 Agere Systems   All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
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</PRE></FONT>
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