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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
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#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
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#install: /usr/local/diamond/2.2_x64/synpbase
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#OS: Linux
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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$ Start of Compile
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#Thu Feb 6 15:34:32 2014
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
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@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
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@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
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@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":732:23:732:27|Specified digits overflow the number's size
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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Verilog syntax check successful!
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File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v changed - recompiling
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Selecting top level module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":158:7:158:12|Synthesizing module shift8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:7:198:10|Synthesizing module alu8
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:12:241:13|No assignment to n8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:20:241:21|No assignment to z8
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":302:0:302:5|Pruning register regq8[7:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":604:7:604:12|Synthesizing module mul8x8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":129:7:129:13|Synthesizing module arith16
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":326:7:326:11|Synthesizing module alu16
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":412:23:412:29|No assignment to wire arith_h
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":518:0:518:5|Pruning register regq16[15:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":138:7:138:15|Synthesizing module decode_op
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":266:7:266:15|Synthesizing module decode_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:7:292:16|Synthesizing module decode_alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":450:6:450:13|Ignoring system task $display
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1074:0:1074:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":67:11:67:23|No assignment to wire alu8_o_result
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":68:11:68:20|No assignment to wire alu8_o_CCR
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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114 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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117 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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118 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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119 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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120 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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121 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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122 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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123 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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124 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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125 |
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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126 |
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[1] is always 0, optimizing ...
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128 |
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[2] is always 0, optimizing ...
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129 |
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130 |
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131 |
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|
132 |
10 |
ale500 |
|
133 |
9 |
ale500 |
|
134 |
10 |
ale500 |
|
135 |
9 |
ale500 |
|
136 |
10 |
ale500 |
|
137 |
|
|
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
|
138 |
|
|
|
139 |
|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
|
140 |
9 |
ale500 |
|
141 |
10 |
ale500 |
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
|
142 |
9 |
ale500 |
|
143 |
10 |
ale500 |
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom
|
144 |
9 |
ale500 |
|
145 |
10 |
ale500 |
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k
|
146 |
9 |
ale500 |
|
147 |
10 |
ale500 |
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
|
148 |
9 |
ale500 |
|
149 |
10 |
ale500 |
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext
|
150 |
9 |
ale500 |
|
151 |
|
|
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display
|
152 |
|
|
|
153 |
|
|
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet
|
154 |
|
|
|
155 |
|
|
@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
|
156 |
|
|
|
157 |
|
|
|
158 |
|
|
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
|
159 |
|
|
|
160 |
|
|
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
|
161 |
|
|
|
162 |
|
|
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
|
163 |
|
|
|
164 |
|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
|
165 |
|
|
|
166 |
|
|
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:14:37:21|No assignment to clk_div2
|
167 |
|
|
|
168 |
|
|
|
169 |
|
|
|
170 |
10 |
ale500 |
|
171 |
|
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out
|
172 |
|
|
|
173 |
9 |
ale500 |
|
174 |
10 |
ale500 |
|
175 |
9 |
ale500 |
|
176 |
10 |
ale500 |
|
177 |
|
|
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
178 |
|
|
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
179 |
|
|
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
180 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
|
181 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
|
182 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
|
183 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
|
184 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
|
185 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
|
186 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
|
187 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
|
188 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
|
189 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
|
190 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
|
191 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
|
192 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
|
193 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
|
194 |
|
|
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 5 to 3 of next_push_state[5:0]
|
195 |
|
|
|
196 |
|
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":22:12:22:20|Input debug_clk is unused
|
197 |
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
198 |
|
|
|
199 |
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
|
200 |
|
|
|
201 |
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
|
202 |
|
|
|
203 |
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
204 |
|
|
|
205 |
|
|
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]
|
206 |
|
|
|
207 |
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...
|
208 |
|
|
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]
|
209 |
|
|
|
210 |
|
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":199:12:199:17|Input clk_in is unused
|
211 |
|
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":160:18:160:21|Input b_in is unused
|
212 |
|
|
@END
|
213 |
9 |
ale500 |
|
214 |
10 |
ale500 |
# Thu Feb 6 15:34:36 2014
|
215 |
|
|
|
216 |
9 |
ale500 |
###########################################################]
|
217 |
|
|
|
218 |
|
|
|
219 |
|
|
|
220 |
|
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
221 |
|
|
|
222 |
|
|
|
223 |
|
|
|
224 |
|
|
|
225 |
|
|
|
226 |
|
|
Printing clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file
|
227 |
|
|
|
228 |
|
|
@N: MF666 |Clock conversion enabled
|
229 |
|
|
|
230 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
|
231 |
|
|
|
232 |
|
|
|
233 |
|
|
|
234 |
|
|
|
235 |
|
|
|
236 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
|
237 |
|
|
|
238 |
|
|
|
239 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)
|
240 |
|
|
|
241 |
|
|
|
242 |
|
|
|
243 |
|
|
Clock Summary
|
244 |
|
|
|
245 |
|
|
|
246 |
|
|
Start Requested Requested Clock Clock
|
247 |
|
|
Clock Frequency Period Type Group
|
248 |
|
|
|
249 |
10 |
ale500 |
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
|
250 |
|
|
CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
|
251 |
9 |
ale500 |
|
252 |
10 |
ale500 |
====================================================================================================================
|
253 |
9 |
ale500 |
|
254 |
10 |
ale500 |
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
255 |
9 |
ale500 |
|
256 |
10 |
ale500 |
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
257 |
9 |
ale500 |
|
258 |
10 |
ale500 |
|
259 |
9 |
ale500 |
|
260 |
10 |
ale500 |
|
261 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
262 |
|
|
# Thu Feb 6 15:34:40 2014
|
263 |
9 |
ale500 |
|
264 |
|
|
###########################################################]
|
265 |
|
|
Map & Optimize Report
|
266 |
|
|
|
267 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
268 |
|
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
269 |
|
|
Product Version G-2012.09L-SP1
|
270 |
|
|
|
271 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
272 |
|
|
|
273 |
|
|
@N: MF248 |Running in 64-bit mode.
|
274 |
|
|
@N: MF666 |Clock conversion enabled
|
275 |
|
|
|
276 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
277 |
10 |
ale500 |
|
278 |
9 |
ale500 |
|
279 |
10 |
ale500 |
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
280 |
9 |
ale500 |
|
281 |
|
|
|
282 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
|
283 |
|
|
|
284 |
|
|
|
285 |
|
|
|
286 |
10 |
ale500 |
|
287 |
9 |
ale500 |
|
288 |
10 |
ale500 |
|
289 |
9 |
ale500 |
|
290 |
10 |
ale500 |
|
291 |
|
|
|
292 |
9 |
ale500 |
|
293 |
10 |
ale500 |
None Found
|
294 |
|
|
|
295 |
9 |
ale500 |
|
296 |
10 |
ale500 |
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
|
297 |
|
|
|
298 |
9 |
ale500 |
|
299 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
300 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
301 |
|
|
|
302 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
|
303 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
|
304 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
|
305 |
|
|
|
306 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
|
307 |
|
|
|
308 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
|
309 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
310 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
311 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
312 |
|
|
|
313 |
|
|
Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 159MB)
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 160MB)
|
320 |
|
|
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IY[15:0] pushed in.
|
327 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IX[15:0] pushed in.
|
328 |
|
|
|
329 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register DP[7:0] pushed in.
|
330 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.
|
331 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register eflag pushed in.
|
332 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register fflag pushed in.
|
333 |
10 |
ale500 |
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register hflag pushed in.
|
334 |
9 |
ale500 |
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register intff pushed in.
|
335 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register nff pushed in.
|
336 |
|
|
|
337 |
10 |
ale500 |
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register vff pushed in.
|
338 |
9 |
ale500 |
|
339 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register PC[15:0] pushed in.
|
340 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.
|
341 |
|
|
|
342 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_inc_pc pushed in.
|
343 |
|
|
|
344 |
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":142:35:142:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
|
345 |
10 |
ale500 |
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
|
346 |
9 |
ale500 |
|
347 |
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)
|
348 |
|
|
|
349 |
|
|
|
350 |
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)
|
351 |
|
|
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:11s; Memory used current: 151MB peak: 160MB)
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:13s; Memory used current: 202MB peak: 230MB)
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
------------------------------------------------------------
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
------------------------------------------------------------
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 230MB)
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:15s; Memory used current: 168MB peak: 230MB)
|
373 |
|
|
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
377 |
|
|
|
378 |
|
|
|
379 |
10 |
ale500 |
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
380 |
9 |
ale500 |
|
381 |
10 |
ale500 |
|
382 |
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
383 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
384 |
9 |
ale500 |
---------------------------------------------------------------------------------------
|
385 |
|
|
@K:CKID0001 clk40_i port 596 div
|
386 |
|
|
=======================================================================================
|
387 |
|
|
===== Gated/Generated Clocks =====
|
388 |
|
|
************** None **************
|
389 |
|
|
----------------------------------
|
390 |
|
|
==================================
|
391 |
|
|
|
392 |
10 |
ale500 |
|
393 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
394 |
|
|
|
395 |
9 |
ale500 |
|
396 |
10 |
ale500 |
|
397 |
9 |
ale500 |
|
398 |
10 |
ale500 |
|
399 |
|
|
Writing EDIF Netlist and constraint files
|
400 |
|
|
G-2012.09L-SP1
|
401 |
9 |
ale500 |
|
402 |
10 |
ale500 |
|
403 |
9 |
ale500 |
|
404 |
|
|
|
405 |
|
|
|
406 |
10 |
ale500 |
|
407 |
9 |
ale500 |
|
408 |
10 |
ale500 |
|
409 |
|
|
##### START OF TIMING REPORT #####[
|
410 |
|
|
# Timing Report written on Thu Feb 6 15:35:10 2014
|
411 |
|
|
#
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
Top view: CC3_top
|
415 |
|
|
Requested Frequency: 1.0 MHz
|
416 |
|
|
Wire load mode: top
|
417 |
|
|
Paths requested: 5
|
418 |
|
|
Constraint File(s):
|
419 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
420 |
|
|
|
421 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
422 |
|
|
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
Performance Summary
|
426 |
|
|
*******************
|
427 |
|
|
|
428 |
9 |
ale500 |
|
429 |
|
|
|
430 |
10 |
ale500 |
|
431 |
9 |
ale500 |
|
432 |
|
|
|
433 |
10 |
ale500 |
------------------------------------------------------------------------------------------------------------------------
|
434 |
9 |
ale500 |
|
435 |
|
|
|
436 |
10 |
ale500 |
|
437 |
9 |
ale500 |
|
438 |
|
|
|
439 |
10 |
ale500 |
|
440 |
9 |
ale500 |
|
441 |
|
|
|
442 |
10 |
ale500 |
*******************
|
443 |
9 |
ale500 |
|
444 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
445 |
|
|
--------------------------------------------------------------------------------------------------------------------------
|
446 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
447 |
|
|
--------------------------------------------------------------------------------------------------------------------------
|
448 |
|
|
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 978.937 | No paths - | No paths - | No paths -
|
449 |
|
|
|
450 |
|
|
|
451 |
10 |
ale500 |
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
452 |
9 |
ale500 |
|
453 |
|
|
|
454 |
|
|
|
455 |
10 |
ale500 |
Interface Information
|
456 |
9 |
ale500 |
|
457 |
|
|
|
458 |
|
|
|
459 |
|
|
|
460 |
|
|
|
461 |
10 |
ale500 |
|
462 |
9 |
ale500 |
|
463 |
10 |
ale500 |
Detailed Report for Clock: CC3_top|clk40_i
|
464 |
9 |
ale500 |
|
465 |
|
|
|
466 |
|
|
|
467 |
|
|
|
468 |
10 |
ale500 |
Starting Points with Worst Slack
|
469 |
9 |
ale500 |
********************************
|
470 |
|
|
|
471 |
|
|
Starting Arrival
|
472 |
|
|
Instance Reference Type Pin Net Time Slack
|
473 |
|
|
Clock
|
474 |
|
|
|
475 |
|
|
|
476 |
|
|
cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.296 979.080
|
477 |
|
|
|
478 |
|
|
cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.288 979.231
|
479 |
|
|
|
480 |
10 |
ale500 |
cpu0.alu.ra_in[0] CC3_top|clk40_i FD1P3AX Q ra_in[0] 1.299 979.502
|
481 |
9 |
ale500 |
|
482 |
|
|
cpu0.alu.rb_in[6] CC3_top|clk40_i FD1P3AX Q rb_in[6] 1.272 979.545
|
483 |
|
|
cpu0.alu.ra_in[1] CC3_top|clk40_i FD1P3AX Q ra_in[1] 1.299 979.645
|
484 |
|
|
cpu0.alu.ra_in[2] CC3_top|clk40_i FD1P3AX Q ra_in[2] 1.299 979.645
|
485 |
|
|
|
486 |
10 |
ale500 |
|
487 |
9 |
ale500 |
|
488 |
|
|
Ending Points with Worst Slack
|
489 |
|
|
|
490 |
|
|
|
491 |
|
|
|
492 |
|
|
Instance Reference Type Pin Net Time Slack
|
493 |
10 |
ale500 |
Clock
|
494 |
9 |
ale500 |
----------------------------------------------------------------------------------------------
|
495 |
|
|
|
496 |
|
|
|
497 |
|
|
cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 978.937
|
498 |
|
|
cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 978.937
|
499 |
|
|
cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 979.080
|
500 |
|
|
cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 979.080
|
501 |
|
|
cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 979.080
|
502 |
|
|
cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 979.080
|
503 |
|
|
|
504 |
|
|
cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 979.223
|
505 |
|
|
|
506 |
|
|
|
507 |
|
|
|
508 |
|
|
|
509 |
|
|
Worst Path Information
|
510 |
|
|
|
511 |
|
|
|
512 |
10 |
ale500 |
|
513 |
9 |
ale500 |
|
514 |
|
|
Requested Period: 1000.000
|
515 |
|
|
- Setup time: 0.106
|
516 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
517 |
10 |
ale500 |
= Required time: 999.894
|
518 |
9 |
ale500 |
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
Starting point: cpu0.alu.rb_in[0] / Q
|
525 |
|
|
Ending point: cpu0.regs.SS[15] / D
|
526 |
|
|
|
527 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
528 |
|
|
|
529 |
|
|
Instance / Net Pin Pin Arrival No. of
|
530 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
531 |
10 |
ale500 |
-----------------------------------------------------------------------------------------------------------
|
532 |
9 |
ale500 |
cpu0.alu.rb_in[0] FD1P3AX Q Out 1.296 1.296 -
|
533 |
|
|
rb_in[0] Net - - - - 24
|
534 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV A In 0.000 1.296 -
|
535 |
|
|
|
536 |
|
|
|
537 |
|
|
|
538 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D COUT Out 1.544 3.408 -
|
539 |
|
|
un8_q_out_cry_0 Net - - - - 1
|
540 |
|
|
|
541 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.957 -
|
542 |
|
|
|
543 |
|
|
|
544 |
|
|
|
545 |
|
|
q_out_2_cry_1_0_RNO_0 Net - - - - 1
|
546 |
|
|
cpu0.alu.alu16.a16.q_out_2_cry_1_0 CCU2D C1 In 0.000 5.974 -
|
547 |
|
|
cpu0.alu.alu16.a16.q_out_2_cry_1_0 CCU2D COUT Out 1.544 7.519 -
|
548 |
|
|
|
549 |
|
|
|
550 |
|
|
|
551 |
|
|
q_out_2_cry_4 Net - - - - 1
|
552 |
|
|
cpu0.alu.alu16.a16.q_out_2_cry_5_0 CCU2D CIN In 0.000 7.661 -
|
553 |
|
|
|
554 |
|
|
q_out_2_cry_6 Net - - - - 1
|
555 |
|
|
cpu0.alu.alu16.a16.q_out_2_cry_7_0 CCU2D CIN In 0.000 7.804 -
|
556 |
|
|
cpu0.alu.alu16.a16.q_out_2_cry_7_0 CCU2D S0 Out 1.549 9.353 -
|
557 |
|
|
N_2370 Net - - - - 1
|
558 |
10 |
ale500 |
cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 B In 0.000 9.353 -
|
559 |
|
|
cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 Z Out 1.153 10.506 -
|
560 |
|
|
arith_q[7] Net - - - - 3
|
561 |
|
|
cpu0.alu.alu16.q_out_1[7] ORCALUT4 A In 0.000 10.506 -
|
562 |
|
|
cpu0.alu.alu16.q_out_1[7] ORCALUT4 Z Out 1.017 11.523 -
|
563 |
|
|
N_60 Net - - - - 1
|
564 |
|
|
cpu0.alu.alu16.q_out[7] PFUMX ALUT In 0.000 11.523 -
|
565 |
|
|
cpu0.alu.alu16.q_out[7] PFUMX Z Out 0.286 11.809 -
|
566 |
|
|
q16_out[7] Net - - - - 2
|
567 |
|
|
cpu0.alu.alu8.datamux_o_dest_bm[7] ORCALUT4 B In 0.000 11.809 -
|
568 |
9 |
ale500 |
cpu0.alu.alu8.datamux_o_dest_bm[7] ORCALUT4 Z Out 1.017 12.826 -
|
569 |
|
|
|
570 |
|
|
|
571 |
|
|
cpu0.alu.alu8.datamux_o_dest[7] PFUMX Z Out 0.286 13.112 -
|
572 |
|
|
datamux_o_dest[7] Net - - - - 2
|
573 |
|
|
|
574 |
|
|
cpu0.regs.left_1[7] ORCALUT4 Z Out 1.273 14.385 -
|
575 |
|
|
left_1[7] Net - - - - 9
|
576 |
|
|
cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 14.385 -
|
577 |
|
|
cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 15.402 -
|
578 |
10 |
ale500 |
N_250 Net - - - - 1
|
579 |
|
|
cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 15.402 -
|
580 |
|
|
cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 16.418 -
|
581 |
|
|
SS_16[7] Net - - - - 1
|
582 |
|
|
cpu0.regs.SS_230_m3 ORCALUT4 B In 0.000 16.418 -
|
583 |
|
|
cpu0.regs.SS_230_m3 ORCALUT4 Z Out 1.017 17.435 -
|
584 |
|
|
SS_230_i1_mux Net - - - - 1
|
585 |
|
|
cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 17.435 -
|
586 |
|
|
cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.544 18.980 -
|
587 |
|
|
SS_cry[7] Net - - - - 1
|
588 |
9 |
ale500 |
cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 18.980 -
|
589 |
|
|
|
590 |
|
|
|
591 |
|
|
|
592 |
|
|
cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 19.265 -
|
593 |
|
|
SS_cry[11] Net - - - - 1
|
594 |
|
|
|
595 |
|
|
|
596 |
|
|
SS_cry[13] Net - - - - 1
|
597 |
|
|
cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 19.408 -
|
598 |
|
|
cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 20.957 -
|
599 |
|
|
SS_s[15] Net - - - - 1
|
600 |
|
|
cpu0.regs.SS[15] FD1P3AX D In 0.000 20.957 -
|
601 |
|
|
|
602 |
10 |
ale500 |
|
603 |
9 |
ale500 |
|
604 |
10 |
ale500 |
|
605 |
9 |
ale500 |
|
606 |
10 |
ale500 |
|
607 |
9 |
ale500 |
---------------------------------------
|
608 |
|
|
Resource Usage Report
|
609 |
|
|
Part: lcmxo2_7000he-4
|
610 |
|
|
|
611 |
|
|
|
612 |
10 |
ale500 |
PIC Latch: 0
|
613 |
|
|
I/O cells: 69
|
614 |
|
|
Block Rams : 10 of 26 (38%)
|
615 |
|
|
|
616 |
|
|
|
617 |
|
|
Details:
|
618 |
|
|
BB: 8
|
619 |
|
|
CCU2D: 186
|
620 |
|
|
DP8KC: 10
|
621 |
|
|
FD1P3AX: 529
|
622 |
|
|
FD1P3DX: 6
|
623 |
|
|
FD1S3AX: 32
|
624 |
|
|
FD1S3IX: 3
|
625 |
|
|
GSR: 1
|
626 |
|
|
IB: 1
|
627 |
|
|
INV: 20
|
628 |
|
|
L6MUX21: 16
|
629 |
|
|
OB: 60
|
630 |
|
|
OFS1P3DX: 9
|
631 |
|
|
OFS1P3IX: 1
|
632 |
|
|
ORCALUT4: 2014
|
633 |
|
|
PFUMX: 226
|
634 |
|
|
PUR: 1
|
635 |
|
|
VHI: 14
|
636 |
|
|
VLO: 20
|
637 |
|
|
false: 1
|
638 |
|
|
true: 7
|
639 |
|
|
Mapper successful!
|
640 |
|
|
|
641 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:17s; Memory used current: 44MB peak: 230MB)
|
642 |
|
|
|
643 |
|
|
Process took 0h:00m:30s realtime, 0h:00m:17s cputime
|
644 |
|
|
# Thu Feb 6 15:35:11 2014
|
645 |
|
|
|
646 |
|
|
###########################################################]
|
647 |
|
|
|
648 |
|
|
|
649 |
|
|
|
650 |
|
|
<BR>
|
651 |
|
|
<BR>
|
652 |
|
|
<BR>
|
653 |
|
|
<BR>
|
654 |
|
|
<BR>
|
655 |
|
|
<BR>
|
656 |
|
|
<BR>
|
657 |
|
|
<BR>
|
658 |
|
|
<BR>
|
659 |
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