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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_synplify.html] - Blame information for rev 12

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<HTML>
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<HEAD><TITLE>Synthesis Report</TITLE>
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<STYLE TYPE="text/css">
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 body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
    margin-bottom: 10px;
    border-bottom: 3px solid #000;    font-size: 1em;
}
h2 {
    font-weight: bold;
    margin-top: 18px;
    margin-bottom: 5px;
    font-size: 0.90em;
}
h3 {
    font-weight: bold;
    margin-top: 12px;
    margin-bottom: 5px;
    font-size: 0.80em;
}
p {
    font-size:78%;
}
P.Table {
    margin-top: 4px;
    margin-bottom: 4px;
    margin-right: 4px;
    margin-left: 4px;
}
table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    border-collapse: collapse;
}
th {
    font-weight:bold;
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
    border-width: 1px 1px 1px 1px;
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    border-color: black black black black;
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    font-size:78%;
}
a {
    color:#013C9A;
    text-decoration:none;
}

a:visited {
    color:#013C9A;
}

a:hover, a:active {
    text-decoration:underline;
    color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
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-->
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
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#Build: Synplify Pro I-2013.09L , Build 064R, Nov 15 2013
11 
#install: C:\lscc\diamond\3.1_x64\synpbase
12 
#OS: Windows 7 6.1
13 
#Hostname: ALE-PC
14 
 
15 
#Implementation: P6809
16 
 
17 
$ Start of Compile
18 
#Sun Jul 06 07:46:25 2014
19 
 
20 
Synopsys Verilog Compiler, version comp201309rc, Build 136R, built Nov 18 2013
21 
@N|Running in 64-bit mode
22 
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
23 
 
24 
@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v"
25 
@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\pmi_def.v"
26 
@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\umr_capim.v"
27 
@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_objects.v"
28 
@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_pipes.svh"
29 
@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\hypermods.v"
30 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v"
31 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v"
32 
@I:"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\defs.v"
33 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v"
34 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v"
35 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v"
36 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v"
37 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v"
38 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v"
39 
@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v"
40 
Verilog syntax check successful!
41 
File C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v changed - recompiling
42 
Selecting top level module CC3_top
43 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":604:7:604:12|Synthesizing module mul8x8
44 
 
45 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":66:7:66:12|Synthesizing module logic8
46 
 
47 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":89:7:89:12|Synthesizing module arith8
48 
 
49 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":162:7:162:12|Synthesizing module shift8
50 
 
51 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":202:7:202:10|Synthesizing module alu8
52 
 
53 
@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":323:0:323:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
54 
@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":239:12:239:13|No assignment to n8
55 
@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":239:20:239:21|No assignment to z8
56 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":133:7:133:13|Synthesizing module arith16
57 
 
58 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":329:7:329:11|Synthesizing module alu16
59 
 
60 
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":412:23:412:29|No assignment to wire arith_h
61 
 
62 
@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Pruning register regq16[15:0]
63 
 
64 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":15:7:15:9|Synthesizing module alu
65 
 
66 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":191:7:191:13|Synthesizing module calc_ea
67 
 
68 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":7:7:7:14|Synthesizing module regblock
69 
 
70 
@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
71 
 
72 
 
73 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":155:7:155:15|Synthesizing module decode_op
74 
 
75 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":286:7:286:15|Synthesizing module decode_ea
76 
 
77 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":312:7:312:16|Synthesizing module decode_alu
78 
 
79 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":385:7:385:20|Synthesizing module test_condition
80 
 
81 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
82 
 
83 
@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":456:6:456:13|Ignoring system task $display
84 
@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":1125:0:1125:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
85 
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":70:11:70:23|No assignment to wire alu8_o_result
86 
 
87 
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":71:11:71:20|No assignment to wire alu8_o_CCR
88 12 ale500 
 
89 
 
90 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
91 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
92 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
93 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
94 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
95 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
96 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
97 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
98 
 
99 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
100 
 
101 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
102 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
103 
 
104 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
105 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
106 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
107 
 
108 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
109 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
110 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_indirect_loaded -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
111 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
112 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
113 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
114 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
115 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
116 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
117 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
118 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
119 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
120 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
121 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
122 
@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
123 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit k_mem_dest[1] is always 0, optimizing ...
124 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit next_mem_state[1] is always 0, optimizing ...
125 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit next_mem_state[2] is always 0, optimizing ...
126 
@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
127 
 
128 
 
129 
 
130 
 
131 
 
132 
 
133 
 
134 
 
135 
 
136 
 
137 
 
138 
@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
139 
 
140 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v":8:7:8:13|Synthesizing module fontrom
141 
 
142 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":8:7:8:15|Synthesizing module textmem4k
143 
 
144 
@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
145 
 
146 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":2:7:2:13|Synthesizing module vgatext
147 
 
148 
@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":133:4:133:11|Ignoring system task $display
149 
 
150 
@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":174:6:174:11|System task $write is not supported yet
151 
 
152 
@W: CG781 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
153 
 
154 
 
155 
@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
156 
 
157 
@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
158 
 
159 
@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element redr.
160 
 
161 
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":10:7:10:13|Synthesizing module CC3_top
162 
 
163 
@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":37:14:37:21|No assignment to clk_div2
164 
 
165 
 
166 
 
167 
 
168 
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out
169 
 
170 
 
171 
 
172 
 
173 
 
174 
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
175 
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
176 
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
177 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
178 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
179 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
180 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
181 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
182 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
183 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
184 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
185 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
186 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
187 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
188 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
189 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
190 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
191 
@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bits 5 to 3 of next_push_state[5:0]
192 
 
193 
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":22:12:22:20|Input debug_clk is unused
194 
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":389:18:389:20|Input port bits 7 to 4 of CCR[7:0] are unused
195 
 
196 
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":314:18:314:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
197 
 
198 
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":287:18:287:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
199 
 
200 
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":333:18:333:20|Input port bits 7 to 4 of CCR[7:0] are unused
201 
 
202 
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":206:18:206:20|Input port bits 3 to 2 of CCR[7:0] are unused
203 
 
204 
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":203:12:203:17|Input clk_in is unused
205 
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":164:18:164:21|Input b_in is unused
206 
@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]
207 
 
208 
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...
209 
@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]
210 
 
211 
 
212 
 
213 
 
214 
 
215 
 
216 
# Sun Jul 06 07:46:27 2014
217 
 
218 
###########################################################]
219 
 
220 
 
221 
 
222 
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
223 
 
224 
 
225 
 
226 
 
227 
 
228 
Printing clock  summary report in "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809_scck.rpt" file
229 
 
230 
@N: MF666 |Clock conversion enabled
231 
 
232 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
233 
 
234 
 
235 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
236 
 
237 
 
238 
 
239 
 
240 
 
241 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)
242 
 
243 
syn_allowed_resources : blockrams=26  set on top level netlist CC3_top
244 
 
245 
 
246 
 
247 
**************
248 
 
249 
 
250 
Clock                             Frequency     Period        Type                               Group
251 
 
252 
CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0
253 
 
254 
CC3_top|div_derived_clock         1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
255 
 
256 
 
257 
 
258 
 
259 
Pre-mapping successful!
260 
 
261 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 146MB)
262 
 
263 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
264 
# Sun Jul 06 07:46:29 2014
265 
 
266 
###########################################################]
267 
Map & Optimize Report
268 
 
269 
Synopsys Lattice Technology Mapper, Version maplat, Build 800R, Built Nov 18 2013 10:58:25
270 
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
271 
Product Version I-2013.09L
272 
 
273 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
274 
 
275 
@N: MF248 |Running in 64-bit mode.
276 
 
277 
 
278 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
279 
 
280 
 
281 
 
282 
 
283 
 
284 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
285 
 
286 
 
287 
 
288 
 
289 
 
290 
 
291 
 
292 
 
293 
 
294 
 
295 
        None Found
296 
 
297 
 
298 
 
299 
 
300 
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
301 
 
302 
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
303 
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
304 
 
305 
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
306 
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
307 
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
308 
 
309 
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
310 
 
311 
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
312 
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
313 
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
314 
 
315 
 
316 
 
317 
 
318 
 
319 
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
320 
 
321 
 
322 
 
323 
 
324 
 
325 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 163MB peak: 177MB)
326 
 
327 
@N: FA113 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":616:12:617:75|Pipelining module pipe0_1[11:0]
328 
 
329 
 
330 
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register rop_in[4:0] pushed in.
331 
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register ra_in[15:0] pushed in.
332 
 
333 
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register rb_in[15:0] pushed in.
334 
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
335 
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":145:35:145:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_i_m2[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
336 
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":146:35:146:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2_i_m2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
337 
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":288:2:288:3|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.k_new_pc_2[15:0] from cpu0.un1_regs_o_pc[15:0]
338 
 
339 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 165MB peak: 177MB)
340 
 
341 
 
342 
 
343 
 
344 
 
345 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 164MB peak: 177MB)
346 
 
347 
 
348 
Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 164MB peak: 177MB)
349 
 
350 
 
351 
Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 242MB peak: 246MB)
352 
 
353 
Pass             CPU time               Worst Slack             Luts / Registers
354 
------------------------------------------------------------
355 
Pass             CPU time               Worst Slack             Luts / Registers
356 
 
357 
------------------------------------------------------------
358 
 
359 
 
360 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 182MB peak: 246MB)
361 
 
362 
@N: FX164 |The option to pack flops in the IOB has not been specified
363 
 
364 
 
365 
 
366 
 
367 
 
368 
#### START OF CLOCK OPTIMIZATION REPORT #####[
369 
 
370 
 
371 
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
372 
 
373 
 
374 
 
375 
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
376 
 
377 
 
378 
=======================================================================================
379 
 
380 
 
381 
 
382 
 
383 
 
384 
 
385 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 185MB peak: 246MB)
386 
 
387 
Writing EDIF Netlist and constraint files
388 
@W: MT558 |Unable to locate source for clock CC3_top|div_derived_clock. Clock will not be forward annotated
389 
@W: MT558 |Unable to locate source for clock CC3_top|cpu_clk_derived_clock. Clock will not be forward annotated
390 
I-2013.09L
391 
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
392 
 
393 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 189MB peak: 246MB)
394 
 
395 
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
396 
 
397 
 
398 
 
399 
##### START OF TIMING REPORT #####[
400 
 
401 
#
402 
 
403 
 
404 
 
405 
Requested Frequency:    1.0 MHz
406 
 
407 
 
408 
 
409 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
410 
 
411 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
412 
 
413 
 
414 
 
415 
Performance Summary
416 
*******************
417 
 
418 
 
419 
Worst slack in design: 979.573
420 
 
421 
                    Requested     Estimated     Requested     Estimated                 Clock        Clock
422 
 
423 
------------------------------------------------------------------------------------------------------------------------
424 
 
425 
 
426 
 
427 
 
428 
 
429 
 
430 
 
431 
 
432 
*******************
433 
 
434 
 
435 
--------------------------------------------------------------------------------------------------------------------------
436 
 
437 
--------------------------------------------------------------------------------------------------------------------------
438 
CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    979.573  |  No paths    -      |  No paths    -      |  No paths    -
439 
==========================================================================================================================
440 
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
441 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
442 
 
443 
 
444 
 
445 
 
446 
*********************
447 
 
448 
No IO constraint found
449 
 
450 
 
451 
 
452 
====================================
453 
 
454 
====================================
455 
 
456 
 
457 
 
458 
Starting Points with Worst Slack
459 
********************************
460 
 
461 
                          Starting                                                 Arrival
462 
Instance                  Reference           Type        Pin     Net              Time        Slack
463 
 
464 
 
465 
cpu0.alu.rb_in[0]         CC3_top|clk40_i     FD1P3AX     Q       rb_in[0]         1.228       979.573
466 
 
467 
cpu0.alu.rb_in[2]         CC3_top|clk40_i     FD1P3AX     Q       rb_in[2]         1.228       979.716
468 
 
469 
cpu0.k_opcode[7]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[7]      1.339       979.836
470 
 
471 
cpu0.alu.rb_in[3]         CC3_top|clk40_i     FD1P3AX     Q       rb_in[3]         1.228       979.859
472 
cpu0.alu.rb_in_pipe_2     CC3_top|clk40_i     FD1P3AX     Q       rb_in_pipe_2     1.268       979.883
473 
cpu0.k_opcode[3]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[3]      1.369       979.909
474 
cpu0.k_opcode[2]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[2]      1.368       979.911
475 
======================================================================================================
476 
 
477 
 
478 
 
479 
******************************
480 
 
481 
 
482 
 
483 
                     Clock
484 
----------------------------------------------------------------------------------------------
485 
cpu0.regs.SS[14]     CC3_top|clk40_i     FD1P3AX     D       SS_s[14]     999.894      979.573
486 
 
487 
 
488 
cpu0.regs.SU[15]     CC3_top|clk40_i     FD1P3AX     D       SU_s[15]     999.894      979.573
489 
cpu0.regs.SS[12]     CC3_top|clk40_i     FD1P3AX     D       SS_s[12]     999.894      979.716
490 
cpu0.regs.SS[13]     CC3_top|clk40_i     FD1P3AX     D       SS_s[13]     999.894      979.716
491 
cpu0.regs.SU[12]     CC3_top|clk40_i     FD1P3AX     D       SU_s[12]     999.894      979.716
492 
cpu0.regs.SU[13]     CC3_top|clk40_i     FD1P3AX     D       SU_s[13]     999.894      979.716
493 
cpu0.regs.SS[10]     CC3_top|clk40_i     FD1P3AX     D       SS_s[10]     999.894      979.859
494 
 
495 
==============================================================================================
496 
 
497 
 
498 
 
499 
Worst Path Information
500 
***********************
501 
 
502 
 
503 
Path information for path number 1:
504 
 
505 
    - Setup time:                            0.106
506 
    + Clock delay at ending point:           0.000 (ideal)
507 
    = Required time:                         999.894
508 
 
509 
    - Propagation time:                      20.321
510 
 
511 
 
512 
 
513 
 
514 
 
515 
    Ending point:                            cpu0.regs.SS[15] / D
516 
    The start point is clocked by            CC3_top|clk40_i [rising] on pin CK
517 
 
518 
 
519 
Instance / Net                                                 Pin      Pin               Arrival     No. of
520 
Name                                              Type         Name     Dir     Delay     Time        Fan Out(s)
521 
----------------------------------------------------------------------------------------------------------------
522 
cpu0.alu.rb_in[0]                                 FD1P3AX      Q        Out     1.228     1.228       -
523 
rb_in[0]                                          Net          -        -       -         -           9
524 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO          INV          A        In      0.000     1.228       -
525 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO          INV          Z        Out     0.568     1.796       -
526 
 
527 
 
528 
 
529 
un8_q_out_cry_0                                   Net          -        -       -         -           1
530 
cpu0.alu.alu16.a16.un8_q_out_cry_1_0              CCU2D        CIN      In      0.000     3.340       -
531 
 
532 
un8_q_out[2]                                      Net          -        -       -         -           1
533 
 
534 
 
535 
 
536 
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0           CCU2D        C1       In      0.000     5.906       -
537 
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0           CCU2D        COUT     Out     1.545     7.451       -
538 
q_out_2_i_m2_cry_2                                Net          -        -       -         -           1
539 
 
540 
 
541 
 
542 
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_5_0           CCU2D        CIN      In      0.000     7.593       -
543 
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_5_0           CCU2D        COUT     Out     0.143     7.736       -
544 
 
545 
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_7_0           CCU2D        CIN      In      0.000     7.736       -
546 
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_7_0           CCU2D        S0       Out     1.549     9.285       -
547 
N_186                                             Net          -        -       -         -           1
548 
cpu0.alu.alu16.a16.q_out_3[7]                     ORCALUT4     B        In      0.000     9.285       -
549 
cpu0.alu.alu16.a16.q_out_3[7]                     ORCALUT4     Z        Out     1.153     10.438      -
550 
arith_q[7]                                        Net          -        -       -         -           3
551 
cpu0.alu.alu16.q_out_1[7]                         ORCALUT4     A        In      0.000     10.438      -
552 
cpu0.alu.alu16.q_out_1[7]                         ORCALUT4     Z        Out     1.017     11.455      -
553 
N_63                                              Net          -        -       -         -           1
554 
cpu0.alu.alu16.q_out[7]                           PFUMX        ALUT     In      0.000     11.455      -
555 
cpu0.alu.alu16.q_out[7]                           PFUMX        Z        Out     0.286     11.741      -
556 
q16_out[7]                                        Net          -        -       -         -           2
557 
cpu0.alu.q_out[7]                                 ORCALUT4     B        In      0.000     11.741      -
558 
cpu0.alu.q_out[7]                                 ORCALUT4     Z        Out     0.449     12.190      -
559 
alu_o_result[7]                                   Net          -        -       -         -           1
560 
 
561 
 
562 
datamux_o_dest[7]                                 Net          -        -       -         -           2
563 
cpu0.regs.path_left_data_RNIVJGV[7]               ORCALUT4     B        In      0.000     12.476      -
564 
 
565 
left_1[7]                                         Net          -        -       -         -           9
566 
cpu0.regs.SS_16_0[7]                              ORCALUT4     B        In      0.000     13.749      -
567 
cpu0.regs.SS_16_0[7]                              ORCALUT4     Z        Out     1.017     14.766      -
568 
N_252                                             Net          -        -       -         -           1
569 
cpu0.regs.SS_16[7]                                ORCALUT4     A        In      0.000     14.766      -
570 
cpu0.regs.SS_16[7]                                ORCALUT4     Z        Out     1.017     15.782      -
571 
SS_16[7]                                          Net          -        -       -         -           1
572 
cpu0.regs.SS_222_m3                               ORCALUT4     B        In      0.000     15.782      -
573 
cpu0.regs.SS_222_m3                               ORCALUT4     Z        Out     1.017     16.799      -
574 
SS_222_i1_mux                                     Net          -        -       -         -           1
575 
cpu0.regs.SS_cry_0[6]                             CCU2D        C1       In      0.000     16.799      -
576 
cpu0.regs.SS_cry_0[6]                             CCU2D        COUT     Out     1.545     18.344      -
577 
SS_cry[7]                                         Net          -        -       -         -           1
578 
cpu0.regs.SS_cry_0[8]                             CCU2D        CIN      In      0.000     18.344      -
579 
cpu0.regs.SS_cry_0[8]                             CCU2D        COUT     Out     0.143     18.486      -
580 
 
581 
 
582 
 
583 
SS_cry[11]                                        Net          -        -       -         -           1
584 
cpu0.regs.SS_cry_0[12]                            CCU2D        CIN      In      0.000     18.629      -
585 
 
586 
 
587 
cpu0.regs.SS_cry_0[14]                            CCU2D        CIN      In      0.000     18.772      -
588 
cpu0.regs.SS_cry_0[14]                            CCU2D        S1       Out     1.549     20.321      -
589 
SS_s[15]                                          Net          -        -       -         -           1
590 
cpu0.regs.SS[15]                                  FD1P3AX      D        In      0.000     20.321      -
591 
================================================================================================================
592 
 
593 
 
594 
 
595 
##### END OF TIMING REPORT #####]
596 
 
597 
---------------------------------------
598 
Resource Usage Report
599 
Part: lcmxo2_7000he-4
600 
 
601 
Register bits: 489 of 6864 (7%)
602 
 
603 
I/O cells:       69
604 
Block Rams : 10 of 26 (38%)
605 
 
606 
 
607 
Details:
608 
BB:             8
609 
CCU2D:          183
610 
DP8KC:          10
611 
FD1P3AX:        438
612 
FD1P3DX:        6
613 
FD1S3AX:        33
614 
FD1S3IX:        2
615 
GSR:            1
616 
IB:             1
617 
INV:            12
618 
L6MUX21:        30
619 
OB:             60
620 
OFS1P3DX:       9
621 
OFS1P3IX:       1
622 
ORCALUT4:       2078
623 
PFUMX:          239
624 
PUR:            1
625 
VHI:            14
626 
VLO:            20
627 
false:          1
628 
true:           7
629 
Mapper successful!
630 
 
631 
At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 58MB peak: 246MB)
632 
 
633 
Process took 0h:00m:18s realtime, 0h:00m:17s cputime
634 
# Sun Jul 06 07:46:48 2014
635 
 
636 
###########################################################]
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