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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_synplify.html] - Blame information for rev 9

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<HTML>
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<HEAD><TITLE>Synthesis Report</TITLE>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
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#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
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#install: /usr/local/diamond/2.2_x64/synpbase
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#OS: Linux
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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$ Start of Compile
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#Mon Jan  6 06:54:11 2014
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
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@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
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@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
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@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":699:23:699:27|Specified digits overflow the number's size
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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Verilog syntax check successful!
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File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling
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Selecting top level module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
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47 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
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49 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":157:7:157:12|Synthesizing module shift8
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51 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":197:7:197:10|Synthesizing module alu8
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53 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:12:240:13|No assignment to n8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:20:240:21|No assignment to z8
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":603:7:603:12|Synthesizing module mul8x8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":128:7:128:13|Synthesizing module arith16
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":411:23:411:29|No assignment to wire arith_h
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":517:0:517:5|Pruning register regq16[15:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":138:7:138:15|Synthesizing module decode_op
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":266:7:266:15|Synthesizing module decode_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:7:292:16|Synthesizing module decode_alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":418:6:418:13|Ignoring system task $display
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1039:0:1039:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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103 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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107 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
108 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
126 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[0] is always 1, optimizing ...
127 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[1] is always 0, optimizing ...
128 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[1] is always 0, optimizing ...
129 
 
130 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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132 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
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134 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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136 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
137 
 
138 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
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150 
 
151 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet
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153 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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155 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...
156 
 
157 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
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162 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
163 
 
164 
 
165 
 
166 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o
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168 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in
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170 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out
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172 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we
173 
 
174 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe
175 
 
176 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
177 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
178 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":105:25:105:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
179 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
180 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
181 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
182 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
183 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
184 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
185 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
186 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
187 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
188 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
189 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
190 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
191 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
192 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
193 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 5 to 3 of next_push_state[5:0]
194 
 
195 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
196 
 
197 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
198 
 
199 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
200 
 
201 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused
202 
 
203 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bits 15 to 13 of pipe0[15:0]
204 
 
205 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Register bit pipe0[12] is always 0, optimizing ...
206 
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bit 12 of pipe0[12:0]
207 
 
208 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:12:198:17|Input clk_in is unused
209 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":159:18:159:21|Input b_in is unused
210 
@END
211 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
212 
# Mon Jan  6 06:54:13 2014
213 
 
214 
 
215 
Premap Report
216 
 
217 
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
218 
 
219 
Product Version G-2012.09L-SP1
220 
 
221 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
222 
 
223 
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt
224 
 
225 
@N: MF248 |Running in 64-bit mode.
226 
 
227 
 
228 
 
229 
 
230 
 
231 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
232 
 
233 
 
234 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
235 
 
236 
 
237 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)
238 
 
239 
 
240 
 
241 
 
242 
**************
243 
 
244 
Start                             Requested     Requested     Clock                              Clock
245 
Clock                             Frequency     Period        Type                               Group
246 
--------------------------------------------------------------------------------------------------------------------
247 
 
248 
CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
249 
====================================================================================================================
250 
 
251 
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
252 
 
253 
syn_allowed_resources : blockrams=26  set on top level netlist CC3_top
254 
 
255 
 
256 
 
257 
 
258 
 
259 
# Mon Jan  6 06:54:14 2014
260 
 
261 
###########################################################]
262 
Map & Optimize Report
263 
 
264 
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
265 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
266 
Product Version G-2012.09L-SP1
267 
 
268 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
269 
 
270 
@N: MF248 |Running in 64-bit mode.
271 
@N: MF666 |Clock conversion enabled
272 
 
273 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
274 
 
275 
 
276 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
277 
 
278 
 
279 
 
280 
 
281 
 
282 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)
283 
 
284 
 
285 
 
286 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
287 
 
288 
 
289 
Available hyper_sources - for debug and ip models
290 
 
291 
 
292 
 
293 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
294 
 
295 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
296 
 
297 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
298 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
299 
 
300 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
301 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
302 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
303 
 
304 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
305 
 
306 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
307 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
308 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
309 
 
310 
 
311 
 
312 
 
313 
 
314 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
315 
 
316 
 
317 
 
318 
 
319 
 
320 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 165MB)
321 
 
322 
 
323 
 
324 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":143:35:143:85|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
325 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":100:35:100:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_2[8:0] from cpu0.alu.alu8.a8.un26_q_out[8:0]
326 
 
327 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":99:35:99:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_1_0[8:0] from cpu0.alu.alu8.a8.un17_q_out[8:0]
328 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":254:2:254:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.ea.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]
329 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
330 
 
331 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
332 
 
333 
 
334 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
335 
 
336 
 
337 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 151MB peak: 165MB)
338 
 
339 
 
340 
 
341 
 
342 
 
343 
 
344 
 
345 
Pass             CPU time               Worst Slack             Luts / Registers
346 
 
347 
Pass             CPU time               Worst Slack             Luts / Registers
348 
------------------------------------------------------------
349 
------------------------------------------------------------
350 
 
351 
 
352 
 
353 
 
354 
@N: FX164 |The option to pack flops in the IOB has not been specified
355 
 
356 
Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 169MB peak: 229MB)
357 
 
358 
 
359 
 
360 
 
361 
 
362 
1 non-gated/non-generated clock tree(s) driving 455 clock pin(s) of sequential element(s)
363 
 
364 
 
365 
 
366 
 
367 
 
368 
 
369 
@K:CKID0001       clk40_i             port                   455        cpu_clk
370 
 
371 
 
372 
************** None **************
373 
----------------------------------
374 
 
375 
 
376 
 
377 
 
378 
 
379 
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
380 
 
381 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 172MB peak: 229MB)
382 
 
383 
Writing EDIF Netlist and constraint files
384 
G-2012.09L-SP1
385 
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
386 
 
387 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 176MB peak: 229MB)
388 
 
389 
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
390 
 
391 
 
392 
 
393 
##### START OF TIMING REPORT #####[
394 
 
395 
#
396 
 
397 
 
398 
 
399 
Requested Frequency:    1.0 MHz
400 
 
401 
 
402 
 
403 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
404 
 
405 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
406 
 
407 
 
408 
 
409 
Performance Summary
410 
*******************
411 
 
412 
 
413 
 
414 
 
415 
 
416 
 
417 
------------------------------------------------------------------------------------------------------------------------
418 
 
419 
 
420 
 
421 
 
422 
 
423 
 
424 
 
425 
 
426 
*******************
427 
 
428 
Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
429 
--------------------------------------------------------------------------------------------------------------------------
430 
Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
431 
--------------------------------------------------------------------------------------------------------------------------
432 
CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.474  |  No paths    -      |  No paths    -      |  No paths    -
433 
 
434 
 
435 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
436 
 
437 
 
438 
 
439 
Interface Information
440 
 
441 
 
442 
 
443 
 
444 
 
445 
 
446 
 
447 
Detailed Report for Clock: CC3_top|clk40_i
448 
 
449 
 
450 
 
451 
 
452 
Starting Points with Worst Slack
453 
********************************
454 
 
455 
                      Starting                                             Arrival
456 
Instance              Reference           Type        Pin     Net          Time        Slack
457 
                      Clock
458 
 
459 
 
460 
cpu0.alu.rb_in[1]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[1]     1.302       978.617
461 
 
462 
cpu0.alu.rb_in[3]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[3]     1.296       978.766
463 
 
464 
cpu0.alu.ra_in[0]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[0]     1.305       979.039
465 
 
466 
cpu0.alu.ra_in[2]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[2]     1.309       979.178
467 
cpu0.alu.ra_in[3]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[3]     1.305       979.324
468 
cpu0.alu.ra_in[4]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[4]     1.292       979.338
469 
 
470 
 
471 
 
472 
Ending Points with Worst Slack
473 
 
474 
 
475 
 
476 
Instance             Reference           Type        Pin     Net          Time         Slack
477 
                     Clock
478 
----------------------------------------------------------------------------------------------
479 
 
480 
 
481 
cpu0.regs.SU[14]     CC3_top|clk40_i     FD1P3AX     D       SU_s[14]     999.894      978.474
482 
cpu0.regs.SU[15]     CC3_top|clk40_i     FD1P3AX     D       SU_s[15]     999.894      978.474
483 
cpu0.regs.SS[12]     CC3_top|clk40_i     FD1P3AX     D       SS_s[12]     999.894      978.617
484 
cpu0.regs.SS[13]     CC3_top|clk40_i     FD1P3AX     D       SS_s[13]     999.894      978.617
485 
cpu0.regs.SU[12]     CC3_top|clk40_i     FD1P3AX     D       SU_s[12]     999.894      978.617
486 
cpu0.regs.SU[13]     CC3_top|clk40_i     FD1P3AX     D       SU_s[13]     999.894      978.617
487 
 
488 
cpu0.regs.SS[11]     CC3_top|clk40_i     FD1P3AX     D       SS_s[11]     999.894      978.760
489 
 
490 
 
491 
 
492 
 
493 
Worst Path Information
494 
 
495 
 
496 
 
497 
 
498 
      Requested Period:                      1000.000
499 
    - Setup time:                            0.106
500 
    + Clock delay at ending point:           0.000 (ideal)
501 
    = Required time:                         999.894
502 
 
503 
 
504 
 
505 
 
506 
 
507 
 
508 
    Starting point:                          cpu0.alu.rb_in[0] / Q
509 
    Ending point:                            cpu0.regs.SS[15] / D
510 
 
511 
    The end   point is clocked by            CC3_top|clk40_i [rising] on pin CK
512 
 
513 
Instance / Net                                          Pin      Pin               Arrival     No. of
514 
Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
515 
---------------------------------------------------------------------------------------------------------
516 
cpu0.alu.rb_in[0]                          FD1P3AX      Q        Out     1.302     1.302       -
517 
rb_in[0]                                   Net          -        -       -         -           26
518 
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO     INV          A        In      0.000     1.302       -
519 
 
520 
 
521 
 
522 
cpu0.alu.alu8.a8.un8_q_out_cry_0_0         CCU2D        COUT     Out     1.544     3.415       -
523 
un8_q_out_cry_0                            Net          -        -       -         -           1
524 
 
525 
cpu0.alu.alu8.a8.un8_q_out_cry_1_0         CCU2D        S1       Out     1.549     4.964       -
526 
 
527 
 
528 
 
529 
q_out_2_cry_1_0_RNO_0                      Net          -        -       -         -           1
530 
cpu0.alu.alu8.a8.q_out_2_cry_1_0           CCU2D        C1       In      0.000     5.981       -
531 
cpu0.alu.alu8.a8.q_out_2_cry_1_0           CCU2D        COUT     Out     1.544     7.525       -
532 
 
533 
 
534 
 
535 
q_out_2_cry_4                              Net          -        -       -         -           1
536 
cpu0.alu.alu8.a8.q_out_2_cry_5_0           CCU2D        CIN      In      0.000     7.668       -
537 
 
538 
q_out_2_cry_6                              Net          -        -       -         -           1
539 
cpu0.alu.alu8.a8.q_out_2_cry_7_0           CCU2D        CIN      In      0.000     7.811       -
540 
cpu0.alu.alu8.a8.q_out_2_cry_7_0           CCU2D        S0       Out     1.549     9.360       -
541 
N_2388                                     Net          -        -       -         -           1
542 
cpu0.alu.alu8.a8.q_out_3[7]                ORCALUT4     A        In      0.000     9.360       -
543 
cpu0.alu.alu8.a8.q_out_3[7]                ORCALUT4     Z        Out     1.089     10.448      -
544 
arith_q[7]                                 Net          -        -       -         -           2
545 
cpu0.alu.alu8.q_out_4_am[7]                ORCALUT4     A        In      0.000     10.448      -
546 
cpu0.alu.alu8.q_out_4_am[7]                ORCALUT4     Z        Out     1.017     11.465      -
547 
q_out_4_am[7]                              Net          -        -       -         -           1
548 
cpu0.alu.alu8.q_out_4[7]                   PFUMX        BLUT     In      0.000     11.465      -
549 
cpu0.alu.alu8.q_out_4[7]                   PFUMX        Z        Out     0.286     11.751      -
550 
N_160                                      Net          -        -       -         -           2
551 
cpu0.alu.alu8.q_out_5_RNIRSTD1[7]          ORCALUT4     A        In      0.000     11.751      -
552 
cpu0.alu.alu8.q_out_5_RNIRSTD1[7]          ORCALUT4     Z        Out     1.089     12.840      -
553 
 
554 
 
555 
cpu0.alu.q_out[7]                          ORCALUT4     Z        Out     0.449     13.289      -
556 
alu_o_result[7]                            Net          -        -       -         -           1
557 
 
558 
cpu0.alu.alu8.l8.datamux_o_dest[7]         PFUMX        Z        Out     0.286     13.575      -
559 
datamux_o_dest[7]                          Net          -        -       -         -           2
560 
cpu0.regs.path_left_data_RNIOEVA1[7]       ORCALUT4     B        In      0.000     13.575      -
561 
cpu0.regs.path_left_data_RNIOEVA1[7]       ORCALUT4     Z        Out     1.273     14.848      -
562 
left_1[7]                                  Net          -        -       -         -           9
563 
cpu0.regs.SS_16_0[7]                       ORCALUT4     B        In      0.000     14.848      -
564 
cpu0.regs.SS_16_0[7]                       ORCALUT4     Z        Out     1.017     15.865      -
565 
N_250                                      Net          -        -       -         -           1
566 
cpu0.regs.SS_16[7]                         ORCALUT4     A        In      0.000     15.865      -
567 
cpu0.regs.SS_16[7]                         ORCALUT4     Z        Out     1.017     16.882      -
568 
SS_16[7]                                   Net          -        -       -         -           1
569 
cpu0.regs.SS_228_m3                        ORCALUT4     B        In      0.000     16.882      -
570 
cpu0.regs.SS_228_m3                        ORCALUT4     Z        Out     1.017     17.898      -
571 
SS_228_i1_mux                              Net          -        -       -         -           1
572 
cpu0.regs.SS_cry_0[6]                      CCU2D        C1       In      0.000     17.898      -
573 
 
574 
 
575 
 
576 
cpu0.regs.SS_cry_0[8]                      CCU2D        COUT     Out     0.143     19.586      -
577 
SS_cry[9]                                  Net          -        -       -         -           1
578 
 
579 
 
580 
SS_cry[11]                                 Net          -        -       -         -           1
581 
cpu0.regs.SS_cry_0[12]                     CCU2D        CIN      In      0.000     19.729      -
582 
cpu0.regs.SS_cry_0[12]                     CCU2D        COUT     Out     0.143     19.871      -
583 
SS_cry[13]                                 Net          -        -       -         -           1
584 
cpu0.regs.SS_cry_0[14]                     CCU2D        CIN      In      0.000     19.871      -
585 
 
586 
SS_s[15]                                   Net          -        -       -         -           1
587 
cpu0.regs.SS[15]                           FD1P3AX      D        In      0.000     21.420      -
588 
=========================================================================================================
589 
 
590 
 
591 
 
592 
##### END OF TIMING REPORT #####]
593 
 
594 
---------------------------------------
595 
 
596 
Part: lcmxo2_7000he-4
597 
 
598 
Register bits: 439 of 6864 (6%)
599 
PIC Latch:       0
600 
I/O cells:       49
601 
Block Rams : 10 of 26 (38%)
602 
 
603 
 
604 
Details:
605 
CCU2D:          196
606 
DP8KC:          10
607 
FD1P3AX:        393
608 
FD1P3DX:        6
609 
FD1S3AX:        28
610 
FD1S3IX:        2
611 
GSR:            1
612 
IB:             1
613 
INV:            19
614 
L6MUX21:        26
615 
OB:             40
616 
OBZ:            8
617 
OFS1P3DX:       9
618 
OFS1P3IX:       1
619 
ORCALUT4:       2024
620 
PFUMX:          222
621 
PUR:            1
622 
VHI:            13
623 
VLO:            20
624 
false:          1
625 
true:           8
626 
Mapper successful!
627 
 
628 
At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)
629 
 
630 
Process took 0h:00m:14s realtime, 0h:00m:14s cputime
631 
# Mon Jan  6 06:54:29 2014
632 
 
633 
###########################################################]
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