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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_tw1.html] - Blame information for rev 9

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<HTML>
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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</HEAD>
9 
<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
10 
 
11 
Loading design for application trce from file P6809_P6809_map.ncd.
12 
Design name: CC3_top
13 
NCD version: 3.2
14 
Vendor:      LATTICE
15 
Device:      LCMXO2-7000HE
16 
Package:     TQFP144
17 
Performance: 4
18 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
19 
Package Status:                     Final          Version 1.36
20 
Performance Hardware Data Status:   Final)         Version 23.4
21 
Setup and Hold Report
22 
 
23 
--------------------------------------------------------------------------------
24 
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>
25 
Mon Jan  6 06:54:33 2014
26 
 
27 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
28 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
29 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
30 
Copyright (c) 2001 Agere Systems   All rights reserved.
31 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
32 
 
33 
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
34 
------------------
35 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
36 
Design file:     P6809_P6809_map.ncd
37 
Preference file: P6809_P6809.prf
38 
Device,speed:    LCMXO2-7000HE,4
39 
Report level:    verbose report, limited to 1 item per preference
40 
--------------------------------------------------------------------------------
41 
 
42 
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
43 
 
44 
<FONT COLOR=red><LI><A href='#map_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (672 errors)</FONT></A></LI>
45 
</FONT>            4096 items scored, 672 timing errors detected.
46 
Warning:  37.396MHz is the maximum frequency for this preference.
47 
 
48 
BLOCK ASYNCPATHS
49 
BLOCK RESETPATHS
50 
--------------------------------------------------------------------------------
51 
 
52 
 
53 
 
54 
================================================================================
55 
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
56 
            4096 items scored, 672 timing errors detected.
57 
--------------------------------------------------------------------------------
58 
 
59 
 
60 
Error: The following path exceeds requirements by 1.741ns
61 
 
62 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
63 
 
64 
   Source:         FF         Q              cpu0/alu/rb_in[0]  (from cpu_clkgen +)
65 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
66 
 
67 
 
68 
 
69 
 Constraint Details:
70 
 
71 
 
72 
     25.000ns delay constraint less
73 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.741ns
74 
 
75 
 Physical Path Details:
76 
 
77 
      Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
78 
 
79 
   Name    Fanout   Delay (ns)          Site               Resource
80 
REG_DEL     ---     0.452 *SLICE_229.CLK to */SLICE_229.Q0 cpu0/SLICE_229 (from cpu_clkgen)
81 
ROUTE        26   e 1.234 */SLICE_229.Q0 to *SLICE_1227.A1 cpu0/alu/rb_in[0]
82 
CTOF_DEL    ---     0.495 *SLICE_1227.A1 to *SLICE_1227.F1 cpu0/alu/SLICE_1227
83 
ROUTE         1   e 1.234 *SLICE_1227.F1 to */SLICE_167.A1 cpu0/alu/alu8/a8/rb_in_i[0]
84 
C1TOFCO_DE  ---     0.889 */SLICE_167.A1 to *SLICE_167.FCO cpu0/alu/alu8/a8/SLICE_167
85 
ROUTE         1   e 0.001 *SLICE_167.FCO to *SLICE_166.FCI cpu0/alu/alu8/a8/un8_q_out_cry_0
86 
FCITOF0_DE  ---     0.585 *SLICE_166.FCI to */SLICE_166.F0 cpu0/alu/alu8/a8/SLICE_166
87 
ROUTE         1   e 1.234 */SLICE_166.F0 to *SLICE_1216.A1 cpu0/alu/alu8/a8/un8_q_out[1]
88 
CTOF_DEL    ---     0.495 *SLICE_1216.A1 to *SLICE_1216.F1 cpu0/alu/SLICE_1216
89 
ROUTE         1   e 1.234 *SLICE_1216.F1 to */SLICE_176.C0 cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO
90 
C0TOFCO_DE  ---     1.023 */SLICE_176.C0 to *SLICE_176.FCO cpu0/alu/alu8/a8/SLICE_176
91 
ROUTE         1   e 0.001 *SLICE_176.FCO to *SLICE_175.FCI cpu0/alu/alu8/a8/q_out_2_cry_2
92 
FCITOFCO_D  ---     0.162 *SLICE_175.FCI to *SLICE_175.FCO cpu0/alu/alu8/a8/SLICE_175
93 
 
94 
FCITOFCO_D  ---     0.162 *SLICE_174.FCI to *SLICE_174.FCO cpu0/alu/alu8/a8/SLICE_174
95 
ROUTE         1   e 0.001 *SLICE_174.FCO to *SLICE_173.FCI cpu0/alu/alu8/a8/q_out_2_cry_6
96 
FCITOF0_DE  ---     0.585 *SLICE_173.FCI to */SLICE_173.F0 cpu0/alu/alu8/a8/SLICE_173
97 
ROUTE         1   e 1.234 */SLICE_173.F0 to */SLICE_639.A1 cpu0/alu/alu8/a8/N_2388
98 
CTOF_DEL    ---     0.495 */SLICE_639.A1 to */SLICE_639.F1 cpu0/alu/alu8/a8/SLICE_639
99 
ROUTE         2   e 1.234 */SLICE_639.F1 to */SLICE_561.A0 cpu0/alu/alu8/arith_q[7]
100 
CTOOFX_DEL  ---     0.721 */SLICE_561.A0 to *LICE_561.OFX0 cpu0/alu/alu8/q_out_4[7]/SLICE_561
101 
ROUTE         2   e 1.234 *LICE_561.OFX0 to *SLICE_1235.A0 cpu0/alu/alu8/N_160
102 
CTOF_DEL    ---     0.495 *SLICE_1235.A0 to *SLICE_1235.F0 cpu0/alu/alu8/SLICE_1235
103 
ROUTE         2   e 1.234 *SLICE_1235.F0 to */SLICE_542.A1 cpu0/alu/q8_out[7]
104 
CTOOFX_DEL  ---     0.721 */SLICE_542.A1 to *LICE_542.OFX0 cpu0/alu/alu8/l8/datamux_o_dest[7]/SLICE_542
105 
 
106 
CTOF_DEL    ---     0.495 */SLICE_361.B1 to */SLICE_361.F1 cpu0/regs/SLICE_361
107 
ROUTE         9   e 1.234 */SLICE_361.F1 to *SLICE_1126.B0 cpu0/regs/left_1[7]
108 
CTOF_DEL    ---     0.495 *SLICE_1126.B0 to *SLICE_1126.F0 cpu0/regs/SLICE_1126
109 
 
110 
CTOF_DEL    ---     0.495 */SLICE_902.A1 to */SLICE_902.F1 cpu0/regs/SLICE_902
111 
ROUTE         1   e 0.480 */SLICE_902.F1 to */SLICE_902.B0 cpu0/regs/SU_16[7]
112 
CTOF_DEL    ---     0.495 */SLICE_902.B0 to */SLICE_902.F0 cpu0/regs/SLICE_902
113 
ROUTE         1   e 1.234 */SLICE_902.F0 to *s/SLICE_68.C1 cpu0/regs/SU_212_i1_mux
114 
C1TOFCO_DE  ---     0.889 *s/SLICE_68.C1 to */SLICE_68.FCO cpu0/regs/SLICE_68
115 
 
116 
FCITOFCO_D  ---     0.162 */SLICE_67.FCI to */SLICE_67.FCO cpu0/regs/SLICE_67
117 
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI cpu0/regs/SU_cry[9]
118 
FCITOFCO_D  ---     0.162 */SLICE_66.FCI to */SLICE_66.FCO cpu0/regs/SLICE_66
119 
ROUTE         1   e 0.001 */SLICE_66.FCO to */SLICE_65.FCI cpu0/regs/SU_cry[11]
120 
FCITOFCO_D  ---     0.162 */SLICE_65.FCI to */SLICE_65.FCO cpu0/regs/SLICE_65
121 
ROUTE         1   e 0.001 */SLICE_65.FCO to */SLICE_64.FCI cpu0/regs/SU_cry[13]
122 
FCITOF1_DE  ---     0.643 */SLICE_64.FCI to *s/SLICE_64.F1 cpu0/regs/SLICE_64
123 
ROUTE         1   e 0.001 *s/SLICE_64.F1 to */SLICE_64.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
124 
 
125 
                   26.575   (42.4% logic, 57.6% route), 22 logic levels.
126 
 
127 
Warning:  37.396MHz is the maximum frequency for this preference.
128 
 
129 
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
130 
 
131 
----------------------------------------------------------------------------
132 
Preference                              |   Constraint|       Actual|Levels
133 
----------------------------------------------------------------------------
134 
 
135 
 
136 
 
137 
                                        |             |             |
138 
----------------------------------------------------------------------------
139 
 
140 
 
141 
 
142 
 
143 
----------------------------------------------------------------------------
144 
 
145 
----------------------------------------------------------------------------
146 
 
147 
                                        |        |        |
148 
cpu0/alu/alu8/N_160                     |       2|     550|     81.85%
149 
 
150 
cpu0/alu/alu8/a8/N_2388                 |       1|     550|     81.85%
151 
 
152 
cpu0/alu/alu8/arith_q[7]                |       2|     550|     81.85%
153 
 
154 
cpu0/regs/left_1[7]                     |       9|     550|     81.85%
155 
                                        |        |        |
156 
cpu0/datamux_o_dest[7]                  |       2|     550|     81.85%
157 
 
158 
cpu0/alu/alu8/a8/q_out_2_cry_6          |       1|     454|     67.56%
159 
 
160 
cpu0/alu/alu8/a8/q_out_2_cry_4          |       1|     336|     50.00%
161 
 
162 
cpu0/alu/alu8/a8/un8_q_out_cry_2        |       1|     334|     49.70%
163 
                                        |        |        |
164 
cpu0/regs/SS_cry[7]                     |       1|     323|     48.07%
165 
                                        |        |        |
166 
cpu0/regs/SU_cry[7]                     |       1|     323|     48.07%
167 
                                        |        |        |
168 
cpu0/regs/N_250                         |       1|     275|     40.92%
169 
                                        |        |        |
170 
cpu0/regs/N_286                         |       1|     275|     40.92%
171 
                                        |        |        |
172 
cpu0/regs/SS_228_i1_mux                 |       1|     275|     40.92%
173 
                                        |        |        |
174 
cpu0/regs/SS_16[7]                      |       1|     275|     40.92%
175 
                                        |        |        |
176 
cpu0/regs/SU_212_i1_mux                 |       1|     275|     40.92%
177 
                                        |        |        |
178 
cpu0/regs/SU_16[7]                      |       1|     275|     40.92%
179 
                                        |        |        |
180 
cpu0/regs/SS_cry[9]                     |       1|     267|     39.73%
181 
                                        |        |        |
182 
cpu0/regs/SU_cry[9]                     |       1|     267|     39.73%
183 
                                        |        |        |
184 
cpu0/alu/alu8/a8/un8_q_out_cry_4        |       1|     252|     37.50%
185 
                                        |        |        |
186 
cpu0/alu/alu8/a8/un8_q_out_cry_0        |       1|     220|     32.74%
187 
                                        |        |        |
188 
cpu0/alu/rb_in[0]                       |      26|     214|     31.85%
189 
                                        |        |        |
190 
cpu0/alu/alu8/a8/rb_in_i[0]             |       1|     208|     30.95%
191 
                                        |        |        |
192 
cpu0/regs/SS_cry[11]                    |       1|     203|     30.21%
193 
                                        |        |        |
194 
cpu0/regs/SU_cry[11]                    |       1|     203|     30.21%
195 
                                        |        |        |
196 
cpu0/alu/alu8/a8/rb_in_i[1]             |       1|     146|     21.73%
197 
                                        |        |        |
198 
cpu0/alu/rb_in[1]                       |      26|     146|     21.73%
199 
                                        |        |        |
200 
cpu0/alu/alu8/a8/q_out_2_cry_2          |       1|     144|     21.43%
201 
                                        |        |        |
202 
cpu0/alu/alu8/a8/q_out_2_cry_3_0_RNO    |       1|     114|     16.96%
203 
                                        |        |        |
204 
cpu0/alu/alu8/a8/un8_q_out[3]           |       1|     114|     16.96%
205 
                                        |        |        |
206 
cpu0/alu/alu8/a8/rb_in_i[2]             |       1|     112|     16.67%
207 
                                        |        |        |
208 
cpu0/alu/rb_in[2]                       |      23|     112|     16.67%
209 
 
210 
cpu0/regs/SS_cry[13]                    |       1|     112|     16.67%
211 
 
212 
cpu0/regs/SU_cry[13]                    |       1|     112|     16.67%
213 
                                        |        |        |
214 
cpu0/alu/alu8/a8/q_out_2_cry_5_0_RNO_0  |       1|     108|     16.07%
215 
                                        |        |        |
216 
cpu0/alu/alu8/a8/un8_q_out[6]           |       1|     108|     16.07%
217 
                                        |        |        |
218 
cpu0/alu/alu8/a8/q_out_2_cry_3_0_RNO_0  |       1|     106|     15.77%
219 
                                        |        |        |
220 
cpu0/alu/alu8/a8/un8_q_out[4]           |       1|     106|     15.77%
221 
                                        |        |        |
222 
 
223 
 
224 
cpu0/alu/alu8/a8/un8_q_out[5]           |       1|     104|     15.48%
225 
 
226 
cpu0/alu/alu8/a8/un8_q_out_cry_6        |       1|      96|     14.29%
227 
                                        |        |        |
228 
cpu0/alu/alu8/a8/q_out_2_cry_7_0_RNO    |       1|      96|     14.29%
229 
                                        |        |        |
230 
cpu0/alu/alu8/a8/un8_q_out[7]           |       1|      96|     14.29%
231 
                                        |        |        |
232 
cpu0/alu/alu8/a8/rb_in_i[3]             |       1|      82|     12.20%
233 
                                        |        |        |
234 
cpu0/alu/rb_in[3]                       |      24|      82|     12.20%
235 
                                        |        |        |
236 
cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO_0  |       1|      74|     11.01%
237 
                                        |        |        |
238 
cpu0/alu/alu8/a8/un8_q_out[2]           |       1|      74|     11.01%
239 
                                        |        |        |
240 
cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO    |       1|      70|     10.42%
241 
                                        |        |        |
242 
cpu0/alu/alu8/a8/un8_q_out[1]           |       1|      70|     10.42%
243 
                                        |        |        |
244 
----------------------------------------------------------------------------
245 
 
246 
 
247 
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
248 
------------------------
249 
 
250 
Found 1 clocks:
251 
 
252 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 290
253 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
254 
 
255 
 
256 
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
257 
---------------
258 
 
259 
Timing errors: 672  Score: 491074
260 
Cumulative negative slack: 491074
261 
 
262 
Constraints cover 1007472 paths, 1 nets, and 9180 connections (96.2% coverage)
263 
 
264 
--------------------------------------------------------------------------------
265 
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>
266 
Mon Jan  6 06:54:33 2014
267 
 
268 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
269 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
270 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
271 
Copyright (c) 2001 Agere Systems   All rights reserved.
272 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
273 
 
274 
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
275 
------------------
276 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
277 
Design file:     P6809_P6809_map.ncd
278 
Preference file: P6809_P6809.prf
279 
Device,speed:    LCMXO2-7000HE,M
280 
Report level:    verbose report, limited to 1 item per preference
281 
--------------------------------------------------------------------------------
282 
 
283 
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
284 
 
285 
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI>            4096 items scored, 0 timing errors detected.
286 
 
287 
BLOCK ASYNCPATHS
288 
BLOCK RESETPATHS
289 
--------------------------------------------------------------------------------
290 
 
291 
 
292 
 
293 
================================================================================
294 
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
295 
            4096 items scored, 0 timing errors detected.
296 
--------------------------------------------------------------------------------
297 
 
298 
 
299 
Passed: The following path meets requirements by 0.443ns
300 
 
301 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
302 
 
303 
   Source:         FF         Q              cpu_clk  (from cpu_clkgen +)
304 
   Destination:    FF         Data in        cpu_clk  (to cpu_clkgen +)
305 
 
306 
   Delay:               0.430ns  (53.5% logic, 46.5% route), 2 logic levels.
307 
 
308 
 Constraint Details:
309 
 
310 
      0.430ns physical path delay SLICE_383 to SLICE_383 meets
311 
     -0.013ns DIN_HLD and
312 
      0.000ns delay constraint requirement (totaling -0.013ns) by 0.443ns
313 
 
314 
 Physical Path Details:
315 
 
316 
      Data path SLICE_383 to SLICE_383:
317 
 
318 
   Name    Fanout   Delay (ns)          Site               Resource
319 
REG_DEL     ---     0.131  SLICE_383.CLK to   SLICE_383.Q0 SLICE_383 (from cpu_clkgen)
320 
ROUTE       101   e 0.199   SLICE_383.Q0 to   SLICE_383.A0 cpu_clk
321 
CTOF_DEL    ---     0.099   SLICE_383.A0 to   SLICE_383.F0 SLICE_383
322 
ROUTE         1   e 0.001   SLICE_383.F0 to  SLICE_383.DI0 cpu_clk_i (to cpu_clkgen)
323 
                  --------
324 
                    0.430   (53.5% logic, 46.5% route), 2 logic levels.
325 
 
326 
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
327 
--------------
328 
 
329 
 
330 
----------------------------------------------------------------------------
331 
                                        |             |             |
332 
 
333 
MHz ;                                   |            -|            -|   2
334 
 
335 
----------------------------------------------------------------------------
336 
 
337 
 
338 
 
339 
 
340 
 
341 
 
342 
------------------------
343 
 
344 
 
345 
 
346 
 
347 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
348 
 
349 
 
350 
 
351 
---------------
352 
 
353 
Timing errors: 0  Score: 0
354 
Cumulative negative slack: 0
355 
 
356 
 
357 
 
358 
 
359 
 
360 
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
361 
---------------
362 
 
363 
Timing errors: 672 (setup), 0 (hold)
364 
Score: 491074 (setup), 0 (hold)
365 
 
366 
--------------------------------------------------------------------------------
367 
 
368 
--------------------------------------------------------------------------------
369 
 
370 
 
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