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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_twr.html] - Blame information for rev 12

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1 12 ale500 
<HTML>
2 
<HEAD><TITLE>Lattice TRACE Report</TITLE>
3 
<STYLE TYPE="text/css">
4 
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</HEAD>
9 
<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
10 
 
11 
Loading design for application trce from file p6809_p6809.ncd.
12 
Design name: CC3_top
13 
NCD version: 3.2
14 
Vendor:      LATTICE
15 
Device:      LCMXO2-7000HE
16 
Package:     TQFP144
17 
Performance: 4
18 
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.
19 
Package Status:                     Final          Version 1.36
20 
Performance Hardware Data Status:   Final)         Version 23.4
21 
Setup and Hold Report
22 
 
23 
--------------------------------------------------------------------------------
24 
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.1.0.96</big></U></B>
25 
Sun Jul 06 07:47:15 2014
26 
 
27 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
28 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
29 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
30 
Copyright (c) 2001 Agere Systems   All rights reserved.
31 
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.
32 
 
33 
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
34 
------------------
35 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prf
36 
Design file:     p6809_p6809.ncd
37 
Preference file: p6809_p6809.prf
38 
Device,speed:    LCMXO2-7000HE,4
39 
Report level:    verbose report, limited to 10 items per preference
40 
--------------------------------------------------------------------------------
41 
 
42 
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
43 
 
44 
<FONT COLOR=red><LI><A href='#par_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "clk40_i_c" 111.645000 MHz (4096 errors)</FONT></A></LI>
45 
</FONT>            4096 items scored, 4096 timing errors detected.
46 
Warning:  29.641MHz is the maximum frequency for this preference.
47 
 
48 
Report Type:     based on TRACE automatically generated preferences
49 
BLOCK ASYNCPATHS
50 
BLOCK RESETPATHS
51 
--------------------------------------------------------------------------------
52 
 
53 
 
54 
 
55 
================================================================================
56 
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
57 
            4096 items scored, 4096 timing errors detected.
58 
--------------------------------------------------------------------------------
59 
 
60 
 
61 
Error: The following path exceeds requirements by 24.781ns
62 
 
63 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
64 
 
65 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
66 
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to clk40_i_c +)
67 
 
68 
   Delay:              33.571ns  (26.7% logic, 73.3% route), 18 logic levels.
69 
 
70 
 Constraint Details:
71 
 
72 
     33.571ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_64 exceeds
73 
      8.956ns delay constraint less
74 
      0.000ns skew and
75 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.781ns
76 
 
77 
 Physical Path Details:
78 
 
79 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_64:
80 
 
81 
   Name    Fanout   Delay (ns)          Site               Resource
82 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
83 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
84 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
85 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
86 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
87 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
88 12 ale500 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
89 
 
90 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
91 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
92 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
93 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
94 
 
95 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
96 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
97 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
98 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
99 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
100 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
101 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
102 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
103 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
104 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
105 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
106 
 
107 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
108 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
109 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
110 
 
111 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
112 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
113 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
114 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
115 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
116 
 
117 
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
118 
                  --------
119 
                   33.571   (26.7% logic, 73.3% route), 18 logic levels.
120 
 
121 
 Clock Skew Details:
122 
 
123 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
124 
 
125 
 
126 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
127 
 
128 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
129 
 
130 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
131 
 
132 
   Name    Fanout   Delay (ns)          Site               Resource
133 
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
134 
                  --------
135 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
136 
 
137 
 
138 
 
139 
 
140 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
141 
 
142 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
143 
 
144 
 
145 
   Delay:              33.513ns  (26.6% logic, 73.4% route), 18 logic levels.
146 
 
147 
 Constraint Details:
148 
 
149 
     33.513ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_64 exceeds
150 
      8.956ns delay constraint less
151 
 
152 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.723ns
153 
 
154 
 Physical Path Details:
155 
 
156 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_64:
157 
 
158 
   Name    Fanout   Delay (ns)          Site               Resource
159 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
160 
 
161 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
162 
 
163 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
164 
 
165 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
166 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
167 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
168 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
169 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
170 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
171 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
172 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
173 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
174 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
175 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
176 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
177 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
178 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
179 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
180 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
181 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
182 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
183 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
184 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
185 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
186 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
187 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
188 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
189 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
190 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
191 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
192 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
193 
FCITOF0_DE  ---     0.585    R11C13A.FCI to     R11C13A.F0 cpu0/regs/SLICE_64
194 
ROUTE         1     0.000     R11C13A.F0 to    R11C13A.DI0 cpu0/regs/SS_s[14] (to clk40_i_c)
195 
                  --------
196 
                   33.513   (26.6% logic, 73.4% route), 18 logic levels.
197 
 
198 
 Clock Skew Details:
199 
 
200 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
201 
 
202 
   Name    Fanout   Delay (ns)          Site               Resource
203 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
204 
 
205 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
206 
 
207 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
208 
 
209 
   Name    Fanout   Delay (ns)          Site               Resource
210 
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
211 
                  --------
212 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
213 
 
214 
 
215 
 
216 
 
217 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
218 
 
219 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
220 
 
221 
 
222 
   Delay:              33.409ns  (26.3% logic, 73.7% route), 17 logic levels.
223 
 
224 
 Constraint Details:
225 
 
226 
     33.409ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_65 exceeds
227 
      8.956ns delay constraint less
228 
 
229 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.619ns
230 
 
231 
 Physical Path Details:
232 
 
233 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_65:
234 
 
235 
   Name    Fanout   Delay (ns)          Site               Resource
236 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
237 
 
238 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
239 
 
240 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
241 
 
242 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
243 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
244 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
245 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
246 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
247 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
248 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
249 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
250 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
251 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
252 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
253 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
254 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
255 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
256 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
257 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
258 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
259 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
260 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
261 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
262 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
263 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
264 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
265 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
266 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
267 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
268 
FCITOF1_DE  ---     0.643    R11C12D.FCI to     R11C12D.F1 cpu0/regs/SLICE_65
269 
ROUTE         1     0.000     R11C12D.F1 to    R11C12D.DI1 cpu0/regs/SS_s[13] (to clk40_i_c)
270 
                  --------
271 
                   33.409   (26.3% logic, 73.7% route), 17 logic levels.
272 
 
273 
 Clock Skew Details:
274 
 
275 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
276 
 
277 
   Name    Fanout   Delay (ns)          Site               Resource
278 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
279 
                  --------
280 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
281 
 
282 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_65:
283 
 
284 
   Name    Fanout   Delay (ns)          Site               Resource
285 
 
286 
                  --------
287 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
288 
 
289 
 
290 
 
291 
 
292 
 
293 
 
294 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
295 
   Destination:    FF         Data in        cpu0/regs/SS[12]  (to clk40_i_c +)
296 
 
297 
 
298 
 
299 
 Constraint Details:
300 
 
301 
     33.351ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_65 exceeds
302 
 
303 
      0.000ns skew and
304 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.561ns
305 
 
306 
 Physical Path Details:
307 
 
308 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_65:
309 
 
310 
   Name    Fanout   Delay (ns)          Site               Resource
311 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
312 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
313 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
314 
 
315 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
316 
 
317 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
318 
 
319 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
320 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
321 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
322 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
323 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
324 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
325 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
326 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
327 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
328 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
329 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
330 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
331 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
332 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
333 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
334 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
335 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
336 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
337 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
338 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
339 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
340 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
341 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
342 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
343 
FCITOF0_DE  ---     0.585    R11C12D.FCI to     R11C12D.F0 cpu0/regs/SLICE_65
344 
ROUTE         1     0.000     R11C12D.F0 to    R11C12D.DI0 cpu0/regs/SS_s[12] (to clk40_i_c)
345 
                  --------
346 
                   33.351   (26.2% logic, 73.8% route), 17 logic levels.
347 
 
348 
 Clock Skew Details:
349 
 
350 
      Source Clock Path clk40_i to cpu0/SLICE_1217:
351 
 
352 
   Name    Fanout   Delay (ns)          Site               Resource
353 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
354 
                  --------
355 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
356 
 
357 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_65:
358 
 
359 
   Name    Fanout   Delay (ns)          Site               Resource
360 
 
361 
                  --------
362 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
363 
 
364 
 
365 
 
366 
 
367 
 
368 
 
369 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
370 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to clk40_i_c +)
371 
 
372 
 
373 
 
374 
 Constraint Details:
375 
 
376 
     32.909ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_55 exceeds
377 
 
378 
      0.000ns skew and
379 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 24.119ns
380 
 
381 
 Physical Path Details:
382 
 
383 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_55:
384 
 
385 
   Name    Fanout   Delay (ns)          Site               Resource
386 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
387 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
388 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
389 
 
390 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
391 
 
392 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
393 
 
394 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
395 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
396 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
397 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
398 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
399 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
400 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
401 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
402 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
403 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
404 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
405 
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
406 
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
407 
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
408 
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
409 
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
410 
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
411 
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
412 
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
413 
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
414 
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
415 
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
416 
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
417 
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
418 
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
419 
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
420 
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
421 
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
422 
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
423 
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
424 
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
425 
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
426 
FCITOFCO_D  ---     0.162    R12C10D.FCI to    R12C10D.FCO cpu0/regs/SLICE_56
427 
ROUTE         1     0.000    R12C10D.FCO to    R12C11A.FCI cpu0/regs/SU_cry[13]
428 
FCITOF1_DE  ---     0.643    R12C11A.FCI to     R12C11A.F1 cpu0/regs/SLICE_55
429 
ROUTE         1     0.000     R12C11A.F1 to    R12C11A.DI1 cpu0/regs/SU_s[15] (to clk40_i_c)
430 
                  --------
431 
 
432 
 
433 
 
434 
 
435 
 
436 
 
437 
   Name    Fanout   Delay (ns)          Site               Resource
438 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
439 
                  --------
440 
 
441 
 
442 
 
443 
 
444 
   Name    Fanout   Delay (ns)          Site               Resource
445 
ROUTE       318     2.399       27.PADDI to    R12C11A.CLK clk40_i_c
446 
                  --------
447 
 
448 
 
449 
 
450 
 
451 
 
452 
 
453 
 
454 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
455 
 
456 
 
457 
 
458 
 
459 
 
460 
 
461 
     32.851ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_55 exceeds
462 
      8.956ns delay constraint less
463 
      0.000ns skew and
464 
 
465 
 
466 
 
467 
 
468 
 
469 
 
470 
   Name    Fanout   Delay (ns)          Site               Resource
471 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
472 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
473 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
474 
ROUTE        13     2.235     R18C26B.F1 to     R19C25B.A1 cpu0/state133_3
475 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
476 
ROUTE         1     0.436     R19C25B.F1 to     R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
477 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
478 
ROUTE         2     1.343     R19C25B.F0 to     R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
479 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
480 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
481 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
482 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
483 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
484 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
485 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
486 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
487 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
488 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
489 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
490 
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
491 
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
492 
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
493 
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
494 
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
495 
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
496 
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
497 
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
498 
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
499 
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
500 
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
501 
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
502 
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
503 
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
504 
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
505 
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
506 
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
507 
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
508 
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
509 
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
510 
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
511 
FCITOFCO_D  ---     0.162    R12C10D.FCI to    R12C10D.FCO cpu0/regs/SLICE_56
512 
ROUTE         1     0.000    R12C10D.FCO to    R12C11A.FCI cpu0/regs/SU_cry[13]
513 
FCITOF0_DE  ---     0.585    R12C11A.FCI to     R12C11A.F0 cpu0/regs/SLICE_55
514 
ROUTE         1     0.000     R12C11A.F0 to    R12C11A.DI0 cpu0/regs/SU_s[14] (to clk40_i_c)
515 
                  --------
516 
 
517 
 
518 
 
519 
 
520 
 
521 
 
522 
   Name    Fanout   Delay (ns)          Site               Resource
523 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
524 
                  --------
525 
 
526 
 
527 
 
528 
 
529 
   Name    Fanout   Delay (ns)          Site               Resource
530 
ROUTE       318     2.399       27.PADDI to    R12C11A.CLK clk40_i_c
531 
                  --------
532 
 
533 
 
534 
 
535 
 
536 
 
537 
 
538 
 
539 
   Source:         FF         Q              cpu0/k_opcode[5]  (from clk40_i_c +)
540 
 
541 
 
542 
 
543 
 
544 
 
545 
 
546 
     32.761ns physical path delay cpu0/SLICE_1144 to cpu0/regs/SLICE_64 exceeds
547 
      8.956ns delay constraint less
548 
      0.000ns skew and
549 
 
550 
 
551 
 
552 
 
553 
 
554 
 
555 
   Name    Fanout   Delay (ns)          Site               Resource
556 
REG_DEL     ---     0.452    R12C21A.CLK to     R12C21A.Q1 cpu0/SLICE_1144 (from clk40_i_c)
557 
ROUTE        52     4.508     R12C21A.Q1 to     R19C22A.A0 cpu0/k_opcode[5]
558 
CTOF_DEL    ---     0.495     R19C22A.A0 to     R19C22A.F0 cpu0/SLICE_772
559 
ROUTE         2     1.308     R19C22A.F0 to     R18C24A.A0 cpu0/un1_k_opcode_3_4
560 
CTOF_DEL    ---     0.495     R18C24A.A0 to     R18C24A.F0 cpu0/dec_regs/SLICE_1118
561 
ROUTE         1     0.693     R18C24A.F0 to     R18C24B.B1 cpu0/dec_regs/path_left_addr79
562 
CTOF_DEL    ---     0.495     R18C24B.B1 to     R18C24B.F1 cpu0/dec_regs/SLICE_771
563 
ROUTE         1     0.964     R18C24B.F1 to     R17C24A.A1 cpu0/dec_regs/un1_path_left_addr75_1_0
564 
CTOF_DEL    ---     0.495     R17C24A.A1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
565 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
566 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
567 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
568 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
569 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
570 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
571 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
572 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
573 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
574 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
575 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
576 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
577 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
578 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
579 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
580 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
581 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
582 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
583 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
584 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
585 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
586 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
587 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
588 
FCITOF1_DE  ---     0.643    R11C13A.FCI to     R11C13A.F1 cpu0/regs/SLICE_64
589 
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
590 
                  --------
591 
                   32.761   (25.8% logic, 74.2% route), 17 logic levels.
592 
 
593 
 Clock Skew Details:
594 
 
595 
      Source Clock Path clk40_i to cpu0/SLICE_1144:
596 
 
597 
   Name    Fanout   Delay (ns)          Site               Resource
598 
ROUTE       318     2.399       27.PADDI to    R12C21A.CLK clk40_i_c
599 
                  --------
600 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
601 
 
602 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
603 
 
604 
   Name    Fanout   Delay (ns)          Site               Resource
605 
 
606 
                  --------
607 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
608 
 
609 
 
610 
 
611 
 
612 
 
613 
 
614 
   Source:         FF         Q              cpu0/k_opcode[7]  (from clk40_i_c +)
615 
   Destination:    FF         Data in        cpu0/regs/SU[13]  (to clk40_i_c +)
616 
 
617 
 
618 
 
619 
 Constraint Details:
620 
 
621 
     32.747ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_56 exceeds
622 
 
623 
      0.000ns skew and
624 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.957ns
625 
 
626 
 Physical Path Details:
627 
 
628 
      Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_56:
629 
 
630 
   Name    Fanout   Delay (ns)          Site               Resource
631 
REG_DEL     ---     0.452    R12C21C.CLK to     R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
632 
ROUTE        42     3.151     R12C21C.Q1 to     R18C26B.C1 cpu0/k_opcode[7]
633 
CTOF_DEL    ---     0.495     R18C26B.C1 to     R18C26B.F1 cpu0/SLICE_726
634 
 
635 
CTOF_DEL    ---     0.495     R19C25B.A1 to     R19C25B.F1 cpu0/dec_regs/SLICE_659
636 
 
637 
CTOF_DEL    ---     0.495     R19C25B.C0 to     R19C25B.F0 cpu0/dec_regs/SLICE_659
638 
 
639 
CTOF_DEL    ---     0.495     R18C24D.B1 to     R18C24D.F1 cpu0/SLICE_766
640 
ROUTE         1     0.623     R18C24D.F1 to     R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
641 
CTOF_DEL    ---     0.495     R17C24A.D1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
642 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
643 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
644 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
645 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
646 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
647 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
648 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
649 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
650 
ROUTE        25     2.485     R18C22B.F1 to     R10C25C.B1 cpu0/dec_o_alu_size
651 
CTOOFX_DEL  ---     0.721     R10C25C.B1 to   R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
652 
ROUTE         2     1.513   R10C25C.OFX0 to      R9C23D.C0 cpu0/datamux_o_dest[2]
653 
CTOF_DEL    ---     0.495      R9C23D.C0 to      R9C23D.F0 cpu0/regs/SLICE_895
654 
ROUTE         9     2.274      R9C23D.F0 to     R10C16D.A0 cpu0/regs/left_1[2]
655 
CTOF_DEL    ---     0.495     R10C16D.A0 to     R10C16D.F0 cpu0/regs/SLICE_1219
656 
ROUTE         1     1.801     R10C16D.F0 to     R10C10A.A1 cpu0/regs/N_283
657 
CTOF_DEL    ---     0.495     R10C10A.A1 to     R10C10A.F1 cpu0/regs/SLICE_909
658 
ROUTE         1     0.693     R10C10A.F1 to     R10C10A.B0 cpu0/regs/SU_16[2]
659 
CTOF_DEL    ---     0.495     R10C10A.B0 to     R10C10A.F0 cpu0/regs/SLICE_909
660 
ROUTE         1     1.620     R10C10A.F0 to      R12C9C.C0 cpu0/regs/SU_201_i1_mux
661 
C0TOFCO_DE  ---     1.023      R12C9C.C0 to     R12C9C.FCO cpu0/regs/SLICE_61
662 
ROUTE         1     0.000     R12C9C.FCO to     R12C9D.FCI cpu0/regs/SU_cry[3]
663 
FCITOFCO_D  ---     0.162     R12C9D.FCI to     R12C9D.FCO cpu0/regs/SLICE_60
664 
ROUTE         1     0.000     R12C9D.FCO to    R12C10A.FCI cpu0/regs/SU_cry[5]
665 
FCITOFCO_D  ---     0.162    R12C10A.FCI to    R12C10A.FCO cpu0/regs/SLICE_59
666 
ROUTE         1     0.000    R12C10A.FCO to    R12C10B.FCI cpu0/regs/SU_cry[7]
667 
FCITOFCO_D  ---     0.162    R12C10B.FCI to    R12C10B.FCO cpu0/regs/SLICE_58
668 
ROUTE         1     0.000    R12C10B.FCO to    R12C10C.FCI cpu0/regs/SU_cry[9]
669 
FCITOFCO_D  ---     0.162    R12C10C.FCI to    R12C10C.FCO cpu0/regs/SLICE_57
670 
ROUTE         1     0.000    R12C10C.FCO to    R12C10D.FCI cpu0/regs/SU_cry[11]
671 
FCITOF1_DE  ---     0.643    R12C10D.FCI to     R12C10D.F1 cpu0/regs/SLICE_56
672 
ROUTE         1     0.000     R12C10D.F1 to    R12C10D.DI1 cpu0/regs/SU_s[13] (to clk40_i_c)
673 
                  --------
674 
                   32.747   (29.9% logic, 70.1% route), 21 logic levels.
675 
 
676 
 
677 
 
678 
 
679 
 
680 
 
681 
ROUTE       318     2.399       27.PADDI to    R12C21C.CLK clk40_i_c
682 
                  --------
683 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
684 
 
685 
 
686 
 
687 
 
688 
ROUTE       318     2.399       27.PADDI to    R12C10D.CLK clk40_i_c
689 
                  --------
690 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
691 
 
692 
 
693 
 
694 
 
695 
 
696 
 
697 
 
698 
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to clk40_i_c +)
699 
 
700 
 
701 
 
702 
 
703 
 
704 
 
705 
      8.956ns delay constraint less
706 
      0.000ns skew and
707 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.922ns
708 
 
709 
 
710 
 
711 
 
712 
 
713 
 
714 
REG_DEL     ---     0.452    R14C14A.CLK to     R14C14A.Q1 SLICE_284 (from clk40_i_c)
715 
ROUTE        26     3.767     R14C14A.Q1 to      R5C14B.A1 cpu0/k_ind_ea[7]
716 
CTOF_DEL    ---     0.495      R5C14B.A1 to      R5C14B.F1 cpu0/regs/ea/SLICE_877
717 
ROUTE        18     1.450      R5C14B.F1 to      R5C15D.A1 cpu0/regs/ea/N_62
718 
CTOF_DEL    ---     0.495      R5C15D.A1 to      R5C15D.F1 cpu0/regs/ea/SLICE_668
719 
ROUTE        18     1.939      R5C15D.F1 to      R6C15B.D1 cpu0/regs/ea/N_107
720 
CTOF_DEL    ---     0.495      R6C15B.D1 to      R6C15B.F1 cpu0/regs/ea/SLICE_876
721 
ROUTE        16     2.634      R6C15B.F1 to      R8C12C.A1 cpu0/regs/ea/un1_eapostbyte_12
722 
CTOF_DEL    ---     0.495      R8C12C.A1 to      R8C12C.F1 cpu0/regs/ea/SLICE_1211
723 
ROUTE         1     1.163      R8C12C.F1 to      R8C13D.C0 cpu0/regs/ea/N_77
724 
C0TOFCO_DE  ---     1.023      R8C13D.C0 to     R8C13D.FCO cpu0/regs/ea/SLICE_51
725 
ROUTE         1     0.000     R8C13D.FCO to     R8C14A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
726 
FCITOFCO_D  ---     0.162     R8C14A.FCI to     R8C14A.FCO cpu0/regs/ea/SLICE_50
727 
ROUTE         1     0.000     R8C14A.FCO to     R8C14B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
728 
FCITOFCO_D  ---     0.162     R8C14B.FCI to     R8C14B.FCO cpu0/regs/ea/SLICE_49
729 
ROUTE         1     0.000     R8C14B.FCO to     R8C14C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
730 
FCITOF0_DE  ---     0.585     R8C14C.FCI to      R8C14C.F0 cpu0/regs/ea/SLICE_48
731 
ROUTE         4     3.207      R8C14C.F0 to      R9C22A.A1 cpu0/regs/ea/regs_o_eamem_addr[11]
732 
CTOF_DEL    ---     0.495      R9C22A.A1 to      R9C22A.F1 cpu0/regs/ea/SLICE_1071
733 
ROUTE         1     1.193      R9C22A.F1 to      R9C25A.C0 cpu0/regs/ea/N_1327
734 
CTOF_DEL    ---     0.495      R9C25A.C0 to      R9C25A.F0 cpu0/SLICE_862
735 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
736 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
737 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
738 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
739 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
740 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
741 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
742 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
743 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
744 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
745 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
746 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
747 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
748 
FCITOF1_DE  ---     0.643    R11C13A.FCI to     R11C13A.F1 cpu0/regs/SLICE_64
749 
ROUTE         1     0.000     R11C13A.F1 to    R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
750 
                  --------
751 
                   32.712   (27.6% logic, 72.4% route), 18 logic levels.
752 
 
753 
 Clock Skew Details:
754 
 
755 
      Source Clock Path clk40_i to SLICE_284:
756 
 
757 
   Name    Fanout   Delay (ns)          Site               Resource
758 
ROUTE       318     2.399       27.PADDI to    R14C14A.CLK clk40_i_c
759 
 
760 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
761 
 
762 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
763 
 
764 
   Name    Fanout   Delay (ns)          Site               Resource
765 
ROUTE       318     2.399       27.PADDI to    R11C13A.CLK clk40_i_c
766 
                  --------
767 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
768 
 
769 
 
770 
 
771 
 
772 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
773 
 
774 
   Source:         FF         Q              cpu0/k_opcode[5]  (from clk40_i_c +)
775 
 
776 
 
777 
   Delay:              32.703ns  (25.7% logic, 74.3% route), 17 logic levels.
778 
 
779 
 Constraint Details:
780 
 
781 
     32.703ns physical path delay cpu0/SLICE_1144 to cpu0/regs/SLICE_64 exceeds
782 
      8.956ns delay constraint less
783 
 
784 
      0.166ns DIN_SET requirement (totaling 8.790ns) by 23.913ns
785 
 
786 
 Physical Path Details:
787 
 
788 
      Data path cpu0/SLICE_1144 to cpu0/regs/SLICE_64:
789 
 
790 
   Name    Fanout   Delay (ns)          Site               Resource
791 
REG_DEL     ---     0.452    R12C21A.CLK to     R12C21A.Q1 cpu0/SLICE_1144 (from clk40_i_c)
792 
 
793 
CTOF_DEL    ---     0.495     R19C22A.A0 to     R19C22A.F0 cpu0/SLICE_772
794 
 
795 
CTOF_DEL    ---     0.495     R18C24A.A0 to     R18C24A.F0 cpu0/dec_regs/SLICE_1118
796 
 
797 
CTOF_DEL    ---     0.495     R18C24B.B1 to     R18C24B.F1 cpu0/dec_regs/SLICE_771
798 
ROUTE         1     0.964     R18C24B.F1 to     R17C24A.A1 cpu0/dec_regs/un1_path_left_addr75_1_0
799 
CTOF_DEL    ---     0.495     R17C24A.A1 to     R17C24A.F1 cpu0/dec_regs/SLICE_813
800 
ROUTE         6     0.675     R17C24A.F1 to     R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
801 
CTOF_DEL    ---     0.495     R15C24D.D1 to     R15C24D.F1 cpu0/dec_regs/SLICE_806
802 
ROUTE         8     0.772     R15C24D.F1 to     R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
803 
CTOF_DEL    ---     0.495     R15C24A.C1 to     R15C24A.F1 cpu0/dec_regs/SLICE_802
804 
ROUTE         5     1.441     R15C24A.F1 to     R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
805 
MTOOFX_DEL  ---     0.376     R17C25D.M0 to   R17C25D.OFX0 cpu0/dec_regs/SLICE_264
806 
ROUTE         5     1.882   R17C25D.OFX0 to     R18C22B.A1 cpu0/dec_o_left_path_addr[3]
807 
CTOF_DEL    ---     0.495     R18C22B.A1 to     R18C22B.F1 cpu0/dec_regs/SLICE_846
808 
ROUTE        25     3.725     R18C22B.F1 to      R9C25A.A0 cpu0/dec_o_alu_size
809 
CTOF_DEL    ---     0.495      R9C25A.A0 to      R9C25A.F0 cpu0/SLICE_862
810 
ROUTE         2     2.557      R9C25A.F0 to      R9C20D.B1 cpu0/datamux_o_dest[11]
811 
CTOF_DEL    ---     0.495      R9C20D.B1 to      R9C20D.F1 cpu0/regs/SLICE_945
812 
ROUTE         6     2.382      R9C20D.F1 to     R10C16B.D0 cpu0/regs/left_1[11]
813 
CTOF_DEL    ---     0.495     R10C16B.D0 to     R10C16B.F0 cpu0/regs/SLICE_1220
814 
ROUTE         1     1.450     R10C16B.F0 to     R10C12D.B1 cpu0/regs/N_256
815 
CTOF_DEL    ---     0.495     R10C12D.B1 to     R10C12D.F1 cpu0/regs/SLICE_934
816 
ROUTE         1     0.436     R10C12D.F1 to     R10C12D.C0 cpu0/regs/SS_16[11]
817 
CTOF_DEL    ---     0.495     R10C12D.C0 to     R10C12D.F0 cpu0/regs/SLICE_934
818 
ROUTE         1     1.506     R10C12D.F0 to     R11C12C.C1 cpu0/regs/SS_226_i1_mux
819 
C1TOFCO_DE  ---     0.889     R11C12C.C1 to    R11C12C.FCO cpu0/regs/SLICE_66
820 
ROUTE         1     0.000    R11C12C.FCO to    R11C12D.FCI cpu0/regs/SS_cry[11]
821 
FCITOFCO_D  ---     0.162    R11C12D.FCI to    R11C12D.FCO cpu0/regs/SLICE_65
822 
ROUTE         1     0.000    R11C12D.FCO to    R11C13A.FCI cpu0/regs/SS_cry[13]
823 
FCITOF0_DE  ---     0.585    R11C13A.FCI to     R11C13A.F0 cpu0/regs/SLICE_64
824 
ROUTE         1     0.000     R11C13A.F0 to    R11C13A.DI0 cpu0/regs/SS_s[14] (to clk40_i_c)
825 
                  --------
826 
                   32.703   (25.7% logic, 74.3% route), 17 logic levels.
827 
 
828 
 Clock Skew Details:
829 
 
830 
      Source Clock Path clk40_i to cpu0/SLICE_1144:
831 
 
832 
   Name    Fanout   Delay (ns)          Site               Resource
833 
ROUTE       318     2.399       27.PADDI to    R12C21A.CLK clk40_i_c
834 
                  --------
835 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
836 
 
837 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
838 
 
839 
   Name    Fanout   Delay (ns)          Site               Resource
840 
 
841 
                  --------
842 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
843 
 
844 
Warning:  29.641MHz is the maximum frequency for this preference.
845 
 
846 
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
847 
 
848 
----------------------------------------------------------------------------
849 
Preference                              |   Constraint|       Actual|Levels
850 
----------------------------------------------------------------------------
851 
                                        |             |             |
852 
 
853 
 
854 
                                        |             |             |
855 
 
856 
 
857 
 
858 
1 preference(marked by "*" above) not met.
859 
 
860 
 
861 
Critical Nets                           |   Loads|  Errors| % of total
862 
 
863 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/dec_o_alu_size">cpu0/dec_o_alu_size</a>                     |      25|    3143|     76.73%
864 
 
865 
cpu0/dec_o_left_path_addr[3]            |       5|    2799|     68.33%
866 
                                        |        |        |
867 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/dec_regs/un1_path_left_addr75_1">cpu0/dec_regs/un1_path_left_addr75_1</a>    |       6|    2724|     66.50%
868 
                                        |        |        |
869 
 
870 
                                        |        |        |
871 
 
872 
                                        |        |        |
873 
 
874 
                                        |        |        |
875 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/dec_regs/un1_path_left_addr75_1_4">cpu0/dec_regs/un1_path_left_addr75_1_4</a>  |       1|    1706|     41.65%
876 
                                        |        |        |
877 
cpu0/regs/SU_cry[9]                     |       1|    1283|     31.32%
878 
                                        |        |        |
879 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/dec_regs/un1_path_left_addr85_1_1_2">cpu0/dec_regs/un1_path_left_addr85_1_1_2</a>|       1|    1267|     30.93%
880 
                                        |        |        |
881 
cpu0/regs/SS_cry[11]                    |       1|    1111|     27.12%
882 
                                        |        |        |
883 
cpu0/regs/SU_cry[5]                     |       1|    1107|     27.03%
884 
                                        |        |        |
885 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/state133_3">cpu0/state133_3</a>                         |      13|    1096|     26.76%
886 
                                        |        |        |
887 
cpu0/regs/SU_cry[11]                    |       1|    1045|     25.51%
888 
                                        |        |        |
889 
cpu0/regs/SU_cry[7]                     |       1|    1024|     25.00%
890 
                                        |        |        |
891 
cpu0/regs/left_1[11]                    |       6|     955|     23.32%
892 
                                        |        |        |
893 
cpu0/datamux_o_dest[11]                 |       2|     955|     23.32%
894 
                                        |        |        |
895 
cpu0/k_opcode[7]                        |      42|     951|     23.22%
896 
                                        |        |        |
897 
cpu0/regs/SU_cry[3]                     |       1|     891|     21.75%
898 
                                        |        |        |
899 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/ea/N_107">cpu0/regs/ea/N_107</a>                      |      18|     882|     21.53%
900 
                                        |        |        |
901 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/ea/un1_eapostbyte_12">cpu0/regs/ea/un1_eapostbyte_12</a>          |      16|     864|     21.09%
902 
                                        |        |        |
903 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/N_256">cpu0/regs/N_256</a>                         |       1|     852|     20.80%
904 
                                        |        |        |
905 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/SS_226_i1_mux">cpu0/regs/SS_226_i1_mux</a>                 |       1|     852|     20.80%
906 
                                        |        |        |
907 
cpu0/regs/SS_16[11]                     |       1|     852|     20.80%
908 
                                        |        |        |
909 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/ea/eamem_addr_o_cry_8">cpu0/regs/ea/eamem_addr_o_cry_8</a>         |       1|     770|     18.80%
910 
                                        |        |        |
911 
 
912 
                                        |        |        |
913 
 
914 
                                        |        |        |
915 
 
916 
                                        |        |        |
917 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/un1_cpu_reset_9">cpu0/un1_cpu_reset_9</a>                    |       4|     619|     15.11%
918 
                                        |        |        |
919 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/ea/eamem_addr_o_cry_6">cpu0/regs/ea/eamem_addr_o_cry_6</a>         |       1|     616|     15.04%
920 
 
921 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/un1_state_116">cpu0/un1_state_116</a>                      |      16|     615|     15.01%
922 
 
923 
cpu0/regs/SS_cry[13]                    |       1|     612|     14.94%
924 
                                        |        |        |
925 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/dec_regs/un1_path_left_addr85_1_1_1">cpu0/dec_regs/un1_path_left_addr85_1_1_1</a>|       1|     588|     14.36%
926 
                                        |        |        |
927 
 
928 
                                        |        |        |
929 
 
930 
                                        |        |        |
931 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/dec_regs/path_left_addr79">cpu0/dec_regs/path_left_addr79</a>          |       1|     583|     14.23%
932 
                                        |        |        |
933 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/ea/N_62">cpu0/regs/ea/N_62</a>                       |      18|     576|     14.06%
934 
                                        |        |        |
935 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/N_283">cpu0/regs/N_283</a>                         |       1|     545|     13.31%
936 
                                        |        |        |
937 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/SU_201_i1_mux">cpu0/regs/SU_201_i1_mux</a>                 |       1|     545|     13.31%
938 
                                        |        |        |
939 
cpu0/regs/SU_16[2]                      |       1|     545|     13.31%
940 
 
941 
 
942 
                                        |        |        |
943 
 
944 
                                        |        |        |
945 
cpu0/regs/left_1[9]                     |       6|     525|     12.82%
946 
                                        |        |        |
947 
cpu0/regs/left_1[3]                     |       9|     502|     12.26%
948 
                                        |        |        |
949 
cpu0/datamux_o_dest[3]                  |       2|     502|     12.26%
950 
                                        |        |        |
951 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/un1_k_opcode_3_4">cpu0/un1_k_opcode_3_4</a>                   |       2|     499|     12.18%
952 
                                        |        |        |
953 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/un1_k_cpu_addr_1_cry_8">cpu0/un1_k_cpu_addr_1_cry_8</a>             |       1|     472|     11.52%
954 
                                        |        |        |
955 
cpu0/k_opcode[5]                        |      52|     469|     11.45%
956 
                                        |        |        |
957 
cpu0/regs/SS_cry[5]                     |       1|     463|     11.30%
958 
                                        |        |        |
959 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/un1_k_cpu_addr_1_cry_10">cpu0/un1_k_cpu_addr_1_cry_10</a>            |       1|     459|     11.21%
960 
                                        |        |        |
961 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/ea/eamem_addr_o_cry_10">cpu0/regs/ea/eamem_addr_o_cry_10</a>        |       1|     450|     10.99%
962 
                                        |        |        |
963 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/N_290">cpu0/regs/N_290</a>                         |       1|     445|     10.86%
964 
                                        |        |        |
965 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/regs/SU_208_i1_mux">cpu0/regs/SU_208_i1_mux</a>                 |       1|     445|     10.86%
966 
                                        |        |        |
967 
cpu0/regs/SU_16[9]                      |       1|     445|     10.86%
968 
                                        |        |        |
969 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/un1_k_cpu_addr_1_cry_6">cpu0/un1_k_cpu_addr_1_cry_6</a>             |       1|     444|     10.84%
970 
                                        |        |        |
971 
cpu0/regs/SS_cry[9]                     |       1|     437|     10.67%
972 
                                        |        |        |
973 
cpu0/regs/SS_cry[7]                     |       1|     424|     10.35%
974 
                                        |        |        |
975 
<a href="bali://?app=PHYSICAL_VIEW&amp;sig=LocateNet&amp;args=cpu0/alu/mulu/N_1325">cpu0/alu/mulu/N_1325</a>                    |       1|     419|     10.23%
976 
                                        |        |        |
977 
----------------------------------------------------------------------------
978 
 
979 
 
980 
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
981 
------------------------
982 
 
983 
Found 1 clocks:
984 
 
985 
Clock Domain: clk40_i_c   Source: clk40_i.PAD   Loads: 318
986 
   Covered under: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
987 
 
988 
 
989 
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
990 
---------------
991 
 
992 
Timing errors: 4096  Score: 88089612
993 
Cumulative negative slack: 88089612
994 
 
995 
Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)
996 
 
997 
--------------------------------------------------------------------------------
998 
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.1.0.96</big></U></B>
999 
Sun Jul 06 07:47:16 2014
1000 
 
1001 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1002 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1003 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1004 
Copyright (c) 2001 Agere Systems   All rights reserved.
1005 
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.
1006 
 
1007 
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
1008 
------------------
1009 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prf
1010 
Design file:     p6809_p6809.ncd
1011 
Preference file: p6809_p6809.prf
1012 
Device,speed:    LCMXO2-7000HE,m
1013 
Report level:    verbose report, limited to 10 items per preference
1014 
--------------------------------------------------------------------------------
1015 
 
1016 
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
1017 
 
1018 
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY NET "clk40_i_c" 111.645000 MHz (0 errors)</A></LI>            4096 items scored, 0 timing errors detected.
1019 
 
1020 
BLOCK ASYNCPATHS
1021 
BLOCK RESETPATHS
1022 
--------------------------------------------------------------------------------
1023 
 
1024 
 
1025 
 
1026 
================================================================================
1027 
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
1028 
            4096 items scored, 0 timing errors detected.
1029 
--------------------------------------------------------------------------------
1030 
 
1031 
 
1032 
Passed: The following path meets requirements by 0.199ns
1033 
 
1034 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1035 
 
1036 
   Source:         FF         Q              textctrl/chars_data[1]  (from clk40_i_c +)
1037 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)
1038 
 
1039 
   Delay:               0.304ns  (43.1% logic, 56.9% route), 1 logic levels.
1040 
 
1041 
 Constraint Details:
1042 
 
1043 
      0.304ns physical path delay SLICE_412 to textctrl/font/fontrom_0_0_3 meets
1044 
      0.052ns ADDR_HLD and
1045 
      0.000ns delay constraint less
1046 
     -0.053ns skew requirement (totaling 0.105ns) by 0.199ns
1047 
 
1048 
 Physical Path Details:
1049 
 
1050 
      Data path SLICE_412 to textctrl/font/fontrom_0_0_3:
1051 
 
1052 
   Name    Fanout   Delay (ns)          Site               Resource
1053 
REG_DEL     ---     0.131    R18C28D.CLK to     R18C28D.Q1 SLICE_412 (from clk40_i_c)
1054 
ROUTE         4     0.173     R18C28D.Q1 to *R_R20C27.ADA6 textctrl/chars_data[1] (to clk40_i_c)
1055 
                  --------
1056 
                    0.304   (43.1% logic, 56.9% route), 1 logic levels.
1057 
 
1058 
 Clock Skew Details:
1059 
 
1060 
      Source Clock Path clk40_i to SLICE_412:
1061 
 
1062 
 
1063 
 
1064 
                  --------
1065 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1066 
 
1067 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
1068 
 
1069 
   Name    Fanout   Delay (ns)          Site               Resource
1070 
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
1071 
 
1072 
 
1073 
 
1074 
 
1075 
 
1076 
 
1077 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1078 
 
1079 
   Source:         FF         Q              textctrl/line_cnt[3]  (from clk40_i_c +)
1080 
 
1081 
 
1082 
   Delay:               0.339ns  (38.6% logic, 61.4% route), 1 logic levels.
1083 
 
1084 
 
1085 
 
1086 
      0.339ns physical path delay textctrl/SLICE_421 to textctrl/font/fontrom_0_3_0 meets
1087 
      0.052ns ADDR_HLD and
1088 
      0.000ns delay constraint less
1089 
     -0.071ns skew requirement (totaling 0.123ns) by 0.216ns
1090 
 
1091 
 Physical Path Details:
1092 
 
1093 
      Data path textctrl/SLICE_421 to textctrl/font/fontrom_0_3_0:
1094 
 
1095 
   Name    Fanout   Delay (ns)          Site               Resource
1096 
REG_DEL     ---     0.131    R22C26B.CLK to     R22C26B.Q1 textctrl/SLICE_421 (from clk40_i_c)
1097 
ROUTE         7     0.208     R22C26B.Q1 to *R_R20C24.ADA4 textctrl/line_cnt[3] (to clk40_i_c)
1098 
                  --------
1099 
 
1100 
 
1101 
 
1102 
 
1103 
 
1104 
 
1105 
   Name    Fanout   Delay (ns)          Site               Resource
1106 
ROUTE       318     0.828       27.PADDI to    R22C26B.CLK clk40_i_c
1107 
 
1108 
 
1109 
 
1110 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
1111 
 
1112 
   Name    Fanout   Delay (ns)          Site               Resource
1113 
ROUTE       318     0.899       27.PADDI to *R_R20C24.CLKA clk40_i_c
1114 
 
1115 
 
1116 
 
1117 
 
1118 
Passed: The following path meets requirements by 0.277ns
1119 
 
1120 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1121 
 
1122 
 
1123 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)
1124 
 
1125 
   Delay:               0.382ns  (34.3% logic, 65.7% route), 1 logic levels.
1126 
 
1127 
 Constraint Details:
1128 
 
1129 
      0.382ns physical path delay SLICE_412 to textctrl/font/fontrom_0_0_3 meets
1130 
      0.052ns ADDR_HLD and
1131 
 
1132 
     -0.053ns skew requirement (totaling 0.105ns) by 0.277ns
1133 
 
1134 
 Physical Path Details:
1135 
 
1136 
      Data path SLICE_412 to textctrl/font/fontrom_0_0_3:
1137 
 
1138 
   Name    Fanout   Delay (ns)          Site               Resource
1139 
REG_DEL     ---     0.131    R18C28D.CLK to     R18C28D.Q0 SLICE_412 (from clk40_i_c)
1140 
ROUTE         4     0.251     R18C28D.Q0 to *R_R20C27.ADA5 textctrl/chars_data[0] (to clk40_i_c)
1141 
 
1142 
                    0.382   (34.3% logic, 65.7% route), 1 logic levels.
1143 
 
1144 
 Clock Skew Details:
1145 
 
1146 
      Source Clock Path clk40_i to SLICE_412:
1147 
 
1148 
   Name    Fanout   Delay (ns)          Site               Resource
1149 
ROUTE       318     0.846       27.PADDI to    R18C28D.CLK clk40_i_c
1150 
 
1151 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1152 
 
1153 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
1154 
 
1155 
   Name    Fanout   Delay (ns)          Site               Resource
1156 
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
1157 
 
1158 
 
1159 
 
1160 
 
1161 
Passed: The following path meets requirements by 0.294ns
1162 
 
1163 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1164 
 
1165 
 
1166 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)
1167 
 
1168 
   Delay:               0.418ns  (31.3% logic, 68.7% route), 1 logic levels.
1169 
 
1170 
 Constraint Details:
1171 
 
1172 
      0.418ns physical path delay cpu0/SLICE_183 to textctrl/chars/textmem4k_0_2_1 meets
1173 
      0.071ns ADDR_HLD and
1174 
 
1175 
     -0.053ns skew requirement (totaling 0.124ns) by 0.294ns
1176 
 
1177 
 Physical Path Details:
1178 
 
1179 
      Data path cpu0/SLICE_183 to textctrl/chars/textmem4k_0_2_1:
1180 
 
1181 
   Name    Fanout   Delay (ns)          Site               Resource
1182 
REG_DEL     ---     0.131    R16C14C.CLK to     R16C14C.Q0 cpu0/SLICE_183 (from clk40_i_c)
1183 
ROUTE        11     0.287     R16C14C.Q0 to *R_R13C13.ADB1 addr_o_c[0] (to clk40_i_c)
1184 
 
1185 
                    0.418   (31.3% logic, 68.7% route), 1 logic levels.
1186 
 
1187 
 Clock Skew Details:
1188 
 
1189 
      Source Clock Path clk40_i to cpu0/SLICE_183:
1190 
 
1191 
   Name    Fanout   Delay (ns)          Site               Resource
1192 
ROUTE       318     0.846       27.PADDI to    R16C14C.CLK clk40_i_c
1193 
 
1194 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1195 
 
1196 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1197 
 
1198 
   Name    Fanout   Delay (ns)          Site               Resource
1199 
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
1200 
 
1201 
 
1202 
 
1203 
 
1204 
Passed: The following path meets requirements by 0.302ns
1205 
 
1206 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1207 
 
1208 
 
1209 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)
1210 
 
1211 
   Delay:               0.407ns  (32.2% logic, 67.8% route), 1 logic levels.
1212 
 
1213 
 Constraint Details:
1214 
 
1215 
      0.407ns physical path delay SLICE_415 to textctrl/font/fontrom_0_0_3 meets
1216 
      0.052ns ADDR_HLD and
1217 
 
1218 
     -0.053ns skew requirement (totaling 0.105ns) by 0.302ns
1219 
 
1220 
 Physical Path Details:
1221 
 
1222 
      Data path SLICE_415 to textctrl/font/fontrom_0_0_3:
1223 
 
1224 
   Name    Fanout   Delay (ns)          Site               Resource
1225 
REG_DEL     ---     0.131    R16C28A.CLK to     R16C28A.Q1 SLICE_415 (from clk40_i_c)
1226 
ROUTE         4     0.276     R16C28A.Q1 to *_R20C27.ADA12 textctrl/chars_data[7] (to clk40_i_c)
1227 
 
1228 
                    0.407   (32.2% logic, 67.8% route), 1 logic levels.
1229 
 
1230 
 Clock Skew Details:
1231 
 
1232 
      Source Clock Path clk40_i to SLICE_415:
1233 
 
1234 
   Name    Fanout   Delay (ns)          Site               Resource
1235 
ROUTE       318     0.846       27.PADDI to    R16C28A.CLK clk40_i_c
1236 
 
1237 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1238 
 
1239 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
1240 
 
1241 
   Name    Fanout   Delay (ns)          Site               Resource
1242 
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
1243 
 
1244 
 
1245 
 
1246 
 
1247 
Passed: The following path meets requirements by 0.314ns
1248 
 
1249 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1250 
 
1251 
 
1252 
   Destination:    DP8KC      Port           bios/bios2k_0_1_0(ASIC)  (to clk40_i_c +)
1253 
 
1254 
   Delay:               0.419ns  (31.3% logic, 68.7% route), 1 logic levels.
1255 
 
1256 
 Constraint Details:
1257 
 
1258 
      0.419ns physical path delay cpu0/SLICE_186 to bios/bios2k_0_1_0 meets
1259 
      0.052ns ADDR_HLD and
1260 
 
1261 
     -0.053ns skew requirement (totaling 0.105ns) by 0.314ns
1262 
 
1263 
 Physical Path Details:
1264 
 
1265 
      Data path cpu0/SLICE_186 to bios/bios2k_0_1_0:
1266 
 
1267 
   Name    Fanout   Delay (ns)          Site               Resource
1268 
REG_DEL     ---     0.131    R15C12A.CLK to     R15C12A.Q0 cpu0/SLICE_186 (from clk40_i_c)
1269 
ROUTE         8     0.288     R15C12A.Q0 to *R_R13C10.ADA8 addr_o_c[6] (to clk40_i_c)
1270 
 
1271 
                    0.419   (31.3% logic, 68.7% route), 1 logic levels.
1272 
 
1273 
 Clock Skew Details:
1274 
 
1275 
      Source Clock Path clk40_i to cpu0/SLICE_186:
1276 
 
1277 
   Name    Fanout   Delay (ns)          Site               Resource
1278 
ROUTE       318     0.846       27.PADDI to    R15C12A.CLK clk40_i_c
1279 
 
1280 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1281 
 
1282 
      Destination Clock Path clk40_i to bios/bios2k_0_1_0:
1283 
 
1284 
   Name    Fanout   Delay (ns)          Site               Resource
1285 
ROUTE       318     0.899       27.PADDI to *R_R13C10.CLKA clk40_i_c
1286 
 
1287 
 
1288 
 
1289 
 
1290 
Passed: The following path meets requirements by 0.322ns
1291 
 
1292 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1293 
 
1294 
 
1295 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)
1296 
 
1297 
   Delay:               0.446ns  (29.4% logic, 70.6% route), 1 logic levels.
1298 
 
1299 
 Constraint Details:
1300 
 
1301 
      0.446ns physical path delay cpu0/SLICE_185 to textctrl/chars/textmem4k_0_2_1 meets
1302 
      0.071ns ADDR_HLD and
1303 
 
1304 
     -0.053ns skew requirement (totaling 0.124ns) by 0.322ns
1305 
 
1306 
 Physical Path Details:
1307 
 
1308 
      Data path cpu0/SLICE_185 to textctrl/chars/textmem4k_0_2_1:
1309 
 
1310 
   Name    Fanout   Delay (ns)          Site               Resource
1311 
REG_DEL     ---     0.131    R16C13D.CLK to     R16C13D.Q1 cpu0/SLICE_185 (from clk40_i_c)
1312 
ROUTE         9     0.315     R16C13D.Q1 to *R_R13C13.ADB6 addr_o_c[5] (to clk40_i_c)
1313 
 
1314 
                    0.446   (29.4% logic, 70.6% route), 1 logic levels.
1315 
 
1316 
 Clock Skew Details:
1317 
 
1318 
      Source Clock Path clk40_i to cpu0/SLICE_185:
1319 
 
1320 
   Name    Fanout   Delay (ns)          Site               Resource
1321 
ROUTE       318     0.846       27.PADDI to    R16C13D.CLK clk40_i_c
1322 
 
1323 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1324 
 
1325 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1326 
 
1327 
   Name    Fanout   Delay (ns)          Site               Resource
1328 
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
1329 
 
1330 
 
1331 
 
1332 
 
1333 
Passed: The following path meets requirements by 0.326ns
1334 
 
1335 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1336 
 
1337 
 
1338 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to clk40_i_c +)
1339 
 
1340 
   Delay:               0.449ns  (29.2% logic, 70.8% route), 1 logic levels.
1341 
 
1342 
 Constraint Details:
1343 
 
1344 
      0.449ns physical path delay textctrl/SLICE_420 to textctrl/font/fontrom_0_0_3 meets
1345 
      0.052ns ADDR_HLD and
1346 
 
1347 
     -0.071ns skew requirement (totaling 0.123ns) by 0.326ns
1348 
 
1349 
 Physical Path Details:
1350 
 
1351 
      Data path textctrl/SLICE_420 to textctrl/font/fontrom_0_0_3:
1352 
 
1353 
   Name    Fanout   Delay (ns)          Site               Resource
1354 
REG_DEL     ---     0.131    R22C27D.CLK to     R22C27D.Q1 textctrl/SLICE_420 (from clk40_i_c)
1355 
ROUTE         9     0.318     R22C27D.Q1 to *R_R20C27.ADA2 textctrl/line_cnt[1] (to clk40_i_c)
1356 
 
1357 
                    0.449   (29.2% logic, 70.8% route), 1 logic levels.
1358 
 
1359 
 Clock Skew Details:
1360 
 
1361 
      Source Clock Path clk40_i to textctrl/SLICE_420:
1362 
 
1363 
   Name    Fanout   Delay (ns)          Site               Resource
1364 
ROUTE       318     0.828       27.PADDI to    R22C27D.CLK clk40_i_c
1365 
 
1366 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1367 
 
1368 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
1369 
 
1370 
   Name    Fanout   Delay (ns)          Site               Resource
1371 
ROUTE       318     0.899       27.PADDI to *R_R20C27.CLKA clk40_i_c
1372 
 
1373 
 
1374 
 
1375 
 
1376 
Passed: The following path meets requirements by 0.326ns
1377 
 
1378 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1379 
 
1380 
 
1381 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to clk40_i_c +)
1382 
 
1383 
   Delay:               0.450ns  (29.1% logic, 70.9% route), 1 logic levels.
1384 
 
1385 
 Constraint Details:
1386 
 
1387 
      0.450ns physical path delay cpu0/SLICE_187 to textctrl/chars/textmem4k_0_2_1 meets
1388 
      0.071ns ADDR_HLD and
1389 
 
1390 
     -0.053ns skew requirement (totaling 0.124ns) by 0.326ns
1391 
 
1392 
 Physical Path Details:
1393 
 
1394 
      Data path cpu0/SLICE_187 to textctrl/chars/textmem4k_0_2_1:
1395 
 
1396 
   Name    Fanout   Delay (ns)          Site               Resource
1397 
REG_DEL     ---     0.131    R15C12B.CLK to     R15C12B.Q1 cpu0/SLICE_187 (from clk40_i_c)
1398 
ROUTE         8     0.319     R15C12B.Q1 to *_R13C13.ADB10 addr_o_c[9] (to clk40_i_c)
1399 
 
1400 
                    0.450   (29.1% logic, 70.9% route), 1 logic levels.
1401 
 
1402 
 Clock Skew Details:
1403 
 
1404 
      Source Clock Path clk40_i to cpu0/SLICE_187:
1405 
 
1406 
   Name    Fanout   Delay (ns)          Site               Resource
1407 
ROUTE       318     0.846       27.PADDI to    R15C12B.CLK clk40_i_c
1408 
 
1409 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1410 
 
1411 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1412 
 
1413 
   Name    Fanout   Delay (ns)          Site               Resource
1414 
ROUTE       318     0.899       27.PADDI to *R_R13C13.CLKB clk40_i_c
1415 
 
1416 
 
1417 
 
1418 
 
1419 
Passed: The following path meets requirements by 0.328ns
1420 
 
1421 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1422 
 
1423 
 
1424 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_3_0(ASIC)  (to clk40_i_c +)
1425 
 
1426 
   Delay:               0.451ns  (29.0% logic, 71.0% route), 1 logic levels.
1427 
 
1428 
 Constraint Details:
1429 
 
1430 
      0.451ns physical path delay textctrl/SLICE_420 to textctrl/font/fontrom_0_3_0 meets
1431 
      0.052ns ADDR_HLD and
1432 
 
1433 
     -0.071ns skew requirement (totaling 0.123ns) by 0.328ns
1434 
 
1435 
 Physical Path Details:
1436 
 
1437 
      Data path textctrl/SLICE_420 to textctrl/font/fontrom_0_3_0:
1438 
 
1439 
   Name    Fanout   Delay (ns)          Site               Resource
1440 
REG_DEL     ---     0.131    R22C27D.CLK to     R22C27D.Q1 textctrl/SLICE_420 (from clk40_i_c)
1441 
ROUTE         9     0.320     R22C27D.Q1 to *R_R20C24.ADA2 textctrl/line_cnt[1] (to clk40_i_c)
1442 
 
1443 
                    0.451   (29.0% logic, 71.0% route), 1 logic levels.
1444 
 
1445 
 Clock Skew Details:
1446 
 
1447 
      Source Clock Path clk40_i to textctrl/SLICE_420:
1448 
 
1449 
   Name    Fanout   Delay (ns)          Site               Resource
1450 
ROUTE       318     0.828       27.PADDI to    R22C27D.CLK clk40_i_c
1451 
 
1452 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1453 
 
1454 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
1455 
 
1456 
   Name    Fanout   Delay (ns)          Site               Resource
1457 
ROUTE       318     0.899       27.PADDI to *R_R20C24.CLKA clk40_i_c
1458 
 
1459 
 
1460 
 
1461 
 
1462 
--------------
1463 
 
1464 
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
1465 
----------------------------------------------------------------------------
1466 
 
1467 
FREQUENCY NET "clk40_i_c" 111.645000    |             |             |
1468 
 
1469 
                                        |             |             |
1470 
 
1471 
 
1472 
 
1473 
All preferences were met.
1474 
 
1475 
 
1476 
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
1477 
 
1478 
 
1479 
 
1480 
 
1481 
Clock Domain: clk40_i_c   Source: clk40_i.PAD   Loads: 318
1482 
   Covered under: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
1483 
 
1484 
 
1485 
 
1486 
---------------
1487 
 
1488 
Timing errors: 0  Score: 0
1489 
 
1490 
 
1491 
Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)
1492 
 
1493 
 
1494 
 
1495 
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
1496 
 
1497 
 
1498 
Timing errors: 4096 (setup), 0 (hold)
1499 
Score: 88089612 (setup), 0 (hold)
1500 
Cumulative negative slack: 88089612 (88089612+0)
1501 
 
1502 
 
1503 
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