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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_twr.html] - Blame information for rev 9

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<HTML>
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<HEAD><TITLE>Lattice TRACE Report</TITLE>
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<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
10 
 
11 
Loading design for application trce from file P6809_P6809.ncd.
12 
Design name: CC3_top
13 
NCD version: 3.2
14 
Vendor:      LATTICE
15 
Device:      LCMXO2-7000HE
16 
Package:     TQFP144
17 
Performance: 4
18 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
19 
Package Status:                     Final          Version 1.36
20 
Performance Hardware Data Status:   Final)         Version 23.4
21 
Setup and Hold Report
22 
 
23 
--------------------------------------------------------------------------------
24 
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>
25 
Mon Jan  6 06:55:04 2014
26 
 
27 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
28 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
29 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
30 
Copyright (c) 2001 Agere Systems   All rights reserved.
31 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
32 
 
33 
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
34 
------------------
35 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
36 
Design file:     P6809_P6809.ncd
37 
Preference file: P6809_P6809.prf
38 
Device,speed:    LCMXO2-7000HE,4
39 
Report level:    verbose report, limited to 10 items per preference
40 
--------------------------------------------------------------------------------
41 
 
42 
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
43 
 
44 
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI>            4096 items scored, 0 timing errors detected.
45 
Report:   41.761MHz is the maximum frequency for this preference.
46 
 
47 
BLOCK ASYNCPATHS
48 
BLOCK RESETPATHS
49 
--------------------------------------------------------------------------------
50 
 
51 
 
52 
 
53 
================================================================================
54 
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
55 
            4096 items scored, 0 timing errors detected.
56 
--------------------------------------------------------------------------------
57 
 
58 
 
59 
Passed: The following path meets requirements by 1.054ns
60 
 
61 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
62 
 
63 
   Source:         FF         Q              cpu0/alu/rb_in[1]  (from cpu_clkgen +)
64 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
65 
 
66 
   Delay:              23.780ns  (42.8% logic, 57.2% route), 19 logic levels.
67 
 
68 
 Constraint Details:
69 
 
70 
     23.780ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 meets
71 
 
72 
      0.000ns skew and
73 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.054ns
74 
 
75 
 Physical Path Details:
76 
 
77 
      Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
78 
 
79 
   Name    Fanout   Delay (ns)          Site               Resource
80 
REG_DEL     ---     0.452    R12C13B.CLK to     R12C13B.Q1 cpu0/SLICE_229 (from cpu_clkgen)
81 
ROUTE        26     1.735     R12C13B.Q1 to     R10C14B.A0 cpu0/alu/rb_in[1]
82 
C0TOFCO_DE  ---     1.023     R10C14B.A0 to    R10C14B.FCO cpu0/alu/alu16/a16/SLICE_98
83 
ROUTE         1     0.000    R10C14B.FCO to    R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
84 
FCITOF1_DE  ---     0.643    R10C14C.FCI to     R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
85 
ROUTE         1     1.385     R10C14C.F1 to     R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
86 
CTOF_DEL    ---     0.495     R11C17C.D0 to     R11C17C.F0 cpu0/alu/SLICE_1151
87 
ROUTE         1     1.675     R11C17C.F0 to     R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
88 
C1TOFCO_DE  ---     0.889     R11C21C.C1 to    R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
89 
ROUTE         1     0.000    R11C21C.FCO to    R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
90 
FCITOF0_DE  ---     0.585    R11C21D.FCI to     R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
91 
ROUTE         1     1.705     R11C21D.F0 to      R7C15D.C0 cpu0/alu/alu16/a16/N_2261
92 
CTOF_DEL    ---     0.495      R7C15D.C0 to      R7C15D.F0 cpu0/alu/alu16/SLICE_1209
93 
 
94 
CTOOFX_DEL  ---     0.721      R9C15A.D1 to    R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
95 
ROUTE         2     1.285    R9C15A.OFX0 to      R9C22B.C1 cpu0/alu/q16_out[5]
96 
CTOOFX_DEL  ---     0.721      R9C22B.C1 to    R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
97 
ROUTE         2     1.392    R9C22B.OFX0 to     R11C20D.D0 cpu0/datamux_o_dest[5]
98 
CTOF_DEL    ---     0.495     R11C20D.D0 to     R11C20D.F0 cpu0/regs/SLICE_890
99 
ROUTE         9     0.798     R11C20D.F0 to      R9C20D.C1 cpu0/regs/left_1[5]
100 
CTOF_DEL    ---     0.495      R9C20D.C1 to      R9C20D.F1 cpu0/regs/SLICE_1124
101 
ROUTE         1     0.958      R9C20D.F1 to      R8C18A.D1 cpu0/regs/N_284
102 
CTOF_DEL    ---     0.495      R8C18A.D1 to      R8C18A.F1 cpu0/regs/SLICE_900
103 
ROUTE         1     0.626      R8C18A.F1 to      R8C18A.D0 cpu0/regs/SU_16[5]
104 
CTOF_DEL    ---     0.495      R8C18A.D0 to      R8C18A.F0 cpu0/regs/SLICE_900
105 
 
106 
C1TOFCO_DE  ---     0.889     R10C18D.C1 to    R10C18D.FCO cpu0/regs/SLICE_69
107 
ROUTE         1     0.000    R10C18D.FCO to    R10C19A.FCI cpu0/regs/SU_cry[5]
108 
FCITOFCO_D  ---     0.162    R10C19A.FCI to    R10C19A.FCO cpu0/regs/SLICE_68
109 
 
110 
FCITOFCO_D  ---     0.162    R10C19B.FCI to    R10C19B.FCO cpu0/regs/SLICE_67
111 
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI cpu0/regs/SU_cry[9]
112 
FCITOFCO_D  ---     0.162    R10C19C.FCI to    R10C19C.FCO cpu0/regs/SLICE_66
113 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
114 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
115 
 
116 
FCITOF1_DE  ---     0.643    R10C20A.FCI to     R10C20A.F1 cpu0/regs/SLICE_64
117 
ROUTE         1     0.000     R10C20A.F1 to    R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
118 
                  --------
119 
                   23.780   (42.8% logic, 57.2% route), 19 logic levels.
120 
 
121 
 Clock Skew Details:
122 
 
123 
      Source Clock Path clk40_i to cpu0/SLICE_229:
124 
 
125 
   Name    Fanout   Delay (ns)          Site               Resource
126 
 
127 
                  --------
128 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
129 
 
130 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
131 
 
132 
   Name    Fanout   Delay (ns)          Site               Resource
133 
 
134 
 
135 
 
136 
 
137 
 
138 
Passed: The following path meets requirements by 1.057ns
139 
 
140 
 
141 
 
142 
   Source:         FF         Q              cpu0/alu/rb_in[8]  (from cpu_clkgen +)
143 
 
144 
 
145 
 
146 
 
147 
 Constraint Details:
148 
 
149 
     23.777ns physical path delay cpu0/SLICE_232 to cpu0/regs/SLICE_64 meets
150 
 
151 
      0.000ns skew and
152 
 
153 
 
154 
 Physical Path Details:
155 
 
156 
      Data path cpu0/SLICE_232 to cpu0/regs/SLICE_64:
157 
 
158 
   Name    Fanout   Delay (ns)          Site               Resource
159 
 
160 
ROUTE         6     1.156     R14C16C.Q0 to     R12C15A.C1 cpu0/alu/rb_in[8]
161 
 
162 
ROUTE         1     1.299     R12C15A.F1 to     R10C15A.A1 cpu0/alu/alu16/a16/rb_in_i[8]
163 
C1TOFCO_DE  ---     0.889     R10C15A.A1 to    R10C15A.FCO cpu0/alu/alu16/a16/SLICE_95
164 
ROUTE         1     0.000    R10C15A.FCO to    R10C15B.FCI cpu0/alu/alu16/a16/un8_q_out_cry_8
165 
FCITOF1_DE  ---     0.643    R10C15B.FCI to     R10C15B.F1 cpu0/alu/alu16/a16/SLICE_94
166 
ROUTE         1     0.986     R10C15B.F1 to     R11C15D.A0 cpu0/alu/alu16/a16/un8_q_out[10]
167 
CTOF_DEL    ---     0.495     R11C15D.A0 to     R11C15D.F0 cpu0/alu/SLICE_1213
168 
ROUTE         1     1.675     R11C15D.F0 to     R11C22B.C1 cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0
169 
C1TOFCO_DE  ---     0.889     R11C22B.C1 to    R11C22B.FCO cpu0/alu/alu16/a16/SLICE_112
170 
ROUTE         1     0.000    R11C22B.FCO to    R11C22C.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
171 
FCITOF0_DE  ---     0.585    R11C22C.FCI to     R11C22C.F0 cpu0/alu/alu16/a16/SLICE_111
172 
ROUTE         1     1.072     R11C22C.F0 to      R7C22D.D0 cpu0/alu/alu16/a16/N_2324
173 
CTOF_DEL    ---     0.495      R7C22D.D0 to      R7C22D.F0 cpu0/alu/alu16/SLICE_986
174 
ROUTE         1     0.436      R7C22D.F0 to      R7C22D.C1 cpu0/alu/alu16/arith_q[11]
175 
CTOF_DEL    ---     0.495      R7C22D.C1 to      R7C22D.F1 cpu0/alu/alu16/SLICE_986
176 
ROUTE         1     0.958      R7C22D.F1 to     R10C22C.D1 cpu0/alu/alu16/N_2298
177 
CTOF_DEL    ---     0.495     R10C22C.D1 to     R10C22C.F1 cpu0/alu/alu16/SLICE_1001
178 
ROUTE         2     1.032     R10C22C.F1 to     R12C22D.B1 cpu0/alu/q16_out[11]
179 
CTOF_DEL    ---     0.495     R12C22D.B1 to     R12C22D.F1 cpu0/alu/SLICE_1236
180 
ROUTE         2     0.635     R12C22D.F1 to     R12C22A.D1 cpu0/datamux_o_dest[11]
181 
CTOF_DEL    ---     0.495     R12C22A.D1 to     R12C22A.F1 cpu0/regs/SLICE_941
182 
ROUTE         6     1.479     R12C22A.F1 to     R14C19C.D0 cpu0/regs/left_1[11]
183 
CTOF_DEL    ---     0.495     R14C19C.D0 to     R14C19C.F0 cpu0/regs/SLICE_1193
184 
ROUTE         1     1.035     R14C19C.F0 to     R12C19D.D1 cpu0/regs/N_290
185 
CTOF_DEL    ---     0.495     R12C19D.D1 to     R12C19D.F1 cpu0/regs/SLICE_914
186 
ROUTE         1     0.436     R12C19D.F1 to     R12C19D.C0 cpu0/regs/SU_16[11]
187 
CTOF_DEL    ---     0.495     R12C19D.C0 to     R12C19D.F0 cpu0/regs/SLICE_914
188 
ROUTE         1     1.476     R12C19D.F0 to     R10C19C.C1 cpu0/regs/SU_216_i1_mux
189 
C1TOFCO_DE  ---     0.889     R10C19C.C1 to    R10C19C.FCO cpu0/regs/SLICE_66
190 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
191 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
192 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
193 
FCITOF1_DE  ---     0.643    R10C20A.FCI to     R10C20A.F1 cpu0/regs/SLICE_64
194 
ROUTE         1     0.000     R10C20A.F1 to    R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
195 
                  --------
196 
                   23.777   (42.5% logic, 57.5% route), 18 logic levels.
197 
 
198 
 Clock Skew Details:
199 
 
200 
      Source Clock Path clk40_i to cpu0/SLICE_232:
201 
 
202 
   Name    Fanout   Delay (ns)          Site               Resource
203 
 
204 
                  --------
205 
 
206 
 
207 
 
208 
 
209 
   Name    Fanout   Delay (ns)          Site               Resource
210 
ROUTE       290     2.399       27.PADDI to    R10C20A.CLK cpu_clkgen
211 
                  --------
212 
 
213 
 
214 
 
215 
Passed: The following path meets requirements by 1.091ns
216 
 
217 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
218 
 
219 
 
220 
 
221 
 
222 
 
223 
 
224 
 
225 
 
226 
     23.743ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_201 meets
227 
 
228 
      0.000ns skew and
229 
 
230 
 
231 
 
232 
 
233 
      Data path cpu0/SLICE_1133 to cpu0/SLICE_201:
234 
 
235 
   Name    Fanout   Delay (ns)          Site               Resource
236 
 
237 
ROUTE        21     1.473     R14C26D.Q0 to     R14C25D.B1 cpu0/k_postbyte[4]
238 
 
239 
ROUTE         1     1.525     R14C25D.F1 to     R12C26B.A1 cpu0/dec_op/mode76_0
240 
 
241 
ROUTE         3     0.984     R12C26B.F1 to     R12C26B.A0 cpu0/dec_op/mode76
242 
CTOF_DEL    ---     0.495     R12C26B.A0 to     R12C26B.F0 cpu0/dec_op/SLICE_743
243 
ROUTE         1     1.022     R12C26B.F0 to     R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
244 
CTOF_DEL    ---     0.495     R14C26C.D0 to     R14C26C.F0 cpu0/dec_op/SLICE_739
245 
ROUTE         2     0.632     R14C26C.F0 to     R14C27B.D1 cpu0/dec_op/N_290
246 
CTOF_DEL    ---     0.495     R14C27B.D1 to     R14C27B.F1 cpu0/dec_op/SLICE_700
247 
ROUTE         3     2.174     R14C27B.F1 to     R15C27B.M0 cpu0/dec_op/un1_mode93
248 
MTOOFX_DEL  ---     0.376     R15C27B.M0 to   R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
249 
ROUTE         5     2.393   R15C27B.OFX0 to     R14C23C.B0 cpu0/mode_7[2]
250 
CTOF_DEL    ---     0.495     R14C23C.B0 to     R14C23C.F0 cpu0/SLICE_592
251 
ROUTE        11     0.635     R14C23C.F0 to     R14C23D.D0 cpu0/state81
252 
CTOF_DEL    ---     0.495     R14C23D.D0 to     R14C23D.F0 cpu0/dec_op/SLICE_718
253 
ROUTE         3     1.153     R14C23D.F0 to     R12C24B.D0 cpu0/un1_cpu_reset_11
254 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/SLICE_593
255 
ROUTE        33     1.338     R12C24B.F0 to     R10C24A.A1 cpu0/un1_state_122
256 
C1TOFCO_DE  ---     0.889     R10C24A.A1 to    R10C24A.FCO cpu0/SLICE_36
257 
ROUTE         1     0.000    R10C24A.FCO to    R10C24B.FCI cpu0/un1_k_cpu_addr_1_cry_0
258 
FCITOFCO_D  ---     0.162    R10C24B.FCI to    R10C24B.FCO cpu0/SLICE_195
259 
ROUTE         1     0.000    R10C24B.FCO to    R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
260 
FCITOFCO_D  ---     0.162    R10C24C.FCI to    R10C24C.FCO cpu0/SLICE_194
261 
ROUTE         1     0.000    R10C24C.FCO to    R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
262 
FCITOFCO_D  ---     0.162    R10C24D.FCI to    R10C24D.FCO cpu0/SLICE_193
263 
ROUTE         1     0.000    R10C24D.FCO to    R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
264 
FCITOFCO_D  ---     0.162    R10C25A.FCI to    R10C25A.FCO cpu0/SLICE_192
265 
ROUTE         1     0.000    R10C25A.FCO to    R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
266 
FCITOF1_DE  ---     0.643    R10C25B.FCI to     R10C25B.F1 cpu0/SLICE_191
267 
ROUTE         1     1.498     R10C25B.F1 to     R12C28C.A0 cpu0/un1_k_cpu_addr_1_cry_9_0_S1
268 
CTOF_DEL    ---     0.495     R12C28C.A0 to     R12C28C.F0 cpu0/SLICE_1059
269 
ROUTE         1     0.958     R12C28C.F0 to     R11C26A.D0 cpu0/regs/ea/un1_k_cpu_addr_1_m[10]
270 
CTOF_DEL    ---     0.495     R11C26A.D0 to     R11C26A.F0 cpu0/SLICE_201
271 
ROUTE         1     0.000     R11C26A.F0 to    R11C26A.DI0 cpu0/k_cpu_addr_28[10] (to cpu_clkgen)
272 
                  --------
273 
                   23.743   (33.5% logic, 66.5% route), 18 logic levels.
274 
 
275 
 Clock Skew Details:
276 
 
277 
      Source Clock Path clk40_i to cpu0/SLICE_1133:
278 
 
279 
   Name    Fanout   Delay (ns)          Site               Resource
280 
 
281 
                  --------
282 
 
283 
 
284 
 
285 
 
286 
   Name    Fanout   Delay (ns)          Site               Resource
287 
ROUTE       290     2.399       27.PADDI to    R11C26A.CLK cpu_clkgen
288 
                  --------
289 
 
290 
 
291 
 
292 
Passed: The following path meets requirements by 1.094ns
293 
 
294 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
295 
 
296 
 
297 
 
298 
 
299 
 
300 
 
301 
 
302 
 
303 
     23.740ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_203 meets
304 
 
305 
      0.000ns skew and
306 
 
307 
 
308 
 
309 
 
310 
      Data path cpu0/SLICE_1133 to cpu0/SLICE_203:
311 
 
312 
   Name    Fanout   Delay (ns)          Site               Resource
313 
 
314 
ROUTE        21     1.473     R14C26D.Q0 to     R14C25D.B1 cpu0/k_postbyte[4]
315 
 
316 
ROUTE         1     1.525     R14C25D.F1 to     R12C26B.A1 cpu0/dec_op/mode76_0
317 
 
318 
ROUTE         3     0.984     R12C26B.F1 to     R12C26B.A0 cpu0/dec_op/mode76
319 
CTOF_DEL    ---     0.495     R12C26B.A0 to     R12C26B.F0 cpu0/dec_op/SLICE_743
320 
ROUTE         1     1.022     R12C26B.F0 to     R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
321 
CTOF_DEL    ---     0.495     R14C26C.D0 to     R14C26C.F0 cpu0/dec_op/SLICE_739
322 
ROUTE         2     0.632     R14C26C.F0 to     R14C27B.D1 cpu0/dec_op/N_290
323 
CTOF_DEL    ---     0.495     R14C27B.D1 to     R14C27B.F1 cpu0/dec_op/SLICE_700
324 
ROUTE         3     2.174     R14C27B.F1 to     R15C27B.M0 cpu0/dec_op/un1_mode93
325 
MTOOFX_DEL  ---     0.376     R15C27B.M0 to   R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
326 
ROUTE         5     2.393   R15C27B.OFX0 to     R14C23C.B0 cpu0/mode_7[2]
327 
CTOF_DEL    ---     0.495     R14C23C.B0 to     R14C23C.F0 cpu0/SLICE_592
328 
ROUTE        11     0.635     R14C23C.F0 to     R14C23D.D0 cpu0/state81
329 
CTOF_DEL    ---     0.495     R14C23D.D0 to     R14C23D.F0 cpu0/dec_op/SLICE_718
330 
ROUTE         3     1.153     R14C23D.F0 to     R12C24B.D0 cpu0/un1_cpu_reset_11
331 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/SLICE_593
332 
ROUTE        33     1.338     R12C24B.F0 to     R10C24A.A1 cpu0/un1_state_122
333 
C1TOFCO_DE  ---     0.889     R10C24A.A1 to    R10C24A.FCO cpu0/SLICE_36
334 
ROUTE         1     0.000    R10C24A.FCO to    R10C24B.FCI cpu0/un1_k_cpu_addr_1_cry_0
335 
FCITOFCO_D  ---     0.162    R10C24B.FCI to    R10C24B.FCO cpu0/SLICE_195
336 
ROUTE         1     0.000    R10C24B.FCO to    R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
337 
FCITOFCO_D  ---     0.162    R10C24C.FCI to    R10C24C.FCO cpu0/SLICE_194
338 
ROUTE         1     0.000    R10C24C.FCO to    R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
339 
FCITOFCO_D  ---     0.162    R10C24D.FCI to    R10C24D.FCO cpu0/SLICE_193
340 
ROUTE         1     0.000    R10C24D.FCO to    R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
341 
FCITOFCO_D  ---     0.162    R10C25A.FCI to    R10C25A.FCO cpu0/SLICE_192
342 
ROUTE         1     0.000    R10C25A.FCO to    R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
343 
FCITOFCO_D  ---     0.162    R10C25B.FCI to    R10C25B.FCO cpu0/SLICE_191
344 
ROUTE         1     0.000    R10C25B.FCO to    R10C25C.FCI cpu0/un1_k_cpu_addr_1_cry_10
345 
FCITOFCO_D  ---     0.162    R10C25C.FCI to    R10C25C.FCO cpu0/SLICE_190
346 
ROUTE         1     0.000    R10C25C.FCO to    R10C25D.FCI cpu0/un1_k_cpu_addr_1_cry_12
347 
FCITOF1_DE  ---     0.643    R10C25D.FCI to     R10C25D.F1 cpu0/SLICE_189
348 
ROUTE         1     1.385     R10C25D.F1 to     R12C28A.D0 cpu0/un1_k_cpu_addr_1_cry_13_0_S1
349 
CTOF_DEL    ---     0.495     R12C28A.D0 to     R12C28A.F0 cpu0/SLICE_1246
350 
ROUTE         1     0.744     R12C28A.F0 to     R12C27A.C0 cpu0/alu/un1_k_cpu_addr_1_m[14]
351 
CTOF_DEL    ---     0.495     R12C27A.C0 to     R12C27A.F0 cpu0/SLICE_203
352 
ROUTE         1     0.000     R12C27A.F0 to    R12C27A.DI0 cpu0/k_cpu_addr_28[14] (to cpu_clkgen)
353 
                  --------
354 
                   23.740   (34.9% logic, 65.1% route), 20 logic levels.
355 
 
356 
 Clock Skew Details:
357 
 
358 
      Source Clock Path clk40_i to cpu0/SLICE_1133:
359 
 
360 
   Name    Fanout   Delay (ns)          Site               Resource
361 
 
362 
                  --------
363 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
364 
 
365 
      Destination Clock Path clk40_i to cpu0/SLICE_203:
366 
 
367 
   Name    Fanout   Delay (ns)          Site               Resource
368 
 
369 
                  --------
370 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
371 
 
372 
 
373 
 
374 
 
375 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
376 
 
377 
   Source:         FF         Q              cpu0/alu/ra_in[0]  (from cpu_clkgen +)
378 
 
379 
 
380 
   Delay:              23.723ns  (42.1% logic, 57.9% route), 19 logic levels.
381 
 
382 
 Constraint Details:
383 
 
384 
     23.723ns physical path delay cpu0/SLICE_217 to cpu0/regs/SLICE_64 meets
385 
 
386 
      0.000ns skew and
387 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.111ns
388 
 
389 
 Physical Path Details:
390 
 
391 
      Data path cpu0/SLICE_217 to cpu0/regs/SLICE_64:
392 
 
393 
   Name    Fanout   Delay (ns)          Site               Resource
394 
 
395 
ROUTE        27     2.790     R12C15D.Q0 to      R6C24A.A1 cpu0/alu/ra_in[0]
396 
C1TOFCO_DE  ---     0.889      R6C24A.A1 to     R6C24A.FCO cpu0/alu/alu8/a8/SLICE_172
397 
ROUTE         1     0.000     R6C24A.FCO to     R6C24B.FCI cpu0/alu/alu8/a8/q_out_1_cry_0
398 
FCITOF1_DE  ---     0.643     R6C24B.FCI to      R6C24B.F1 cpu0/alu/alu8/a8/SLICE_171
399 
ROUTE         1     1.506      R6C24B.F1 to      R6C22B.C1 cpu0/alu/alu8/a8/q_out_1[2]
400 
C1TOFCO_DE  ---     0.889      R6C22B.C1 to     R6C22B.FCO cpu0/alu/alu8/a8/SLICE_181
401 
ROUTE         1     0.000     R6C22B.FCO to     R6C22C.FCI cpu0/alu/alu8/a8/q_out_1_0_cry_2
402 
FCITOFCO_D  ---     0.162     R6C22C.FCI to     R6C22C.FCO cpu0/alu/alu8/a8/SLICE_180
403 
ROUTE         1     0.000     R6C22C.FCO to     R6C22D.FCI cpu0/alu/alu8/a8/q_out_1_0_cry_4
404 
FCITOF1_DE  ---     0.643     R6C22D.FCI to      R6C22D.F1 cpu0/alu/alu8/a8/SLICE_179
405 
ROUTE         1     2.080      R6C22D.F1 to     R11C17B.C1 cpu0/alu/alu8/a8/N_2393
406 
CTOF_DEL    ---     0.495     R11C17B.C1 to     R11C17B.F1 cpu0/alu/SLICE_1204
407 
ROUTE         1     1.385     R11C17B.F1 to     R12C14C.D0 cpu0/alu/alu8/arith_q[6]
408 
CTOOFX_DEL  ---     0.721     R12C14C.D0 to   R12C14C.OFX0 cpu0/alu/alu8/q_out_4[6]/SLICE_560
409 
ROUTE         1     0.000   R12C14C.OFX0 to    R12C14C.FXB cpu0/alu/alu8/N_159
410 
FXTOOFX_DE  ---     0.241    R12C14C.FXB to   R12C14C.OFX1 cpu0/alu/alu8/q_out_4[6]/SLICE_560
411 
ROUTE         2     1.505   R12C14C.OFX1 to     R12C22C.A1 cpu0/alu/q8_out[6]
412 
CTOOFX_DEL  ---     0.721     R12C22C.A1 to   R12C22C.OFX0 cpu0/alu/alu16/datamux_o_dest[6]/SLICE_541
413 
ROUTE         2     0.772   R12C22C.OFX0 to     R12C21A.C0 cpu0/datamux_o_dest[6]
414 
CTOF_DEL    ---     0.495     R12C21A.C0 to     R12C21A.F0 cpu0/regs/SLICE_889
415 
ROUTE         9     1.224     R12C21A.F0 to     R12C17A.C1 cpu0/regs/left_1[6]
416 
CTOF_DEL    ---     0.495     R12C17A.C1 to     R12C17A.F1 cpu0/regs/SLICE_1125
417 
ROUTE         1     0.958     R12C17A.F1 to     R10C17B.D1 cpu0/regs/N_285
418 
CTOF_DEL    ---     0.495     R10C17B.D1 to     R10C17B.F1 cpu0/regs/SLICE_901
419 
ROUTE         1     0.436     R10C17B.F1 to     R10C17B.C0 cpu0/regs/SU_16[6]
420 
CTOF_DEL    ---     0.495     R10C17B.C0 to     R10C17B.F0 cpu0/regs/SLICE_901
421 
ROUTE         1     1.079     R10C17B.F0 to     R10C19A.C0 cpu0/regs/SU_211_i1_mux
422 
C0TOFCO_DE  ---     1.023     R10C19A.C0 to    R10C19A.FCO cpu0/regs/SLICE_68
423 
ROUTE         1     0.000    R10C19A.FCO to    R10C19B.FCI cpu0/regs/SU_cry[7]
424 
FCITOFCO_D  ---     0.162    R10C19B.FCI to    R10C19B.FCO cpu0/regs/SLICE_67
425 
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI cpu0/regs/SU_cry[9]
426 
FCITOFCO_D  ---     0.162    R10C19C.FCI to    R10C19C.FCO cpu0/regs/SLICE_66
427 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
428 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
429 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
430 
FCITOF1_DE  ---     0.643    R10C20A.FCI to     R10C20A.F1 cpu0/regs/SLICE_64
431 
ROUTE         1     0.000     R10C20A.F1 to    R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
432 
                  --------
433 
                   23.723   (42.1% logic, 57.9% route), 19 logic levels.
434 
 
435 
 Clock Skew Details:
436 
 
437 
      Source Clock Path clk40_i to cpu0/SLICE_217:
438 
 
439 
   Name    Fanout   Delay (ns)          Site               Resource
440 
 
441 
                  --------
442 
 
443 
 
444 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
445 
 
446 
   Name    Fanout   Delay (ns)          Site               Resource
447 
 
448 
                  --------
449 
 
450 
 
451 
 
452 
Passed: The following path meets requirements by 1.112ns
453 
 
454 
 
455 
 
456 
   Source:         FF         Q              cpu0/alu/rb_in[1]  (from cpu_clkgen +)
457 
 
458 
 
459 
 
460 
 
461 
 Constraint Details:
462 
 
463 
     23.722ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 meets
464 
 
465 
      0.000ns skew and
466 
 
467 
 
468 
 Physical Path Details:
469 
 
470 
      Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
471 
 
472 
   Name    Fanout   Delay (ns)          Site               Resource
473 
 
474 
ROUTE        26     1.735     R12C13B.Q1 to     R10C14B.A0 cpu0/alu/rb_in[1]
475 
 
476 
ROUTE         1     0.000    R10C14B.FCO to    R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
477 
FCITOF1_DE  ---     0.643    R10C14C.FCI to     R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
478 
ROUTE         1     1.385     R10C14C.F1 to     R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
479 
CTOF_DEL    ---     0.495     R11C17C.D0 to     R11C17C.F0 cpu0/alu/SLICE_1151
480 
ROUTE         1     1.675     R11C17C.F0 to     R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
481 
C1TOFCO_DE  ---     0.889     R11C21C.C1 to    R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
482 
ROUTE         1     0.000    R11C21C.FCO to    R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
483 
FCITOF0_DE  ---     0.585    R11C21D.FCI to     R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
484 
ROUTE         1     1.705     R11C21D.F0 to      R7C15D.C0 cpu0/alu/alu16/a16/N_2261
485 
CTOF_DEL    ---     0.495      R7C15D.C0 to      R7C15D.F0 cpu0/alu/alu16/SLICE_1209
486 
ROUTE         1     0.958      R7C15D.F0 to      R9C15A.D1 cpu0/alu/alu16/arith_q[5]
487 
CTOOFX_DEL  ---     0.721      R9C15A.D1 to    R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
488 
ROUTE         2     1.285    R9C15A.OFX0 to      R9C22B.C1 cpu0/alu/q16_out[5]
489 
CTOOFX_DEL  ---     0.721      R9C22B.C1 to    R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
490 
ROUTE         2     1.392    R9C22B.OFX0 to     R11C20D.D0 cpu0/datamux_o_dest[5]
491 
CTOF_DEL    ---     0.495     R11C20D.D0 to     R11C20D.F0 cpu0/regs/SLICE_890
492 
ROUTE         9     0.798     R11C20D.F0 to      R9C20D.C1 cpu0/regs/left_1[5]
493 
CTOF_DEL    ---     0.495      R9C20D.C1 to      R9C20D.F1 cpu0/regs/SLICE_1124
494 
ROUTE         1     0.958      R9C20D.F1 to      R8C18A.D1 cpu0/regs/N_284
495 
CTOF_DEL    ---     0.495      R8C18A.D1 to      R8C18A.F1 cpu0/regs/SLICE_900
496 
ROUTE         1     0.626      R8C18A.F1 to      R8C18A.D0 cpu0/regs/SU_16[5]
497 
CTOF_DEL    ---     0.495      R8C18A.D0 to      R8C18A.F0 cpu0/regs/SLICE_900
498 
ROUTE         1     1.079      R8C18A.F0 to     R10C18D.C1 cpu0/regs/SU_210_i1_mux
499 
C1TOFCO_DE  ---     0.889     R10C18D.C1 to    R10C18D.FCO cpu0/regs/SLICE_69
500 
ROUTE         1     0.000    R10C18D.FCO to    R10C19A.FCI cpu0/regs/SU_cry[5]
501 
FCITOFCO_D  ---     0.162    R10C19A.FCI to    R10C19A.FCO cpu0/regs/SLICE_68
502 
ROUTE         1     0.000    R10C19A.FCO to    R10C19B.FCI cpu0/regs/SU_cry[7]
503 
FCITOFCO_D  ---     0.162    R10C19B.FCI to    R10C19B.FCO cpu0/regs/SLICE_67
504 
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI cpu0/regs/SU_cry[9]
505 
FCITOFCO_D  ---     0.162    R10C19C.FCI to    R10C19C.FCO cpu0/regs/SLICE_66
506 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
507 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
508 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
509 
FCITOF0_DE  ---     0.585    R10C20A.FCI to     R10C20A.F0 cpu0/regs/SLICE_64
510 
ROUTE         1     0.000     R10C20A.F0 to    R10C20A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
511 
                  --------
512 
                   23.722   (42.7% logic, 57.3% route), 19 logic levels.
513 
 
514 
 Clock Skew Details:
515 
 
516 
      Source Clock Path clk40_i to cpu0/SLICE_229:
517 
 
518 
   Name    Fanout   Delay (ns)          Site               Resource
519 
 
520 
                  --------
521 
 
522 
 
523 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
524 
 
525 
   Name    Fanout   Delay (ns)          Site               Resource
526 
 
527 
                  --------
528 
 
529 
 
530 
 
531 
Passed: The following path meets requirements by 1.112ns
532 
 
533 
 
534 
 
535 
   Source:         FF         Q              cpu0/k_postbyte[4]  (from cpu_clkgen +)
536 
 
537 
 
538 
 
539 
 
540 
 Constraint Details:
541 
 
542 
     23.722ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_201 meets
543 
 
544 
      0.000ns skew and
545 
 
546 
 
547 
 Physical Path Details:
548 
 
549 
      Data path cpu0/SLICE_1133 to cpu0/SLICE_201:
550 
 
551 
   Name    Fanout   Delay (ns)          Site               Resource
552 
 
553 
ROUTE        21     1.473     R14C26D.Q0 to     R14C25D.B1 cpu0/k_postbyte[4]
554 
 
555 
ROUTE         1     1.525     R14C25D.F1 to     R12C26B.A1 cpu0/dec_op/mode76_0
556 
CTOF_DEL    ---     0.495     R12C26B.A1 to     R12C26B.F1 cpu0/dec_op/SLICE_743
557 
ROUTE         3     0.984     R12C26B.F1 to     R12C26B.A0 cpu0/dec_op/mode76
558 
CTOF_DEL    ---     0.495     R12C26B.A0 to     R12C26B.F0 cpu0/dec_op/SLICE_743
559 
ROUTE         1     1.022     R12C26B.F0 to     R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
560 
CTOF_DEL    ---     0.495     R14C26C.D0 to     R14C26C.F0 cpu0/dec_op/SLICE_739
561 
ROUTE         2     0.632     R14C26C.F0 to     R14C27B.D1 cpu0/dec_op/N_290
562 
CTOF_DEL    ---     0.495     R14C27B.D1 to     R14C27B.F1 cpu0/dec_op/SLICE_700
563 
ROUTE         3     2.174     R14C27B.F1 to     R15C27B.M0 cpu0/dec_op/un1_mode93
564 
MTOOFX_DEL  ---     0.376     R15C27B.M0 to   R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
565 
ROUTE         5     2.393   R15C27B.OFX0 to     R14C23C.B0 cpu0/mode_7[2]
566 
CTOF_DEL    ---     0.495     R14C23C.B0 to     R14C23C.F0 cpu0/SLICE_592
567 
ROUTE        11     0.635     R14C23C.F0 to     R14C23D.D0 cpu0/state81
568 
CTOF_DEL    ---     0.495     R14C23D.D0 to     R14C23D.F0 cpu0/dec_op/SLICE_718
569 
ROUTE         3     1.153     R14C23D.F0 to     R12C24B.D0 cpu0/un1_cpu_reset_11
570 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/SLICE_593
571 
ROUTE        33     1.345     R12C24B.F0 to     R10C24B.A0 cpu0/un1_state_122
572 
C0TOFCO_DE  ---     1.023     R10C24B.A0 to    R10C24B.FCO cpu0/SLICE_195
573 
ROUTE         1     0.000    R10C24B.FCO to    R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
574 
FCITOFCO_D  ---     0.162    R10C24C.FCI to    R10C24C.FCO cpu0/SLICE_194
575 
ROUTE         1     0.000    R10C24C.FCO to    R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
576 
FCITOFCO_D  ---     0.162    R10C24D.FCI to    R10C24D.FCO cpu0/SLICE_193
577 
ROUTE         1     0.000    R10C24D.FCO to    R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
578 
FCITOFCO_D  ---     0.162    R10C25A.FCI to    R10C25A.FCO cpu0/SLICE_192
579 
ROUTE         1     0.000    R10C25A.FCO to    R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
580 
FCITOF1_DE  ---     0.643    R10C25B.FCI to     R10C25B.F1 cpu0/SLICE_191
581 
ROUTE         1     1.498     R10C25B.F1 to     R12C28C.A0 cpu0/un1_k_cpu_addr_1_cry_9_0_S1
582 
CTOF_DEL    ---     0.495     R12C28C.A0 to     R12C28C.F0 cpu0/SLICE_1059
583 
ROUTE         1     0.958     R12C28C.F0 to     R11C26A.D0 cpu0/regs/ea/un1_k_cpu_addr_1_m[10]
584 
CTOF_DEL    ---     0.495     R11C26A.D0 to     R11C26A.F0 cpu0/SLICE_201
585 
ROUTE         1     0.000     R11C26A.F0 to    R11C26A.DI0 cpu0/k_cpu_addr_28[10] (to cpu_clkgen)
586 
                  --------
587 
                   23.722   (33.4% logic, 66.6% route), 17 logic levels.
588 
 
589 
 Clock Skew Details:
590 
 
591 
      Source Clock Path clk40_i to cpu0/SLICE_1133:
592 
 
593 
   Name    Fanout   Delay (ns)          Site               Resource
594 
ROUTE       290     2.399       27.PADDI to    R14C26D.CLK cpu_clkgen
595 
                  --------
596 
 
597 
 
598 
 
599 
 
600 
 
601 
ROUTE       290     2.399       27.PADDI to    R11C26A.CLK cpu_clkgen
602 
                  --------
603 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
604 
 
605 
 
606 
Passed: The following path meets requirements by 1.115ns
607 
 
608 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
609 
 
610 
   Source:         FF         Q              cpu0/alu/rb_in[8]  (from cpu_clkgen +)
611 
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)
612 
 
613 
 
614 
 
615 
 
616 
 
617 
 
618 
     25.000ns delay constraint less
619 
      0.000ns skew and
620 
 
621 
 
622 
 
623 
 
624 
 
625 
 
626 
   Name    Fanout   Delay (ns)          Site               Resource
627 
REG_DEL     ---     0.452    R14C16C.CLK to     R14C16C.Q0 cpu0/SLICE_232 (from cpu_clkgen)
628 
ROUTE         6     1.156     R14C16C.Q0 to     R12C15A.C1 cpu0/alu/rb_in[8]
629 
 
630 
ROUTE         1     1.299     R12C15A.F1 to     R10C15A.A1 cpu0/alu/alu16/a16/rb_in_i[8]
631 
 
632 
ROUTE         1     0.000    R10C15A.FCO to    R10C15B.FCI cpu0/alu/alu16/a16/un8_q_out_cry_8
633 
 
634 
ROUTE         1     0.986     R10C15B.F1 to     R11C15D.A0 cpu0/alu/alu16/a16/un8_q_out[10]
635 
CTOF_DEL    ---     0.495     R11C15D.A0 to     R11C15D.F0 cpu0/alu/SLICE_1213
636 
ROUTE         1     1.675     R11C15D.F0 to     R11C22B.C1 cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0
637 
C1TOFCO_DE  ---     0.889     R11C22B.C1 to    R11C22B.FCO cpu0/alu/alu16/a16/SLICE_112
638 
ROUTE         1     0.000    R11C22B.FCO to    R11C22C.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
639 
FCITOF0_DE  ---     0.585    R11C22C.FCI to     R11C22C.F0 cpu0/alu/alu16/a16/SLICE_111
640 
ROUTE         1     1.072     R11C22C.F0 to      R7C22D.D0 cpu0/alu/alu16/a16/N_2324
641 
CTOF_DEL    ---     0.495      R7C22D.D0 to      R7C22D.F0 cpu0/alu/alu16/SLICE_986
642 
ROUTE         1     0.436      R7C22D.F0 to      R7C22D.C1 cpu0/alu/alu16/arith_q[11]
643 
CTOF_DEL    ---     0.495      R7C22D.C1 to      R7C22D.F1 cpu0/alu/alu16/SLICE_986
644 
ROUTE         1     0.958      R7C22D.F1 to     R10C22C.D1 cpu0/alu/alu16/N_2298
645 
CTOF_DEL    ---     0.495     R10C22C.D1 to     R10C22C.F1 cpu0/alu/alu16/SLICE_1001
646 
ROUTE         2     1.032     R10C22C.F1 to     R12C22D.B1 cpu0/alu/q16_out[11]
647 
CTOF_DEL    ---     0.495     R12C22D.B1 to     R12C22D.F1 cpu0/alu/SLICE_1236
648 
ROUTE         2     0.635     R12C22D.F1 to     R12C22A.D1 cpu0/datamux_o_dest[11]
649 
CTOF_DEL    ---     0.495     R12C22A.D1 to     R12C22A.F1 cpu0/regs/SLICE_941
650 
ROUTE         6     1.479     R12C22A.F1 to     R14C19C.D0 cpu0/regs/left_1[11]
651 
CTOF_DEL    ---     0.495     R14C19C.D0 to     R14C19C.F0 cpu0/regs/SLICE_1193
652 
ROUTE         1     1.035     R14C19C.F0 to     R12C19D.D1 cpu0/regs/N_290
653 
CTOF_DEL    ---     0.495     R12C19D.D1 to     R12C19D.F1 cpu0/regs/SLICE_914
654 
ROUTE         1     0.436     R12C19D.F1 to     R12C19D.C0 cpu0/regs/SU_16[11]
655 
CTOF_DEL    ---     0.495     R12C19D.C0 to     R12C19D.F0 cpu0/regs/SLICE_914
656 
ROUTE         1     1.476     R12C19D.F0 to     R10C19C.C1 cpu0/regs/SU_216_i1_mux
657 
C1TOFCO_DE  ---     0.889     R10C19C.C1 to    R10C19C.FCO cpu0/regs/SLICE_66
658 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
659 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
660 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
661 
FCITOF0_DE  ---     0.585    R10C20A.FCI to     R10C20A.F0 cpu0/regs/SLICE_64
662 
ROUTE         1     0.000     R10C20A.F0 to    R10C20A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
663 
                  --------
664 
                   23.719   (42.3% logic, 57.7% route), 18 logic levels.
665 
 
666 
 Clock Skew Details:
667 
 
668 
      Source Clock Path clk40_i to cpu0/SLICE_232:
669 
 
670 
   Name    Fanout   Delay (ns)          Site               Resource
671 
 
672 
                  --------
673 
 
674 
 
675 
 
676 
 
677 
   Name    Fanout   Delay (ns)          Site               Resource
678 
ROUTE       290     2.399       27.PADDI to    R10C20A.CLK cpu_clkgen
679 
                  --------
680 
 
681 
 
682 
 
683 
Passed: The following path meets requirements by 1.115ns
684 
 
685 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
686 
 
687 
 
688 
 
689 
 
690 
 
691 
 
692 
 
693 
 
694 
     23.719ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_203 meets
695 
 
696 
      0.000ns skew and
697 
 
698 
 
699 
 
700 
 
701 
      Data path cpu0/SLICE_1133 to cpu0/SLICE_203:
702 
 
703 
   Name    Fanout   Delay (ns)          Site               Resource
704 
 
705 
ROUTE        21     1.473     R14C26D.Q0 to     R14C25D.B1 cpu0/k_postbyte[4]
706 
 
707 
ROUTE         1     1.525     R14C25D.F1 to     R12C26B.A1 cpu0/dec_op/mode76_0
708 
 
709 
ROUTE         3     0.984     R12C26B.F1 to     R12C26B.A0 cpu0/dec_op/mode76
710 
CTOF_DEL    ---     0.495     R12C26B.A0 to     R12C26B.F0 cpu0/dec_op/SLICE_743
711 
ROUTE         1     1.022     R12C26B.F0 to     R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
712 
CTOF_DEL    ---     0.495     R14C26C.D0 to     R14C26C.F0 cpu0/dec_op/SLICE_739
713 
ROUTE         2     0.632     R14C26C.F0 to     R14C27B.D1 cpu0/dec_op/N_290
714 
CTOF_DEL    ---     0.495     R14C27B.D1 to     R14C27B.F1 cpu0/dec_op/SLICE_700
715 
ROUTE         3     2.174     R14C27B.F1 to     R15C27B.M0 cpu0/dec_op/un1_mode93
716 
MTOOFX_DEL  ---     0.376     R15C27B.M0 to   R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
717 
ROUTE         5     2.393   R15C27B.OFX0 to     R14C23C.B0 cpu0/mode_7[2]
718 
CTOF_DEL    ---     0.495     R14C23C.B0 to     R14C23C.F0 cpu0/SLICE_592
719 
ROUTE        11     0.635     R14C23C.F0 to     R14C23D.D0 cpu0/state81
720 
CTOF_DEL    ---     0.495     R14C23D.D0 to     R14C23D.F0 cpu0/dec_op/SLICE_718
721 
ROUTE         3     1.153     R14C23D.F0 to     R12C24B.D0 cpu0/un1_cpu_reset_11
722 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/SLICE_593
723 
ROUTE        33     1.345     R12C24B.F0 to     R10C24B.A0 cpu0/un1_state_122
724 
C0TOFCO_DE  ---     1.023     R10C24B.A0 to    R10C24B.FCO cpu0/SLICE_195
725 
ROUTE         1     0.000    R10C24B.FCO to    R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
726 
FCITOFCO_D  ---     0.162    R10C24C.FCI to    R10C24C.FCO cpu0/SLICE_194
727 
ROUTE         1     0.000    R10C24C.FCO to    R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
728 
FCITOFCO_D  ---     0.162    R10C24D.FCI to    R10C24D.FCO cpu0/SLICE_193
729 
ROUTE         1     0.000    R10C24D.FCO to    R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
730 
FCITOFCO_D  ---     0.162    R10C25A.FCI to    R10C25A.FCO cpu0/SLICE_192
731 
ROUTE         1     0.000    R10C25A.FCO to    R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
732 
FCITOFCO_D  ---     0.162    R10C25B.FCI to    R10C25B.FCO cpu0/SLICE_191
733 
ROUTE         1     0.000    R10C25B.FCO to    R10C25C.FCI cpu0/un1_k_cpu_addr_1_cry_10
734 
FCITOFCO_D  ---     0.162    R10C25C.FCI to    R10C25C.FCO cpu0/SLICE_190
735 
ROUTE         1     0.000    R10C25C.FCO to    R10C25D.FCI cpu0/un1_k_cpu_addr_1_cry_12
736 
FCITOF1_DE  ---     0.643    R10C25D.FCI to     R10C25D.F1 cpu0/SLICE_189
737 
ROUTE         1     1.385     R10C25D.F1 to     R12C28A.D0 cpu0/un1_k_cpu_addr_1_cry_13_0_S1
738 
CTOF_DEL    ---     0.495     R12C28A.D0 to     R12C28A.F0 cpu0/SLICE_1246
739 
ROUTE         1     0.744     R12C28A.F0 to     R12C27A.C0 cpu0/alu/un1_k_cpu_addr_1_m[14]
740 
CTOF_DEL    ---     0.495     R12C27A.C0 to     R12C27A.F0 cpu0/SLICE_203
741 
ROUTE         1     0.000     R12C27A.F0 to    R12C27A.DI0 cpu0/k_cpu_addr_28[14] (to cpu_clkgen)
742 
                  --------
743 
                   23.719   (34.8% logic, 65.2% route), 19 logic levels.
744 
 
745 
 Clock Skew Details:
746 
 
747 
      Source Clock Path clk40_i to cpu0/SLICE_1133:
748 
 
749 
   Name    Fanout   Delay (ns)          Site               Resource
750 
 
751 
                  --------
752 
 
753 
 
754 
      Destination Clock Path clk40_i to cpu0/SLICE_203:
755 
 
756 
   Name    Fanout   Delay (ns)          Site               Resource
757 
 
758 
                  --------
759 
 
760 
 
761 
 
762 
Passed: The following path meets requirements by 1.149ns
763 
 
764 
 
765 
 
766 
   Source:         FF         Q              cpu0/alu/rb_in[1]  (from cpu_clkgen +)
767 
 
768 
 
769 
 
770 
 
771 
 Constraint Details:
772 
 
773 
     23.685ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_73 meets
774 
 
775 
      0.000ns skew and
776 
 
777 
 
778 
 Physical Path Details:
779 
 
780 
      Data path cpu0/SLICE_229 to cpu0/regs/SLICE_73:
781 
 
782 
   Name    Fanout   Delay (ns)          Site               Resource
783 
 
784 
ROUTE        26     1.735     R12C13B.Q1 to     R10C14B.A0 cpu0/alu/rb_in[1]
785 
 
786 
ROUTE         1     0.000    R10C14B.FCO to    R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
787 
FCITOF1_DE  ---     0.643    R10C14C.FCI to     R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
788 
ROUTE         1     1.385     R10C14C.F1 to     R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
789 
CTOF_DEL    ---     0.495     R11C17C.D0 to     R11C17C.F0 cpu0/alu/SLICE_1151
790 
ROUTE         1     1.675     R11C17C.F0 to     R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
791 
C1TOFCO_DE  ---     0.889     R11C21C.C1 to    R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
792 
ROUTE         1     0.000    R11C21C.FCO to    R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
793 
FCITOF0_DE  ---     0.585    R11C21D.FCI to     R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
794 
ROUTE         1     1.705     R11C21D.F0 to      R7C15D.C0 cpu0/alu/alu16/a16/N_2261
795 
CTOF_DEL    ---     0.495      R7C15D.C0 to      R7C15D.F0 cpu0/alu/alu16/SLICE_1209
796 
ROUTE         1     0.958      R7C15D.F0 to      R9C15A.D1 cpu0/alu/alu16/arith_q[5]
797 
CTOOFX_DEL  ---     0.721      R9C15A.D1 to    R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
798 
ROUTE         2     1.285    R9C15A.OFX0 to      R9C22B.C1 cpu0/alu/q16_out[5]
799 
CTOOFX_DEL  ---     0.721      R9C22B.C1 to    R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
800 
ROUTE         2     1.392    R9C22B.OFX0 to     R11C20D.D0 cpu0/datamux_o_dest[5]
801 
CTOF_DEL    ---     0.495     R11C20D.D0 to     R11C20D.F0 cpu0/regs/SLICE_890
802 
ROUTE         9     0.798     R11C20D.F0 to      R9C20D.C0 cpu0/regs/left_1[5]
803 
CTOF_DEL    ---     0.495      R9C20D.C0 to      R9C20D.F0 cpu0/regs/SLICE_1124
804 
ROUTE         1     0.626      R9C20D.F0 to      R9C20B.D1 cpu0/regs/N_248
805 
CTOF_DEL    ---     0.495      R9C20B.D1 to      R9C20B.F1 cpu0/regs/SLICE_908
806 
ROUTE         1     0.436      R9C20B.F1 to      R9C20B.C0 cpu0/regs/SS_16[5]
807 
CTOF_DEL    ---     0.495      R9C20B.C0 to      R9C20B.F0 cpu0/regs/SLICE_908
808 
ROUTE         1     1.506      R9C20B.F0 to     R11C18D.C1 cpu0/regs/SS_226_i1_mux
809 
C1TOFCO_DE  ---     0.889     R11C18D.C1 to    R11C18D.FCO cpu0/regs/SLICE_78
810 
ROUTE         1     0.000    R11C18D.FCO to    R11C19A.FCI cpu0/regs/SS_cry[5]
811 
FCITOFCO_D  ---     0.162    R11C19A.FCI to    R11C19A.FCO cpu0/regs/SLICE_77
812 
ROUTE         1     0.000    R11C19A.FCO to    R11C19B.FCI cpu0/regs/SS_cry[7]
813 
FCITOFCO_D  ---     0.162    R11C19B.FCI to    R11C19B.FCO cpu0/regs/SLICE_76
814 
ROUTE         1     0.000    R11C19B.FCO to    R11C19C.FCI cpu0/regs/SS_cry[9]
815 
FCITOFCO_D  ---     0.162    R11C19C.FCI to    R11C19C.FCO cpu0/regs/SLICE_75
816 
ROUTE         1     0.000    R11C19C.FCO to    R11C19D.FCI cpu0/regs/SS_cry[11]
817 
FCITOFCO_D  ---     0.162    R11C19D.FCI to    R11C19D.FCO cpu0/regs/SLICE_74
818 
ROUTE         1     0.000    R11C19D.FCO to    R11C20A.FCI cpu0/regs/SS_cry[13]
819 
FCITOF1_DE  ---     0.643    R11C20A.FCI to     R11C20A.F1 cpu0/regs/SLICE_73
820 
ROUTE         1     0.000     R11C20A.F1 to    R11C20A.DI1 cpu0/regs/SS_s[15] (to cpu_clkgen)
821 
                  --------
822 
                   23.685   (43.0% logic, 57.0% route), 19 logic levels.
823 
 
824 
 Clock Skew Details:
825 
 
826 
      Source Clock Path clk40_i to cpu0/SLICE_229:
827 
 
828 
   Name    Fanout   Delay (ns)          Site               Resource
829 
 
830 
                  --------
831 
 
832 
 
833 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_73:
834 
 
835 
   Name    Fanout   Delay (ns)          Site               Resource
836 
 
837 
                  --------
838 
 
839 
 
840 
Report:   41.761MHz is the maximum frequency for this preference.
841 
 
842 
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
843 
 
844 
 
845 
Preference                              |   Constraint|       Actual|Levels
846 
 
847 
                                        |             |             |
848 
 
849 
MHz ;                                   |   40.000 MHz|   41.761 MHz|  19
850 
                                        |             |             |
851 
 
852 
 
853 
 
854 
All preferences were met.
855 
 
856 
 
857 
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
858 
------------------------
859 
 
860 
 
861 
 
862 
 
863 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
864 
 
865 
 
866 
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
867 
---------------
868 
 
869 
Timing errors: 0  Score: 0
870 
Cumulative negative slack: 0
871 
 
872 
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
873 
 
874 
--------------------------------------------------------------------------------
875 
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>
876 
Mon Jan  6 06:55:04 2014
877 
 
878 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
879 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
880 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
881 
Copyright (c) 2001 Agere Systems   All rights reserved.
882 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
883 
 
884 
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
885 
------------------
886 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
887 
Design file:     P6809_P6809.ncd
888 
Preference file: P6809_P6809.prf
889 
Device,speed:    LCMXO2-7000HE,m
890 
Report level:    verbose report, limited to 10 items per preference
891 
--------------------------------------------------------------------------------
892 
 
893 
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
894 
 
895 
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI>            4096 items scored, 0 timing errors detected.
896 
 
897 
BLOCK ASYNCPATHS
898 
BLOCK RESETPATHS
899 
--------------------------------------------------------------------------------
900 
 
901 
 
902 
 
903 
================================================================================
904 
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
905 
            4096 items scored, 0 timing errors detected.
906 
 
907 
 
908 
 
909 
Passed: The following path meets requirements by 0.180ns
910 
 
911 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
912 
 
913 
   Source:         FF         Q              cpu0/k_cpu_addr[5]  (from cpu_clkgen +)
914 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_3_0(ASIC)  (to cpu_clkgen +)
915 
 
916 
   Delay:               0.304ns  (43.1% logic, 56.9% route), 1 logic levels.
917 
 
918 
 Constraint Details:
919 
 
920 
      0.304ns physical path delay cpu0/SLICE_198 to textctrl/chars/textmem4k_0_3_0 meets
921 
      0.071ns ADDR_HLD and
922 
 
923 
     -0.053ns skew requirement (totaling 0.124ns) by 0.180ns
924 
 
925 
 Physical Path Details:
926 
 
927 
      Data path cpu0/SLICE_198 to textctrl/chars/textmem4k_0_3_0:
928 
 
929 
   Name    Fanout   Delay (ns)          Site               Resource
930 
REG_DEL     ---     0.131    R12C28D.CLK to     R12C28D.Q1 cpu0/SLICE_198 (from cpu_clkgen)
931 
ROUTE         8     0.173     R12C28D.Q1 to *R_R13C27.ADB6 addr_o_c[5] (to cpu_clkgen)
932 
                  --------
933 
                    0.304   (43.1% logic, 56.9% route), 1 logic levels.
934 
 
935 
 
936 
 
937 
      Source Clock Path clk40_i to cpu0/SLICE_198:
938 
 
939 
 
940 
ROUTE       290     0.846       27.PADDI to    R12C28D.CLK cpu_clkgen
941 
                  --------
942 
 
943 
 
944 
 
945 
 
946 
   Name    Fanout   Delay (ns)          Site               Resource
947 
 
948 
 
949 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
950 
 
951 
 
952 
Passed: The following path meets requirements by 0.261ns
953 
 
954 
 
955 
 
956 
 
957 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to cpu_clkgen +)
958 
 
959 
   Delay:               0.385ns  (34.0% logic, 66.0% route), 1 logic levels.
960 
 
961 
 Constraint Details:
962 
 
963 
      0.385ns physical path delay cpu0/SLICE_201 to textctrl/chars/textmem4k_0_2_1 meets
964 
      0.071ns ADDR_HLD and
965 
      0.000ns delay constraint less
966 
 
967 
 
968 
 Physical Path Details:
969 
 
970 
      Data path cpu0/SLICE_201 to textctrl/chars/textmem4k_0_2_1:
971 
 
972 
   Name    Fanout   Delay (ns)          Site               Resource
973 
REG_DEL     ---     0.131    R11C26A.CLK to     R11C26A.Q1 cpu0/SLICE_201 (from cpu_clkgen)
974 
ROUTE         6     0.254     R11C26A.Q1 to *_R13C24.ADB12 addr_o_c[11] (to cpu_clkgen)
975 
 
976 
                    0.385   (34.0% logic, 66.0% route), 1 logic levels.
977 
 
978 
 Clock Skew Details:
979 
 
980 
      Source Clock Path clk40_i to cpu0/SLICE_201:
981 
 
982 
   Name    Fanout   Delay (ns)          Site               Resource
983 
 
984 
 
985 
 
986 
 
987 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
988 
 
989 
   Name    Fanout   Delay (ns)          Site               Resource
990 
 
991 
 
992 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
993 
 
994 
 
995 
 
996 
 
997 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
998 
 
999 
   Source:         FF         Q              cpu0/k_cpu_addr[6]  (from cpu_clkgen +)
1000 
 
1001 
 
1002 
 
1003 
 
1004 
 Constraint Details:
1005 
 
1006 
      0.421ns physical path delay cpu0/SLICE_199 to textctrl/chars/textmem4k_0_2_1 meets
1007 
 
1008 
      0.000ns delay constraint less
1009 
 
1010 
 
1011 
 
1012 
 
1013 
      Data path cpu0/SLICE_199 to textctrl/chars/textmem4k_0_2_1:
1014 
 
1015 
   Name    Fanout   Delay (ns)          Site               Resource
1016 
REG_DEL     ---     0.131    R11C25D.CLK to     R11C25D.Q0 cpu0/SLICE_199 (from cpu_clkgen)
1017 
 
1018 
                  --------
1019 
 
1020 
 
1021 
 
1022 
 
1023 
      Source Clock Path clk40_i to cpu0/SLICE_199:
1024 
 
1025 
   Name    Fanout   Delay (ns)          Site               Resource
1026 
 
1027 
                  --------
1028 
 
1029 
 
1030 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1031 
 
1032 
   Name    Fanout   Delay (ns)          Site               Resource
1033 
 
1034 
 
1035 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1036 
 
1037 
 
1038 
 
1039 
 
1040 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1041 
 
1042 
   Source:         FF         Q              cpu0/alu/alu16/mulu/pipe0[0]  (from cpu_clkgen +)
1043 
 
1044 
 
1045 
 
1046 
 
1047 
 Constraint Details:
1048 
 
1049 
      0.282ns physical path delay cpu0/alu/alu16/mulu/SLICE_210 to cpu0/alu/alu16/mulu/SLICE_133 meets
1050 
 
1051 
      0.000ns delay constraint less
1052 
 
1053 
 
1054 
 
1055 
 
1056 
      Data path cpu0/alu/alu16/mulu/SLICE_210 to cpu0/alu/alu16/mulu/SLICE_133:
1057 
 
1058 
   Name    Fanout   Delay (ns)          Site               Resource
1059 
REG_DEL     ---     0.131     R8C12C.CLK to      R8C12C.Q0 cpu0/alu/alu16/mulu/SLICE_210 (from cpu_clkgen)
1060 
 
1061 
                  --------
1062 
 
1063 
 
1064 
 
1065 
 
1066 
      Source Clock Path clk40_i to cpu0/alu/alu16/mulu/SLICE_210:
1067 
 
1068 
   Name    Fanout   Delay (ns)          Site               Resource
1069 
 
1070 
                  --------
1071 
 
1072 
 
1073 
      Destination Clock Path clk40_i to cpu0/alu/alu16/mulu/SLICE_133:
1074 
 
1075 
   Name    Fanout   Delay (ns)          Site               Resource
1076 
 
1077 
 
1078 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1079 
 
1080 
 
1081 
 
1082 
 
1083 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1084 
 
1085 
   Source:         FF         Q              cpu0/k_cpu_addr[10]  (from cpu_clkgen +)
1086 
 
1087 
 
1088 
 
1089 
 
1090 
 Constraint Details:
1091 
 
1092 
      0.488ns physical path delay cpu0/SLICE_201 to textctrl/chars/textmem4k_0_3_0 meets
1093 
 
1094 
      0.000ns delay constraint less
1095 
 
1096 
 
1097 
 
1098 
 
1099 
      Data path cpu0/SLICE_201 to textctrl/chars/textmem4k_0_3_0:
1100 
 
1101 
   Name    Fanout   Delay (ns)          Site               Resource
1102 
REG_DEL     ---     0.131    R11C26A.CLK to     R11C26A.Q0 cpu0/SLICE_201 (from cpu_clkgen)
1103 
 
1104 
                  --------
1105 
 
1106 
 
1107 
 
1108 
 
1109 
      Source Clock Path clk40_i to cpu0/SLICE_201:
1110 
 
1111 
   Name    Fanout   Delay (ns)          Site               Resource
1112 
 
1113 
                  --------
1114 
 
1115 
 
1116 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_3_0:
1117 
 
1118 
   Name    Fanout   Delay (ns)          Site               Resource
1119 
 
1120 
 
1121 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1122 
 
1123 
 
1124 
 
1125 
 
1126 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1127 
 
1128 
   Source:         FF         Q              textctrl/blink_cnt[0]  (from cpu_clkgen +)
1129 
 
1130 
 
1131 
 
1132 
 
1133 
 Constraint Details:
1134 
 
1135 
      0.357ns physical path delay textctrl/SLICE_29 to textctrl/SLICE_29 meets
1136 
 
1137 
      0.000ns delay constraint less
1138 
 
1139 
 
1140 
 
1141 
 
1142 
      Data path textctrl/SLICE_29 to textctrl/SLICE_29:
1143 
 
1144 
   Name    Fanout   Delay (ns)          Site               Resource
1145 
REG_DEL     ---     0.131    R23C32A.CLK to     R23C32A.Q1 textctrl/SLICE_29 (from cpu_clkgen)
1146 
 
1147 
CTOF_DEL    ---     0.099     R23C32A.A1 to     R23C32A.F1 textctrl/SLICE_29
1148 
 
1149 
                  --------
1150 
 
1151 
 
1152 
 Clock Skew Details:
1153 
 
1154 
      Source Clock Path clk40_i to textctrl/SLICE_29:
1155 
 
1156 
   Name    Fanout   Delay (ns)          Site               Resource
1157 
 
1158 
                  --------
1159 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1160 
 
1161 
      Destination Clock Path clk40_i to textctrl/SLICE_29:
1162 
 
1163 
 
1164 
ROUTE       290     0.828       27.PADDI to    R23C32A.CLK cpu_clkgen
1165 
 
1166 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1167 
 
1168 
 
1169 
Passed: The following path meets requirements by 0.370ns
1170 
 
1171 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1172 
 
1173 
   Source:         FF         Q              textctrl/blink_cnt[1]  (from cpu_clkgen +)
1174 
 
1175 
 
1176 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1177 
 
1178 
 Constraint Details:
1179 
 
1180 
      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
1181 
 
1182 
      0.000ns delay constraint less
1183 
 
1184 
 
1185 
 Physical Path Details:
1186 
 
1187 
      Data path textctrl/SLICE_28 to textctrl/SLICE_28:
1188 
 
1189 
 
1190 
REG_DEL     ---     0.131    R23C32B.CLK to     R23C32B.Q0 textctrl/SLICE_28 (from cpu_clkgen)
1191 
 
1192 
CTOF_DEL    ---     0.099     R23C32B.A0 to     R23C32B.F0 textctrl/SLICE_28
1193 
 
1194 
                  --------
1195 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1196 
 
1197 
 Clock Skew Details:
1198 
 
1199 
      Source Clock Path clk40_i to textctrl/SLICE_28:
1200 
 
1201 
   Name    Fanout   Delay (ns)          Site               Resource
1202 
ROUTE       290     0.828       27.PADDI to    R23C32B.CLK cpu_clkgen
1203 
                  --------
1204 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1205 
 
1206 
 
1207 
 
1208 
 
1209 
ROUTE       290     0.828       27.PADDI to    R23C32B.CLK cpu_clkgen
1210 
 
1211 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1212 
 
1213 
 
1214 
Passed: The following path meets requirements by 0.370ns
1215 
 
1216 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1217 
 
1218 
   Source:         FF         Q              textctrl/blink_cnt[3]  (from cpu_clkgen +)
1219 
   Destination:    FF         Data in        textctrl/blink_cnt[3]  (to cpu_clkgen +)
1220 
 
1221 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1222 
 
1223 
 Constraint Details:
1224 
 
1225 
      0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
1226 
 
1227 
      0.000ns delay constraint less
1228 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1229 
 
1230 
 Physical Path Details:
1231 
 
1232 
      Data path textctrl/SLICE_27 to textctrl/SLICE_27:
1233 
 
1234 
 
1235 
REG_DEL     ---     0.131    R23C32C.CLK to     R23C32C.Q0 textctrl/SLICE_27 (from cpu_clkgen)
1236 
 
1237 
CTOF_DEL    ---     0.099     R23C32C.A0 to     R23C32C.F0 textctrl/SLICE_27
1238 
 
1239 
                  --------
1240 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1241 
 
1242 
 Clock Skew Details:
1243 
 
1244 
      Source Clock Path clk40_i to textctrl/SLICE_27:
1245 
 
1246 
   Name    Fanout   Delay (ns)          Site               Resource
1247 
ROUTE       290     0.828       27.PADDI to    R23C32C.CLK cpu_clkgen
1248 
                  --------
1249 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1250 
 
1251 
 
1252 
 
1253 
 
1254 
ROUTE       290     0.828       27.PADDI to    R23C32C.CLK cpu_clkgen
1255 
 
1256 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1257 
 
1258 
 
1259 
Passed: The following path meets requirements by 0.370ns
1260 
 
1261 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1262 
 
1263 
   Source:         FF         Q              textctrl/blink_cnt[2]  (from cpu_clkgen +)
1264 
   Destination:    FF         Data in        textctrl/blink_cnt[2]  (to cpu_clkgen +)
1265 
 
1266 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1267 
 
1268 
 Constraint Details:
1269 
 
1270 
      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
1271 
 
1272 
      0.000ns delay constraint less
1273 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1274 
 
1275 
 Physical Path Details:
1276 
 
1277 
      Data path textctrl/SLICE_28 to textctrl/SLICE_28:
1278 
 
1279 
 
1280 
REG_DEL     ---     0.131    R23C32B.CLK to     R23C32B.Q1 textctrl/SLICE_28 (from cpu_clkgen)
1281 
 
1282 
CTOF_DEL    ---     0.099     R23C32B.A1 to     R23C32B.F1 textctrl/SLICE_28
1283 
 
1284 
                  --------
1285 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1286 
 
1287 
 Clock Skew Details:
1288 
 
1289 
      Source Clock Path clk40_i to textctrl/SLICE_28:
1290 
 
1291 
   Name    Fanout   Delay (ns)          Site               Resource
1292 
ROUTE       290     0.828       27.PADDI to    R23C32B.CLK cpu_clkgen
1293 
                  --------
1294 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1295 
 
1296 
 
1297 
 
1298 
 
1299 
ROUTE       290     0.828       27.PADDI to    R23C32B.CLK cpu_clkgen
1300 
 
1301 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1302 
 
1303 
 
1304 
Passed: The following path meets requirements by 0.370ns
1305 
 
1306 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1307 
 
1308 
   Source:         FF         Q              cpu0/k_cpu_addr[3]  (from cpu_clkgen +)
1309 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to cpu_clkgen +)
1310 
 
1311 
   Delay:               0.494ns  (26.5% logic, 73.5% route), 1 logic levels.
1312 
 
1313 
 Constraint Details:
1314 
 
1315 
      0.494ns physical path delay cpu0/SLICE_197 to textctrl/chars/textmem4k_0_2_1 meets
1316 
 
1317 
      0.000ns delay constraint less
1318 
     -0.053ns skew requirement (totaling 0.124ns) by 0.370ns
1319 
 
1320 
 Physical Path Details:
1321 
 
1322 
      Data path cpu0/SLICE_197 to textctrl/chars/textmem4k_0_2_1:
1323 
 
1324 
 
1325 
REG_DEL     ---     0.131    R12C25A.CLK to     R12C25A.Q1 cpu0/SLICE_197 (from cpu_clkgen)
1326 
 
1327 
                  --------
1328 
 
1329 
 
1330 
 Clock Skew Details:
1331 
 
1332 
      Source Clock Path clk40_i to cpu0/SLICE_197:
1333 
 
1334 
   Name    Fanout   Delay (ns)          Site               Resource
1335 
 
1336 
                  --------
1337 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1338 
 
1339 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1340 
 
1341 
 
1342 
ROUTE       290     0.899       27.PADDI to *R_R13C24.CLKB cpu_clkgen
1343 
 
1344 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1345 
 
1346 
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
1347 
--------------
1348 
 
1349 
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
1350 
 
1351 
                                        |             |             |
1352 
 
1353 
MHz ;                                   |            -|            -|   1
1354 
                                        |             |             |
1355 
----------------------------------------------------------------------------
1356 
 
1357 
 
1358 
All preferences were met.
1359 
 
1360 
 
1361 
 
1362 
------------------------
1363 
 
1364 
Found 1 clocks:
1365 
 
1366 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 290
1367 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
1368 
 
1369 
 
1370 
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
1371 
 
1372 
 
1373 
 
1374 
Cumulative negative slack: 0
1375 
 
1376 
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
1377 
 
1378 
 
1379 
 
1380 
 
1381 
---------------
1382 
 
1383 
Timing errors: 0 (setup), 0 (hold)
1384 
Score: 0 (setup), 0 (hold)
1385 
 
1386 
 
1387 
 
1388 
 
1389 
 
1390 
 
1391 
 
1392 
 
1393 
 
1394 
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1395 
 
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