Subversion Repositories 6809_6309_compatible_core

synpwrap -prj "P6809_P6809_synplify.tcl" -log "P6809_P6809.srf"

*****************************************************************

Warning: You are running on an unsupported platform

  'synplify_pro' only supports Red Hat Enterprise Linux 4.0 and above

  current platform: CentOS release 6.4 (Final)

Kernel \r on an \m

*****************************************************************

Running in Lattice mode

Starting:    /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatch

Install:     /usr/local/diamond/2.2_x64/synpbase

Date:        Wed Jan  1 11:05:21 2014

Version:     G-2012.09L-SP1

Arguments:   -product synplify_pro  -batch P6809_P6809_synplify.tcl

ProductType: synplify_pro

log file: "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr"

Running proj_1|P6809

Running Compile on proj_1|P6809

Running Compile Process on proj_1|P6809

Running Compile Input on proj_1|P6809

Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srs

compiler Completed with warnings

Return Code: 1

Run Time:00h:00m:04s

Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf

Job Compile Process completed on proj_1|P6809

Running Premap on proj_1|P6809

premap Completed with warnings

Return Code: 1

Run Time:00h:00m:00s

Job Compile completed on proj_1|P6809

Running Map on proj_1|P6809

Running Map & Optimize on proj_1|P6809

fpga_mapper Completed with warnings

Return Code: 1

Run Time:00h:00m:16s

Job Map completed on proj_1|P6809

Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf

Job Logic Synthesis completed on proj_1|P6809

TCL script complete: "P6809_P6809_synplify.tcl"

exit status=0

Copyright (C) 1992-2013 Lattice Semiconductor Corporation. All rights reserved.

Lattice Diamond Version 2.2.0.101

Child process exit with 0.

==contents of P6809_P6809.srf

#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013

#install: /usr/local/diamond/2.2_x64/synpbase

#OS: Linux

#Hostname: node01.pacito.sys

#Implementation: P6809

$ Start of Compile

#Wed Jan  1 11:05:21 2014

Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013

@N|Running in 64-bit mode

Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"

@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"

@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"

@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":727:23:727:27|Specified digits overflow the number's size

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"

Verilog syntax check successful!

Options changed - recompiling

Selecting top level module CC3_top

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":57:7:57:10|Synthesizing module alu8

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:5:85:12|No assignment to wire cadd16_w

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:15:85:22|No assignment to wire cadc16_w

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:25:85:32|No assignment to wire csub16_w

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:35:85:42|No assignment to wire csbc16_w

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":184:12:184:13|No assignment to n8

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":184:20:184:21|No assignment to z8

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":650:7:650:12|Synthesizing module mul8x8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":645:0:645:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":433:12:433:18|No assignment to wire q16_mul

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":561:0:561:5|Pruning register regq16[15:0]

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu

@W: CS263 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":32:18:32:28|Port-width mismatch for port a_in. Formal has width 16, Actual 8

@W: CS263 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":32:30:32:40|Port-width mismatch for port b_in. Formal has width 16, Actual 8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":243:0:243:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":131:7:131:15|Synthesizing module decode_op

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":259:7:259:15|Synthesizing module decode_ea

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":285:7:285:16|Synthesizing module decode_alu

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":358:7:358:20|Synthesizing module test_condition

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":445:6:445:13|Ignoring system task $display

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1017:0:1017:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register bit k_mem_dest[0] is always 1, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register bit next_mem_state[2] is always 0, optimizing ...

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k

@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Pruning register bits 5 to 3 of next_push_state[5:0]

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":362:18:362:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":287:18:287:26|Input port bits 5 to 4 of postbyte0[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":260:18:260:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Pruning register bits 15 to 13 of pipe0[15:0]

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Register bit pipe0[12] is always 0, optimizing ...

@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Pruning register bit 12 of pipe0[12:0]

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":59:19:59:22|Input port bits 15 to 8 of a_in[15:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":60:19:60:22|Input port bits 15 to 8 of b_in[15:0] are unused

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":58:12:58:17|Input clk_in is unused

@END

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

# Wed Jan  1 11:05:23 2014

###########################################################]

Premap Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46

Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

Product Version G-2012.09L-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt

Printing clock  summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file

@N: MF248 |Running in 64-bit mode.

@N: MF666 |Clock conversion enabled

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)

Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)

Clock Summary

**************

Start                             Requested     Requested     Clock                              Clock

Clock                             Frequency     Period        Type                               Group

--------------------------------------------------------------------------------------------------------------------

CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0

CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0

====================================================================================================================

@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 1 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

syn_allowed_resources : blockrams=26  set on top level netlist CC3_top

Finished Pre Mapping Phase.Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 136MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

# Wed Jan  1 11:05:25 2014

###########################################################]

Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46

Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

Product Version G-2012.09L-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

@N: MF248 |Running in 64-bit mode.

@N: MF666 |Clock conversion enabled

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)

Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)

Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

Available hyper_sources - for debug and ip models

        None Found

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Found counter in view:work.regblock(verilog) inst PC[15:0]

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 156MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 156MB)

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 162MB)

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":237:2:237:3|Pipelining module un1_ea_reg_2[15:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SU[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register ACCB[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register DP[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SS[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IX[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IY[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register cff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":35:0:35:5|Register rb_in[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register vff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register zff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register nff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register intff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register hflag pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register fflag pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":35:0:35:5|Register ra_in[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register k_memlo[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register k_ind_ea[7:0] pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":280:2:280:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]

Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 150MB peak: 162MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 150MB peak: 162MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 162MB)

Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 148MB peak: 162MB)

Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 189MB peak: 227MB)

Pass             CPU time               Worst Slack             Luts / Registers

------------------------------------------------------------

Pass             CPU time               Worst Slack             Luts / Registers

------------------------------------------------------------

------------------------------------------------------------

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 164MB peak: 227MB)

@N: FX164 |The option to pack flops in the IOB has not been specified

Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 227MB)

#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 504 clock pin(s) of sequential element(s)

233 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================

Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance

---------------------------------------------------------------------------------------

@K:CKID0001       clk40_i             port                   504        cpu_clk

=======================================================================================

===== Gated/Generated Clocks =====

************** None **************

----------------------------------

==================================

##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 169MB peak: 227MB)

Writing EDIF Netlist and constraint files

G-2012.09L-SP1

@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 173MB peak: 227MB)

@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"

##### START OF TIMING REPORT #####[

# Timing Report written on Wed Jan  1 11:05:41 2014

#

Top view:               CC3_top

Requested Frequency:    1.0 MHz

Wire load mode:         top

Paths requested:        5

Constraint File(s):

@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.

Performance Summary

*******************

Worst slack in design: 978.215

                    Requested     Estimated     Requested     Estimated                 Clock        Clock

Starting Clock      Frequency     Frequency     Period        Period        Slack       Type         Group

------------------------------------------------------------------------------------------------------------------------

CC3_top|clk40_i     1.0 MHz       45.9 MHz      1000.000      21.785        978.215     inferred     Inferred_clkgroup_0

========================================================================================================================

Clock Relationships

*******************

Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise

--------------------------------------------------------------------------------------------------------------------------

Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack

--------------------------------------------------------------------------------------------------------------------------

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.215  |  No paths    -      |  No paths    -      |  No paths    -

==========================================================================================================================

 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.

       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

Interface Information

*********************

No IO constraint found

====================================

Detailed Report for Clock: CC3_top|clk40_i

====================================

Starting Points with Worst Slack

********************************

                          Starting                                                          Arrival

Instance                  Reference           Type        Pin     Net                       Time        Slack

                          Clock

---------------------------------------------------------------------------------------------------------------

cpu0.k_opcode[2]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[2]               1.374       978.215

cpu0.k_opcode[0]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]               1.361       978.228

cpu0.k_opcode[1]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]               1.366       978.263

cpu0.k_opcode[6]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[6]               1.336       978.293

cpu0.k_opcode[7]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[7]               1.352       978.341

cpu0.regs.SU_pipe_100     CC3_top|clk40_i     FD1P3AX     Q       un1_SU_4_sqmuxaf          1.268       978.356

cpu0.regs.SU_pipe_102     CC3_top|clk40_i     FD1P3AX     Q       SU_1_sqmuxa_5f            1.268       978.356

cpu0.regs.SS_pipe_100     CC3_top|clk40_i     FD1P3AX     Q       SS_1_sqmuxa_2f            1.268       978.420

cpu0.regs.SS_pipe_102     CC3_top|clk40_i     FD1P3AX     Q       un1_SU_0_sqmuxa_1_snf     1.268       978.420

cpu0.k_opcode[3]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[3]               1.385       978.484

===============================================================================================================

Ending Points with Worst Slack

******************************

                     Starting                                             Required

Instance             Reference           Type        Pin     Net          Time         Slack

                     Clock

----------------------------------------------------------------------------------------------

cpu0.regs.PC[14]     CC3_top|clk40_i     FD1P3AX     D       PC_s[14]     999.894      978.215

cpu0.regs.PC[15]     CC3_top|clk40_i     FD1P3AX     D       PC_s[15]     999.894      978.215

cpu0.regs.PC[12]     CC3_top|clk40_i     FD1P3AX     D       PC_s[12]     999.894      978.358

cpu0.regs.PC[13]     CC3_top|clk40_i     FD1P3AX     D       PC_s[13]     999.894      978.358

cpu0.regs.PC[10]     CC3_top|clk40_i     FD1P3AX     D       PC_s[10]     999.894      978.501

cpu0.regs.PC[11]     CC3_top|clk40_i     FD1P3AX     D       PC_s[11]     999.894      978.501

cpu0.regs.PC[8]      CC3_top|clk40_i     FD1P3AX     D       PC_s[8]      999.894      978.644

cpu0.regs.PC[9]      CC3_top|clk40_i     FD1P3AX     D       PC_s[9]      999.894      978.644

cpu0.regs.PC[6]      CC3_top|clk40_i     FD1P3AX     D       PC_s[6]      999.894      978.786

cpu0.regs.PC[7]      CC3_top|clk40_i     FD1P3AX     D       PC_s[7]      999.894      978.786

==============================================================================================

Worst Path Information

***********************

Path information for path number 1:

      Requested Period:                      1000.000

    - Setup time:                            0.106

    + Clock delay at ending point:           0.000 (ideal)

    = Required time:                         999.894

    - Propagation time:                      21.679

    - Clock delay at starting point:         0.000 (ideal)

    = Slack (critical) :                     978.215

    Number of logic level(s):                22

    Starting point:                          cpu0.k_opcode[2] / Q

    Ending point:                            cpu0.regs.PC[15] / D

    The start point is clocked by            CC3_top|clk40_i [rising] on pin CK

    The end   point is clocked by            CC3_top|clk40_i [rising] on pin CK

Instance / Net                                                         Pin      Pin               Arrival     No. of

Name                                                      Type         Name     Dir     Delay     Time        Fan Out(s)

------------------------------------------------------------------------------------------------------------------------

cpu0.k_opcode[2]                                          FD1P3AX      Q        Out     1.374     1.374       -

k_opcode[2]                                               Net          -        -       -         -           63

cpu0.dec_regs.state_3_sqmuxa_1                            ORCALUT4     B        In      0.000     1.374       -

cpu0.dec_regs.state_3_sqmuxa_1                            ORCALUT4     Z        Out     1.193     2.567       -

state_3_sqmuxa_1                                          Net          -        -       -         -           4

cpu0.dec_op.mode_4_i_a2[0]                                ORCALUT4     C        In      0.000     2.567       -

cpu0.dec_op.mode_4_i_a2[0]                                ORCALUT4     Z        Out     1.193     3.760       -

dest_reg_5_sqmuxa                                         Net          -        -       -         -           4

cpu0.dec_regs.un1_dest_reg44_1_1                          ORCALUT4     B        In      0.000     3.760       -

cpu0.dec_regs.un1_dest_reg44_1_1                          ORCALUT4     Z        Out     1.017     4.777       -

un1_dest_reg44_1_1                                        Net          -        -       -         -           1

cpu0.dec_regs.un1_dest_reg44_1_2                          ORCALUT4     D        In      0.000     4.777       -

cpu0.dec_regs.un1_dest_reg44_1_2                          ORCALUT4     Z        Out     1.017     5.793       -

un1_dest_reg44_1_2                                        Net          -        -       -         -           1

cpu0.dec_regs.un1_dest_reg44_1                            ORCALUT4     A        In      0.000     5.793       -

cpu0.dec_regs.un1_dest_reg44_1                            ORCALUT4     Z        Out     1.153     6.946       -

un1_dest_reg44_1                                          Net          -        -       -         -           3

cpu0.dec_regs.path_left_addr_2_sqmuxa                     ORCALUT4     B        In      0.000     6.946       -

cpu0.dec_regs.path_left_addr_2_sqmuxa                     ORCALUT4     Z        Out     1.089     8.035       -

path_left_addr_2_sqmuxa                                   Net          -        -       -         -           2

cpu0.dec_regs.path_left_addr_1_sqmuxa_2                   ORCALUT4     A        In      0.000     8.035       -

cpu0.dec_regs.path_left_addr_1_sqmuxa_2                   ORCALUT4     Z        Out     1.225     9.260       -

path_left_addr_1_sqmuxa_2                                 Net          -        -       -         -           5

cpu0.dec_regs.k_write_exg10_1_RNITDRD5                    ORCALUT4     A        In      0.000     9.260       -

cpu0.dec_regs.k_write_exg10_1_RNITDRD5                    ORCALUT4     Z        Out     1.193     10.453      -

path_left_addr_sn_N_2                                     Net          -        -       -         -           4

cpu0.dec_regs.path_left_addr[3]                           PFUMX        C0       In      0.000     10.453      -

cpu0.dec_regs.path_left_addr[3]                           PFUMX        Z        Out     1.089     11.542      -

dec_o_left_path_addr[3]                                   Net          -        -       -         -           4

cpu0.regs.datamux_o_alu_in_left_path_addr[3]              ORCALUT4     A        In      0.000     11.542      -

cpu0.regs.datamux_o_alu_in_left_path_addr[3]              ORCALUT4     Z        Out     1.369     12.910      -

datamux_o_alu_in_left_path_addr[3]                        Net          -        -       -         -           34

cpu0.regs.datamux_o_alu_in_left_path_addr_RNIUORB1[1]     ORCALUT4     D        In      0.000     12.910      -

cpu0.regs.datamux_o_alu_in_left_path_addr_RNIUORB1[1]     ORCALUT4     Z        Out     1.313     14.223      -

N_784                                                     Net          -        -       -         -           16

cpu0.regs.path_left_data_bm[3]                            ORCALUT4     C        In      0.000     14.223      -

cpu0.regs.path_left_data_bm[3]                            ORCALUT4     Z        Out     1.017     15.240      -

path_left_data_bm[3]                                      Net          -        -       -         -           1

cpu0.regs.path_left_data[3]                               PFUMX        ALUT     In      0.000     15.240      -

cpu0.regs.path_left_data[3]                               PFUMX        Z        Out     0.350     15.590      -

regs_o_left_path_data[3]                                  Net          -        -       -         -           3

cpu0.regs.path_left_data_RNIU3J91[3]                      ORCALUT4     A        In      0.000     15.590      -

cpu0.regs.path_left_data_RNIU3J91[3]                      ORCALUT4     Z        Out     1.265     16.855      -

left_1[3]                                                 Net          -        -       -         -           8

cpu0.regs.PC_11[3]                                        ORCALUT4     C        In      0.000     16.855      -

cpu0.regs.PC_11[3]                                        ORCALUT4     Z        Out     1.017     17.872      -

PC_11[3]                                                  Net          -        -       -         -           1

cpu0.regs.PC_cry_0[2]                                     CCU2D        B1       In      0.000     17.872      -

cpu0.regs.PC_cry_0[2]                                     CCU2D        COUT     Out     1.544     19.416      -

PC_cry[3]                                                 Net          -        -       -         -           1

cpu0.regs.PC_cry_0[4]                                     CCU2D        CIN      In      0.000     19.416      -

cpu0.regs.PC_cry_0[4]                                     CCU2D        COUT     Out     0.143     19.559      -

PC_cry[5]                                                 Net          -        -       -         -           1

cpu0.regs.PC_cry_0[6]                                     CCU2D        CIN      In      0.000     19.559      -

cpu0.regs.PC_cry_0[6]                                     CCU2D        COUT     Out     0.143     19.702      -

PC_cry[7]                                                 Net          -        -       -         -           1

cpu0.regs.PC_cry_0[8]                                     CCU2D        CIN      In      0.000     19.702      -

cpu0.regs.PC_cry_0[8]                                     CCU2D        COUT     Out     0.143     19.845      -

PC_cry[9]                                                 Net          -        -       -         -           1

cpu0.regs.PC_cry_0[10]                                    CCU2D        CIN      In      0.000     19.845      -

cpu0.regs.PC_cry_0[10]                                    CCU2D        COUT     Out     0.143     19.988      -

PC_cry[11]                                                Net          -        -       -         -           1

cpu0.regs.PC_cry_0[12]                                    CCU2D        CIN      In      0.000     19.988      -

cpu0.regs.PC_cry_0[12]                                    CCU2D        COUT     Out     0.143     20.130      -

PC_cry[13]                                                Net          -        -       -         -           1

cpu0.regs.PC_cry_0[14]                                    CCU2D        CIN      In      0.000     20.130      -

cpu0.regs.PC_cry_0[14]                                    CCU2D        S1       Out     1.549     21.679      -

PC_s[15]                                                  Net          -        -       -         -           1

cpu0.regs.PC[15]                                          FD1P3AX      D        In      0.000     21.679      -

========================================================================================================================

##### END OF TIMING REPORT #####]

---------------------------------------

Resource Usage Report

Part: lcmxo2_7000he-4

Register bits: 500 of 6864 (7%)

PIC Latch:       0

I/O cells:       49

Block Rams : 2 of 26 (7%)

Details:

CCU2D:          160

DP8KC:          2

FD1P3AX:        484

FD1P3DX:        6

FD1P3IX:        1

FD1S3AX:        1

GSR:            1

IB:             1

INV:            13

L6MUX21:        31

OB:             48

OFS1P3DX:       8

ORCALUT4:       1933

PFUMX:          308

PUR:            1

VHI:            8

VLO:            13

true:           5

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 44MB peak: 227MB)

Process took 0h:00m:15s realtime, 0h:00m:15s cputime

# Wed Jan  1 11:05:41 2014

###########################################################]

Synthesis exit by 0.

edif2ngd  -l "MachXO2" -d LCMXO2-7000HE -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi" "P6809_P6809.ngo"

edif2ngd:  version Diamond (64-bit) 2.2.0.101

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.

Copyright (c) 1995 AT&T Corp.   All rights reserved.

Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.

Copyright (c) 2001 Agere Systems   All rights reserved.

Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...

  On or above line 280 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...

  On or above line 288 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 1928 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 5198 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 9990 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 10297 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 11284 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 11361 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 12803 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 15684 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 29797 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 32207 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 32625 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 38016 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...

  On or above line 38686 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

Writing the design to P6809_P6809.ngo...

ngdbuild  -a "MachXO2" -d LCMXO2-7000HE  -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data"  -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "P6809_P6809.ngo" "P6809_P6809.ngd"

ngdbuild:  version Diamond (64-bit) 2.2.0.101

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.

Copyright (c) 1995 AT&T Corp.   All rights reserved.

Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.

Copyright (c) 2001 Agere Systems   All rights reserved.

Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Reading 'P6809_P6809.ngo' ...

Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...

Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data/xo2clib.ngl'...

Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/mg5g00/data/mg5glib.ngl'...

Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...

Running DRC...

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_8_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_8_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_8_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sbc16_w_cry_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sbc16_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_13_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_13_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_11_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_11_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_9_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_9_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_7_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_7_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_5_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_5_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_3_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_3_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_1_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_1_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sbc8_w_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sbc8_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_s_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_s_7_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_5_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_5_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_3_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_3_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_1_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_1_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/PC_cry_0_COUT[14]' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no load

WARNING - ngdbuild: DRC complete with 96 warnings

Design Results:

   3018 blocks expanded

complete the first expansion

Writing 'P6809_P6809.ngd' ...

map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial   "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0

map:  version Diamond (64-bit) 2.2.0.101

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.

Copyright (c) 1995 AT&T Corp.   All rights reserved.

Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.

Copyright (c) 2001 Agere Systems   All rights reserved.

Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

   Process the file: P6809_P6809.ngd

   Picdevice="LCMXO2-7000HE"

   Pictype="TQFP144"

   Picspeed=4

   Remove unused logic

   Do not produce over sized NCDs.

Part used: LCMXO2-7000HETQFP144, Performance used: 4.

Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.

Package Status:                     Final          Version 1.36

Running general design DRC...

Removing unused logic...

Optimizing...

7 CCU2 constant inputs absorbed.

WARNING - map: Using local reset signal 'cpu0.cpu_reset_i_3_i' to infer global GSR net.

WARNING - map: The reset of EBR 'bios/bios2k_0_1_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.

WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.

Design Summary:

   Number of registers:    500

      PFU registers:    492

      PIO registers:    8

   Number of SLICEs:          1135 out of  3432 (33%)

      SLICEs(logic/ROM):       858 out of   858 (100%)

      SLICEs(logic/ROM/RAM):   277 out of  2574 (11%)

          As RAM:            0 out of  2574 (0%)

          As Logic/ROM:    277 out of  2574 (11%)

   Number of logic LUT4s:     1946

   Number of distributed RAM:   0 (0 LUT4s)

   Number of ripple logic:    160 (320 LUT4s)

   Number of shift registers:   0

   Total number of LUT4s:     2266

   Number of PIO sites used: 49 + 4(JTAG) out of 115 (46%)

   Number of block RAMs:  2 out of 26 (8%)

   Number of GSRs:  1 out of 1 (100%)

   EFB used :       No

   JTAG used :      No

   Readback used :  No

   Oscillator used :  No

   Startup used :   No

   POR :            On

   Bandgap :        On

   Number of Power Controller:  0 out of 1 (0%)

   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)

   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)

   Number of DCCA:  0 out of 8 (0%)