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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [automake.log] - Blame information for rev 9

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Line No. Rev Author Line
1 4 ale500 
 
2 
synpwrap -prj "P6809_P6809_synplify.tcl" -log "P6809_P6809.srf"
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*****************************************************************
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Warning: You are running on an unsupported platform
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  'synplify_pro' only supports Red Hat Enterprise Linux 4.0 and above
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  current platform: CentOS release 6.4 (Final)
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Kernel \r on an \m
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*****************************************************************
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Running in Lattice mode
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Starting:    /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatch
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Install:     /usr/local/diamond/2.2_x64/synpbase
19 9 ale500 
Date:        Mon Jan  6 06:54:11 2014
20 4 ale500 
Version:     G-2012.09L-SP1
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Arguments:   -product synplify_pro  -batch P6809_P6809_synplify.tcl
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ProductType: synplify_pro
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log file: "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr"
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33 
Running proj_1|P6809
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35 
Running Compile on proj_1|P6809
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Running Compile Process on proj_1|P6809
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Running Compile Input on proj_1|P6809
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41 
Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srs
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43 
compiler Completed with warnings
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Return Code: 1
45 9 ale500 
Run Time:00h:00m:03s
46 4 ale500 
 
47 
 
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Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
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Job Compile Process completed on proj_1|P6809
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Running Premap on proj_1|P6809
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54 
premap Completed with warnings
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Return Code: 1
56 7 ale500 
Run Time:00h:00m:01s
57 4 ale500 
 
58 
 
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Job Compile completed on proj_1|P6809
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Running Map on proj_1|P6809
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Running Map & Optimize on proj_1|P6809
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65 
fpga_mapper Completed with warnings
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Return Code: 1
67 9 ale500 
Run Time:00h:00m:14s
68 4 ale500 
 
69 
 
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Job Map completed on proj_1|P6809
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Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
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Job Logic Synthesis completed on proj_1|P6809
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TCL script complete: "P6809_P6809_synplify.tcl"
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exit status=0
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Copyright (C) 1992-2013 Lattice Semiconductor Corporation. All rights reserved.
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Lattice Diamond Version 2.2.0.101
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Child process exit with 0.
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==contents of P6809_P6809.srf
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#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
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#install: /usr/local/diamond/2.2_x64/synpbase
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#OS: Linux
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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$ Start of Compile
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#Mon Jan  6 06:54:11 2014
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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100 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
101 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
102 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
103 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
104 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
105 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
106 
@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
107 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
108 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
109 
@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
110 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
111 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
112 9 ale500 
@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":699:23:699:27|Specified digits overflow the number's size
113 4 ale500 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
114 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
115 7 ale500 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
116 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
117 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
118 4 ale500 
Verilog syntax check successful!
119 7 ale500 
File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling
120 4 ale500 
Selecting top level module CC3_top
121 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
122 4 ale500 
 
123 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
124 6 ale500 
 
125 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":157:7:157:12|Synthesizing module shift8
126 6 ale500 
 
127 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":197:7:197:10|Synthesizing module alu8
128 6 ale500 
 
129 9 ale500 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
130 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:12:240:13|No assignment to n8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:20:240:21|No assignment to z8
132 6 ale500 
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]
133 
 
134 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":603:7:603:12|Synthesizing module mul8x8
135 6 ale500 
 
136 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":128:7:128:13|Synthesizing module arith16
137 
 
138 6 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16
139 
 
140 9 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":411:23:411:29|No assignment to wire arith_h
141 6 ale500 
 
142 9 ale500 
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":517:0:517:5|Pruning register regq16[15:0]
143 6 ale500 
 
144 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
145 
 
146 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
147 
 
148 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
149 
 
150 9 ale500 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
151 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
152 
 
153 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":138:7:138:15|Synthesizing module decode_op
154 4 ale500 
 
155 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":266:7:266:15|Synthesizing module decode_ea
156 4 ale500 
 
157 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:7:292:16|Synthesizing module decode_alu
158 4 ale500 
 
159 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
160 4 ale500 
 
161 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
162 
 
163 9 ale500 
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":418:6:418:13|Ignoring system task $display
164 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1039:0:1039:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
165 6 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result
166 4 ale500 
 
167 6 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR
168 
 
169 9 ale500 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
170 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
171 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
172 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
173 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
174 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
175 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
176 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
177 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
178 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
179 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
180 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
181 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
182 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
183 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
184 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
185 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
186 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
187 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
188 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
189 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
190 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
191 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
192 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
193 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
194 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
195 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
196 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
197 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
198 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
199 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
200 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
201 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
202 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[0] is always 1, optimizing ...
203 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[1] is always 0, optimizing ...
204 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[1] is always 0, optimizing ...
205 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[2] is always 0, optimizing ...
206 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
207 6 ale500 
 
208 4 ale500 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
209 
 
210 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
211 
 
212 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
213 
 
214 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
215 
 
216 
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
217 
 
218 7 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom
219 
 
220 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k
221 
 
222 
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
223 
 
224 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext
225 
 
226 
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display
227 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet
228 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet
229 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
230 
@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
231 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...
232 
 
233 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
234 
 
235 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
236 
 
237 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
238 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
239 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
240 
 
241 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2
242 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o
243 
 
244 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in
245 
 
246 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out
247 
 
248 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we
249 
 
250 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe
251 
 
252 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
253 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
254 7 ale500 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":105:25:105:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
255 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
256 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
257 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
258 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
259 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
260 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
261 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
262 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
263 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
264 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
265 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
266 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
267 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
268 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
269 9 ale500 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 5 to 3 of next_push_state[5:0]
270 4 ale500 
 
271 9 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
272 4 ale500 
 
273 9 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
274 4 ale500 
 
275 9 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
276 4 ale500 
 
277 6 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused
278 
 
279 9 ale500 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bits 15 to 13 of pipe0[15:0]
280 6 ale500 
 
281 9 ale500 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Register bit pipe0[12] is always 0, optimizing ...
282 
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bit 12 of pipe0[12:0]
283 6 ale500 
 
284 9 ale500 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:12:198:17|Input clk_in is unused
285 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":159:18:159:21|Input b_in is unused
286 4 ale500 
@END
287 9 ale500 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
288 
# Mon Jan  6 06:54:13 2014
289 4 ale500 
 
290 
###########################################################]
291 
Premap Report
292 
 
293 
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
294 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
295 
Product Version G-2012.09L-SP1
296 
 
297 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
298 
 
299 
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt
300 
Printing clock  summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file
301 
@N: MF248 |Running in 64-bit mode.
302 
@N: MF666 |Clock conversion enabled
303 
 
304 9 ale500 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
305 4 ale500 
 
306 
 
307 9 ale500 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
308 4 ale500 
 
309 
 
310 9 ale500 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
311 4 ale500 
 
312 
 
313 9 ale500 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)
314 4 ale500 
 
315 
 
316 
 
317 
Clock Summary
318 
**************
319 
 
320 
Start                             Requested     Requested     Clock                              Clock
321 
Clock                             Frequency     Period        Type                               Group
322 
--------------------------------------------------------------------------------------------------------------------
323 
CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0
324 
CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
325 
====================================================================================================================
326 
 
327 7 ale500 
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
328 4 ale500 
 
329 
syn_allowed_resources : blockrams=26  set on top level netlist CC3_top
330 
Finished Pre Mapping Phase.Pre-mapping successful!
331 
 
332 9 ale500 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)
333 4 ale500 
 
334 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
335 9 ale500 
# Mon Jan  6 06:54:14 2014
336 4 ale500 
 
337 
###########################################################]
338 
Map & Optimize Report
339 
 
340 
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
341 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
342 
Product Version G-2012.09L-SP1
343 
 
344 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
345 
 
346 
@N: MF248 |Running in 64-bit mode.
347 
@N: MF666 |Clock conversion enabled
348 
 
349 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
350 
 
351 
 
352 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
353 
 
354 
 
355 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
356 
 
357 
 
358 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)
359 
 
360 
 
361 
 
362 7 ale500 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
363 4 ale500 
 
364 
 
365 
Available hyper_sources - for debug and ip models
366 
        None Found
367 
 
368 
 
369 7 ale500 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
370 4 ale500 
 
371 9 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
372 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
373 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
374 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
375 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
376 7 ale500 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
377 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
378 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
379 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
380 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
381 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
382 9 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
383 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
384 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
385 4 ale500 
 
386 9 ale500 
Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 161MB)
387 4 ale500 
 
388 9 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
389 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
390 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
391 4 ale500 
 
392 9 ale500 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 163MB)
393 4 ale500 
 
394 
 
395 
 
396 9 ale500 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 165MB)
397 4 ale500 
 
398 9 ale500 
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":883:11:883:29|Pipelining module un75
399 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register k_pp_regs[7:0] pushed in.
400 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":143:35:143:85|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
401 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":100:35:100:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_2[8:0] from cpu0.alu.alu8.a8.un26_q_out[8:0]
402 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":140:35:140:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
403 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":99:35:99:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_1_0[8:0] from cpu0.alu.alu8.a8.un17_q_out[8:0]
404 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":254:2:254:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.ea.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]
405 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
406 4 ale500 
 
407 9 ale500 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
408 4 ale500 
 
409 
 
410 9 ale500 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
411 4 ale500 
 
412 
 
413 9 ale500 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 151MB peak: 165MB)
414 4 ale500 
 
415 
 
416 9 ale500 
Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 165MB)
417 4 ale500 
 
418 
 
419 9 ale500 
Finished technology mapping (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 212MB peak: 229MB)
420 4 ale500 
 
421 
Pass             CPU time               Worst Slack             Luts / Registers
422 
------------------------------------------------------------
423 
Pass             CPU time               Worst Slack             Luts / Registers
424 
------------------------------------------------------------
425 
------------------------------------------------------------
426 
 
427 
 
428 9 ale500 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 229MB)
429 4 ale500 
 
430 
@N: FX164 |The option to pack flops in the IOB has not been specified
431 
 
432 9 ale500 
Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 169MB peak: 229MB)
433 4 ale500 
 
434 
 
435 
 
436 
#### START OF CLOCK OPTIMIZATION REPORT #####[
437 
 
438 9 ale500 
1 non-gated/non-generated clock tree(s) driving 455 clock pin(s) of sequential element(s)
439 4 ale500 
 
440 9 ale500 
342 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
441 4 ale500 
 
442 
=========================== Non-Gated/Non-Generated Clocks ============================
443 
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
444 
---------------------------------------------------------------------------------------
445 9 ale500 
@K:CKID0001       clk40_i             port                   455        cpu_clk
446 4 ale500 
=======================================================================================
447 
===== Gated/Generated Clocks =====
448 
************** None **************
449 
----------------------------------
450 
==================================
451 
 
452 
 
453 
##### END OF CLOCK OPTIMIZATION REPORT ######]
454 
 
455 
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
456 
 
457 9 ale500 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 172MB peak: 229MB)
458 4 ale500 
 
459 
Writing EDIF Netlist and constraint files
460 
G-2012.09L-SP1
461 
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
462 
 
463 9 ale500 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 176MB peak: 229MB)
464 4 ale500 
 
465 
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
466 
 
467 
 
468 
 
469 
##### START OF TIMING REPORT #####[
470 9 ale500 
# Timing Report written on Mon Jan  6 06:54:29 2014
471 4 ale500 
#
472 
 
473 
 
474 
Top view:               CC3_top
475 
Requested Frequency:    1.0 MHz
476 
Wire load mode:         top
477 
Paths requested:        5
478 
Constraint File(s):
479 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
480 
 
481 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
482 
 
483 
 
484 
 
485 
Performance Summary
486 
*******************
487 
 
488 
 
489 9 ale500 
Worst slack in design: 978.474
490 4 ale500 
 
491 
                    Requested     Estimated     Requested     Estimated                 Clock        Clock
492 
Starting Clock      Frequency     Frequency     Period        Period        Slack       Type         Group
493 
------------------------------------------------------------------------------------------------------------------------
494 9 ale500 
CC3_top|clk40_i     1.0 MHz       46.5 MHz      1000.000      21.526        978.474     inferred     Inferred_clkgroup_0
495 4 ale500 
========================================================================================================================
496 
 
497 
 
498 
 
499 
 
500 
 
501 
Clock Relationships
502 
*******************
503 
 
504 
Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
505 
--------------------------------------------------------------------------------------------------------------------------
506 
Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
507 
--------------------------------------------------------------------------------------------------------------------------
508 9 ale500 
CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.474  |  No paths    -      |  No paths    -      |  No paths    -
509 4 ale500 
==========================================================================================================================
510 
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
511 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
512 
 
513 
 
514 
 
515 
Interface Information
516 
*********************
517 
 
518 
No IO constraint found
519 
 
520 
 
521 
 
522 
====================================
523 
Detailed Report for Clock: CC3_top|clk40_i
524 
====================================
525 
 
526 
 
527 
 
528 
Starting Points with Worst Slack
529 
********************************
530 
 
531 9 ale500 
                      Starting                                             Arrival
532 
Instance              Reference           Type        Pin     Net          Time        Slack
533 
                      Clock
534 
----------------------------------------------------------------------------------------------
535 
cpu0.alu.rb_in[0]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[0]     1.302       978.474
536 
cpu0.alu.rb_in[1]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[1]     1.302       978.617
537 
cpu0.alu.rb_in[2]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[2]     1.292       978.627
538 
cpu0.alu.rb_in[3]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[3]     1.296       978.766
539 
cpu0.alu.rb_in[4]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[4]     1.292       978.770
540 
cpu0.alu.ra_in[0]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[0]     1.305       979.039
541 
cpu0.alu.ra_in[1]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[1]     1.309       979.178
542 
cpu0.alu.ra_in[2]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[2]     1.309       979.178
543 
cpu0.alu.ra_in[3]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[3]     1.305       979.324
544 
cpu0.alu.ra_in[4]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[4]     1.292       979.338
545 
==============================================================================================
546 4 ale500 
 
547 
 
548 
Ending Points with Worst Slack
549 
******************************
550 
 
551 6 ale500 
                     Starting                                             Required
552 
Instance             Reference           Type        Pin     Net          Time         Slack
553 
                     Clock
554 
----------------------------------------------------------------------------------------------
555 9 ale500 
cpu0.regs.SS[14]     CC3_top|clk40_i     FD1P3AX     D       SS_s[14]     999.894      978.474
556 
cpu0.regs.SS[15]     CC3_top|clk40_i     FD1P3AX     D       SS_s[15]     999.894      978.474
557 
cpu0.regs.SU[14]     CC3_top|clk40_i     FD1P3AX     D       SU_s[14]     999.894      978.474
558 
cpu0.regs.SU[15]     CC3_top|clk40_i     FD1P3AX     D       SU_s[15]     999.894      978.474
559 
cpu0.regs.SS[12]     CC3_top|clk40_i     FD1P3AX     D       SS_s[12]     999.894      978.617
560 
cpu0.regs.SS[13]     CC3_top|clk40_i     FD1P3AX     D       SS_s[13]     999.894      978.617
561 
cpu0.regs.SU[12]     CC3_top|clk40_i     FD1P3AX     D       SU_s[12]     999.894      978.617
562 
cpu0.regs.SU[13]     CC3_top|clk40_i     FD1P3AX     D       SU_s[13]     999.894      978.617
563 
cpu0.regs.SS[10]     CC3_top|clk40_i     FD1P3AX     D       SS_s[10]     999.894      978.760
564 
cpu0.regs.SS[11]     CC3_top|clk40_i     FD1P3AX     D       SS_s[11]     999.894      978.760
565 6 ale500 
==============================================================================================
566 4 ale500 
 
567 
 
568 
 
569 
Worst Path Information
570 
***********************
571 
 
572 
 
573 
Path information for path number 1:
574 
      Requested Period:                      1000.000
575 6 ale500 
    - Setup time:                            0.106
576 4 ale500 
    + Clock delay at ending point:           0.000 (ideal)
577 6 ale500 
    = Required time:                         999.894
578 4 ale500 
 
579 9 ale500 
    - Propagation time:                      21.420
580 4 ale500 
    - Clock delay at starting point:         0.000 (ideal)
581 9 ale500 
    = Slack (critical) :                     978.474
582 4 ale500 
 
583 9 ale500 
    Number of logic level(s):                23
584 
    Starting point:                          cpu0.alu.rb_in[0] / Q
585 
    Ending point:                            cpu0.regs.SS[15] / D
586 4 ale500 
    The start point is clocked by            CC3_top|clk40_i [rising] on pin CK
587 
    The end   point is clocked by            CC3_top|clk40_i [rising] on pin CK
588 
 
589 9 ale500 
Instance / Net                                          Pin      Pin               Arrival     No. of
590 
Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
591 
---------------------------------------------------------------------------------------------------------
592 
cpu0.alu.rb_in[0]                          FD1P3AX      Q        Out     1.302     1.302       -
593 
rb_in[0]                                   Net          -        -       -         -           26
594 
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO     INV          A        In      0.000     1.302       -
595 
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO     INV          Z        Out     0.568     1.870       -
596 
rb_in_i[0]                                 Net          -        -       -         -           1
597 
cpu0.alu.alu8.a8.un8_q_out_cry_0_0         CCU2D        A1       In      0.000     1.870       -
598 
cpu0.alu.alu8.a8.un8_q_out_cry_0_0         CCU2D        COUT     Out     1.544     3.415       -
599 
un8_q_out_cry_0                            Net          -        -       -         -           1
600 
cpu0.alu.alu8.a8.un8_q_out_cry_1_0         CCU2D        CIN      In      0.000     3.415       -
601 
cpu0.alu.alu8.a8.un8_q_out_cry_1_0         CCU2D        S1       Out     1.549     4.964       -
602 
un8_q_out[2]                               Net          -        -       -         -           1
603 
cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0     ORCALUT4     A        In      0.000     4.964       -
604 
cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0     ORCALUT4     Z        Out     1.017     5.981       -
605 
q_out_2_cry_1_0_RNO_0                      Net          -        -       -         -           1
606 
cpu0.alu.alu8.a8.q_out_2_cry_1_0           CCU2D        C1       In      0.000     5.981       -
607 
cpu0.alu.alu8.a8.q_out_2_cry_1_0           CCU2D        COUT     Out     1.544     7.525       -
608 
q_out_2_cry_2                              Net          -        -       -         -           1
609 
cpu0.alu.alu8.a8.q_out_2_cry_3_0           CCU2D        CIN      In      0.000     7.525       -
610 
cpu0.alu.alu8.a8.q_out_2_cry_3_0           CCU2D        COUT     Out     0.143     7.668       -
611 
q_out_2_cry_4                              Net          -        -       -         -           1
612 
cpu0.alu.alu8.a8.q_out_2_cry_5_0           CCU2D        CIN      In      0.000     7.668       -
613 
cpu0.alu.alu8.a8.q_out_2_cry_5_0           CCU2D        COUT     Out     0.143     7.811       -
614 
q_out_2_cry_6                              Net          -        -       -         -           1
615 
cpu0.alu.alu8.a8.q_out_2_cry_7_0           CCU2D        CIN      In      0.000     7.811       -
616 
cpu0.alu.alu8.a8.q_out_2_cry_7_0           CCU2D        S0       Out     1.549     9.360       -
617 
N_2388                                     Net          -        -       -         -           1
618 
cpu0.alu.alu8.a8.q_out_3[7]                ORCALUT4     A        In      0.000     9.360       -
619 
cpu0.alu.alu8.a8.q_out_3[7]                ORCALUT4     Z        Out     1.089     10.448      -
620 
arith_q[7]                                 Net          -        -       -         -           2
621 
cpu0.alu.alu8.q_out_4_am[7]                ORCALUT4     A        In      0.000     10.448      -
622 
cpu0.alu.alu8.q_out_4_am[7]                ORCALUT4     Z        Out     1.017     11.465      -
623 
q_out_4_am[7]                              Net          -        -       -         -           1
624 
cpu0.alu.alu8.q_out_4[7]                   PFUMX        BLUT     In      0.000     11.465      -
625 
cpu0.alu.alu8.q_out_4[7]                   PFUMX        Z        Out     0.286     11.751      -
626 
N_160                                      Net          -        -       -         -           2
627 
cpu0.alu.alu8.q_out_5_RNIRSTD1[7]          ORCALUT4     A        In      0.000     11.751      -
628 
cpu0.alu.alu8.q_out_5_RNIRSTD1[7]          ORCALUT4     Z        Out     1.089     12.840      -
629 
q8_out[7]                                  Net          -        -       -         -           2
630 
cpu0.alu.q_out[7]                          ORCALUT4     A        In      0.000     12.840      -
631 
cpu0.alu.q_out[7]                          ORCALUT4     Z        Out     0.449     13.289      -
632 
alu_o_result[7]                            Net          -        -       -         -           1
633 
cpu0.alu.alu8.l8.datamux_o_dest[7]         PFUMX        ALUT     In      0.000     13.289      -
634 
cpu0.alu.alu8.l8.datamux_o_dest[7]         PFUMX        Z        Out     0.286     13.575      -
635 
datamux_o_dest[7]                          Net          -        -       -         -           2
636 
cpu0.regs.path_left_data_RNIOEVA1[7]       ORCALUT4     B        In      0.000     13.575      -
637 
cpu0.regs.path_left_data_RNIOEVA1[7]       ORCALUT4     Z        Out     1.273     14.848      -
638 
left_1[7]                                  Net          -        -       -         -           9
639 
cpu0.regs.SS_16_0[7]                       ORCALUT4     B        In      0.000     14.848      -
640 
cpu0.regs.SS_16_0[7]                       ORCALUT4     Z        Out     1.017     15.865      -
641 
N_250                                      Net          -        -       -         -           1
642 
cpu0.regs.SS_16[7]                         ORCALUT4     A        In      0.000     15.865      -
643 
cpu0.regs.SS_16[7]                         ORCALUT4     Z        Out     1.017     16.882      -
644 
SS_16[7]                                   Net          -        -       -         -           1
645 
cpu0.regs.SS_228_m3                        ORCALUT4     B        In      0.000     16.882      -
646 
cpu0.regs.SS_228_m3                        ORCALUT4     Z        Out     1.017     17.898      -
647 
SS_228_i1_mux                              Net          -        -       -         -           1
648 
cpu0.regs.SS_cry_0[6]                      CCU2D        C1       In      0.000     17.898      -
649 
cpu0.regs.SS_cry_0[6]                      CCU2D        COUT     Out     1.544     19.443      -
650 
SS_cry[7]                                  Net          -        -       -         -           1
651 
cpu0.regs.SS_cry_0[8]                      CCU2D        CIN      In      0.000     19.443      -
652 
cpu0.regs.SS_cry_0[8]                      CCU2D        COUT     Out     0.143     19.586      -
653 
SS_cry[9]                                  Net          -        -       -         -           1
654 
cpu0.regs.SS_cry_0[10]                     CCU2D        CIN      In      0.000     19.586      -
655 
cpu0.regs.SS_cry_0[10]                     CCU2D        COUT     Out     0.143     19.729      -
656 
SS_cry[11]                                 Net          -        -       -         -           1
657 
cpu0.regs.SS_cry_0[12]                     CCU2D        CIN      In      0.000     19.729      -
658 
cpu0.regs.SS_cry_0[12]                     CCU2D        COUT     Out     0.143     19.871      -
659 
SS_cry[13]                                 Net          -        -       -         -           1
660 
cpu0.regs.SS_cry_0[14]                     CCU2D        CIN      In      0.000     19.871      -
661 
cpu0.regs.SS_cry_0[14]                     CCU2D        S1       Out     1.549     21.420      -
662 
SS_s[15]                                   Net          -        -       -         -           1
663 
cpu0.regs.SS[15]                           FD1P3AX      D        In      0.000     21.420      -
664 
=========================================================================================================
665 4 ale500 
 
666 
 
667 
 
668 
##### END OF TIMING REPORT #####]
669 
 
670 
---------------------------------------
671 
Resource Usage Report
672 
Part: lcmxo2_7000he-4
673 
 
674 9 ale500 
Register bits: 439 of 6864 (6%)
675 4 ale500 
PIC Latch:       0
676 
I/O cells:       49
677 7 ale500 
Block Rams : 10 of 26 (38%)
678 4 ale500 
 
679 
 
680 
Details:
681 7 ale500 
CCU2D:          196
682 
DP8KC:          10
683 9 ale500 
FD1P3AX:        393
684 4 ale500 
FD1P3DX:        6
685 7 ale500 
FD1S3AX:        28
686 
FD1S3IX:        2
687 4 ale500 
GSR:            1
688 
IB:             1
689 9 ale500 
INV:            19
690 
L6MUX21:        26
691 7 ale500 
OB:             40
692 
OBZ:            8
693 
OFS1P3DX:       9
694 
OFS1P3IX:       1
695 9 ale500 
ORCALUT4:       2024
696 
PFUMX:          222
697 4 ale500 
PUR:            1
698 9 ale500 
VHI:            13
699 
VLO:            20
700 
false:          1
701 
true:           8
702 4 ale500 
Mapper successful!
703 
 
704 9 ale500 
At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)
705 4 ale500 
 
706 9 ale500 
Process took 0h:00m:14s realtime, 0h:00m:14s cputime
707 
# Mon Jan  6 06:54:29 2014
708 4 ale500 
 
709 
###########################################################]
710 
 
711 
 
712 
Synthesis exit by 0.
713 
 
714 
edif2ngd  -l "MachXO2" -d LCMXO2-7000HE -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi" "P6809_P6809.ngo"
715 
edif2ngd:  version Diamond (64-bit) 2.2.0.101
716 
 
717 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
718 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
719 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
720 
Copyright (c) 2001 Agere Systems   All rights reserved.
721 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
722 
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
723 9 ale500 
  On or above line 299 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
724 4 ale500 
 
725 
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
726 9 ale500 
  On or above line 307 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
727 4 ale500 
 
728 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
729 9 ale500 
  On or above line 1762 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
730 4 ale500 
 
731 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
732 9 ale500 
  On or above line 3985 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
733 4 ale500 
 
734 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
735 9 ale500 
  On or above line 4141 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
736 4 ale500 
 
737 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
738 9 ale500 
  On or above line 5267 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
739 4 ale500 
 
740 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
741 9 ale500 
  On or above line 5492 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
742 4 ale500 
 
743 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
744 9 ale500 
  On or above line 9169 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
745 4 ale500 
 
746 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
747 9 ale500 
  On or above line 10988 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
748 4 ale500 
 
749 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
750 9 ale500 
  On or above line 13438 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
751 4 ale500 
 
752 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
753 9 ale500 
  On or above line 14340 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
754 4 ale500 
 
755 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
756 9 ale500 
  On or above line 15057 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
757 4 ale500 
 
758 6 ale500 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
759 9 ale500 
  On or above line 15354 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
760 6 ale500 
 
761 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
762 9 ale500 
  On or above line 16157 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
763 6 ale500 
 
764 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
765 9 ale500 
  On or above line 16308 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
766 6 ale500 
 
767 7 ale500 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
768 9 ale500 
  On or above line 18673 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
769 7 ale500 
 
770 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
771 9 ale500 
  On or above line 22261 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
772 7 ale500 
 
773 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
774 9 ale500 
  On or above line 32987 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
775 7 ale500 
 
776 9 ale500 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
777 
  On or above line 35566 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
778 
 
779 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
780 
  On or above line 38271 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
781 
 
782 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
783 
  On or above line 38689 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
784 
 
785 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
786 
  On or above line 42846 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
787 
 
788 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
789 
  On or above line 43639 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
790 
 
791 4 ale500 
Writing the design to P6809_P6809.ngo...
792 
 
793 
 
794 
ngdbuild  -a "MachXO2" -d LCMXO2-7000HE  -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data"  -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "P6809_P6809.ngo" "P6809_P6809.ngd"
795 
ngdbuild:  version Diamond (64-bit) 2.2.0.101
796 
 
797 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
798 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
799 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
800 
Copyright (c) 2001 Agere Systems   All rights reserved.
801 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
802 
Reading 'P6809_P6809.ngo' ...
803 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
804 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
805 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
806 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...
807 
 
808 
 
809 
Running DRC...
810 
 
811 9 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_15_0_COUT' has no load
812 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S0_0' has no load
813 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S1_0' has no load
814 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_15_0_COUT' has no load
815 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0_0' has no load
816 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1_0' has no load
817 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_15_0_COUT' has no load
818 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_0_0_S0' has no load
819 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_0_cry_15_0_COUT' has no load
820 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_0_cry_0_0_S0' has no load
821 6 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT' has no load
822 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1' has no load
823 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0' has no load
824 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1' has no load
825 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_COUT' has no load
826 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_S1' has no load
827 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S0' has no load
828 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S1' has no load
829 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_8_0_COUT' has no load
830 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S0' has no load
831 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S1' has no load
832 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_8_0_COUT' has no load
833 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S0' has no load
834 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S1' has no load
835 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_8_0_COUT' has no load
836 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S0' has no load
837 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S1' has no load
838 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT' has no load
839 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1' has no load
840 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0' has no load
841 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1' has no load
842 9 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_7_0_COUT' has no load
843 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_0_0_S0' has no load
844 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_0_0_S1' has no load
845 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_7_0_COUT' has no load
846 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0' has no load
847 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_0_0_S1' has no load
848 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_2_cry_7_0_COUT' has no load
849 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_2_cry_0_0_S0_0' has no load
850 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_0_cry_7_0_COUT' has no load
851 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_0_cry_0_S0_0' has no load
852 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_s_15_0_COUT' has no load
853 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_s_15_0_S1' has no load
854 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_cry_0_0_S0' has no load
855 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_cry_0_0_S1' has no load
856 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_s_15_0_COUT' has no load
857 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_s_15_0_S1' has no load
858 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_cry_0_0_S0' has no load
859 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_cry_0_0_S1' has no load
860 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/k_new_pc_4_s_15_0_COUT' has no load
861 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/k_new_pc_4_s_15_0_S1' has no load
862 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/k_new_pc_4_cry_0_0_S0' has no load
863 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/k_new_pc_4_cry_0_0_S1' has no load
864 6 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_COUT' has no load
865 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_S1' has no load
866 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S0' has no load
867 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S1' has no load
868 9 ale500 
WARNING - ngdbuild: logical net 'cpu0/regs/SU_cry_0_COUT[14]' has no load
869 
WARNING - ngdbuild: logical net 'cpu0/regs/SU_lcry_0_S0' has no load
870 
WARNING - ngdbuild: logical net 'cpu0/regs/SU_lcry_0_S1' has no load
871 
WARNING - ngdbuild: logical net 'cpu0/regs/SS_cry_0_COUT[14]' has no load
872 
WARNING - ngdbuild: logical net 'cpu0/regs/SS_lcry_0_S0' has no load
873 
WARNING - ngdbuild: logical net 'cpu0/regs/SS_lcry_0_S1' has no load
874 
WARNING - ngdbuild: logical net 'cpu0/regs/right_s_15_0_COUT' has no load
875 
WARNING - ngdbuild: logical net 'cpu0/regs/right_s_15_0_S1' has no load
876 
WARNING - ngdbuild: logical net 'cpu0/regs/right_cry_0_0_S0' has no load
877 7 ale500 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_COUT' has no load
878 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_S1' has no load
879 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S0' has no load
880 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S1' has no load
881 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_7_0_COUT' has no load
882 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S0' has no load
883 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S1' has no load
884 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_10_0_COUT' has no load
885 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S0' has no load
886 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S1' has no load
887 
WARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_COUT[5]' has no load
888 
WARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_S0[0]' has no load
889 
WARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_COUT[5]' has no load
890 
WARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_S0[0]' has no load
891 
WARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_COUT[9]' has no load
892 
WARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_S0[0]' has no load
893 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_COUT[5]' has no load
894 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_S1[5]' has no load
895 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_cry_0_S0[0]' has no load
896 
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_COUT[9]' has no load
897 
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_S0[0]' has no load
898 4 ale500 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no load
899 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no load
900 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no load
901 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no load
902 9 ale500 
WARNING - ngdbuild: DRC complete with 91 warnings
903 4 ale500 
 
904 
Design Results:
905 9 ale500 
   3019 blocks expanded
906 4 ale500 
complete the first expansion
907 
Writing 'P6809_P6809.ngd' ...
908 
 
909 
map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial   "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0
910 
map:  version Diamond (64-bit) 2.2.0.101
911 
 
912 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
913 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
914 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
915 
Copyright (c) 2001 Agere Systems   All rights reserved.
916 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
917 
   Process the file: P6809_P6809.ngd
918 
   Picdevice="LCMXO2-7000HE"
919 
 
920 
   Pictype="TQFP144"
921 
 
922 
   Picspeed=4
923 
 
924 
   Remove unused logic
925 
 
926 
   Do not produce over sized NCDs.
927 
 
928 
Part used: LCMXO2-7000HETQFP144, Performance used: 4.
929 
Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
930 
Package Status:                     Final          Version 1.36
931 
 
932 
Running general design DRC...
933 
Removing unused logic...
934 
Optimizing...
935 9 ale500 
5 CCU2 constant inputs absorbed.
936 7 ale500 
WARNING - map: Using local reset signal 'reset_o_c' to infer global GSR net.
937 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
938 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
939 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
940 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
941 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
942 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
943 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
944 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
945 4 ale500 
WARNING - map: The reset of EBR 'bios/bios2k_0_1_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
946 
WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
947 
 
948 
 
949 
 
950 
Design Summary:
951 9 ale500 
   Number of registers:    439
952 
      PFU registers:    429
953 7 ale500 
      PIO registers:    10
954 9 ale500 
   Number of SLICEs:          1218 out of  3432 (35%)
955 4 ale500 
      SLICEs(logic/ROM):       858 out of   858 (100%)
956 9 ale500 
      SLICEs(logic/ROM/RAM):   360 out of  2574 (14%)
957 4 ale500 
          As RAM:            0 out of  2574 (0%)
958 9 ale500 
          As Logic/ROM:    360 out of  2574 (14%)
959 
   Number of logic LUT4s:     2043
960 4 ale500 
   Number of distributed RAM:   0 (0 LUT4s)
961 7 ale500 
   Number of ripple logic:    196 (392 LUT4s)
962 4 ale500 
   Number of shift registers:   0
963 9 ale500 
   Total number of LUT4s:     2435
964 4 ale500 
   Number of PIO sites used: 49 + 4(JTAG) out of 115 (46%)
965 7 ale500 
   Number of block RAMs:  10 out of 26 (38%)
966 4 ale500 
   Number of GSRs:  1 out of 1 (100%)
967 
   EFB used :       No
968 
   JTAG used :      No
969 
   Readback used :  No
970 
   Oscillator used :  No
971 
   Startup used :   No
972 
   POR :            On
973 
   Bandgap :        On
974 
   Number of Power Controller:  0 out of 1 (0%)
975 
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
976 
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
977 
   Number of DCCA:  0 out of 8 (0%)
978 
   Number of DCMA:  0 out of 2 (0%)
979 
   Number of PLLs:  0 out of 2 (0%)
980 
   Number of DQSDLLs:  0 out of 2 (0%)
981 
   Number of CLKDIVC:  0 out of 4 (0%)
982 
   Number of ECLKSYNCA:  0 out of 4 (0%)
983 
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
984 
   Notes:-
985 
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
986 
      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
987 
   Number of clocks:  1
988 9 ale500 
     Net cpu_clkgen: 290 loads, 290 rising, 0 falling (Driver: PIO clk40_i )
989 
   Number of Clock Enables:  36
990 
     Net cpu_clk: 80 loads, 80 LSLICEs
991 
     Net k_cpu_we_RNIKJPB: 8 loads, 0 LSLICEs
992 7 ale500 
     Net textctrl/un1_CPU_OE_EN_0_a2: 8 loads, 0 LSLICEs
993 
     Net textctrl/line_cnte: 2 loads, 2 LSLICEs
994 9 ale500 
     Net textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEs
995 
     Net textctrl/N_103_i: 4 loads, 4 LSLICEs
996 7 ale500 
     Net textctrl/y_cnte: 4 loads, 4 LSLICEs
997 
     Net textctrl/x_cnte: 4 loads, 4 LSLICEs
998 
     Net textctrl/N_4: 6 loads, 6 LSLICEs
999 
     Net textctrl/vsync_cnt_0_sqmuxa_4: 4 loads, 4 LSLICEs
1000 
     Net un1_bios_en_0_a2: 4 loads, 0 LSLICEs
1001 9 ale500 
     Net cpu0/k_mul_cnt_RNI6QASC: 3 loads, 3 LSLICEs
1002 6 ale500 
     Net cpu0/k_ealo_cnv_0[0]: 16 loads, 16 LSLICEs
1003 9 ale500 
     Net cpu0/k_cpu_we_3_RNI4P5E: 8 loads, 8 LSLICEs
1004 
     Net cpu0/k_memhi_0_sqmuxa_RNIGVP52: 4 loads, 4 LSLICEs
1005 
     Net cpu0/mode53_0_RNIULGBO: 3 loads, 3 LSLICEs
1006 
     Net cpu0/k_eahi_0_sqmuxa_2_RNI9C57A: 4 loads, 4 LSLICEs
1007 
     Net cpu0/un1_state_82_1_RNI3MDV1: 4 loads, 4 LSLICEs
1008 
     Net cpu0/un1_state_100_i_o4_RNI60VG1: 4 loads, 4 LSLICEs
1009 
     Net cpu0/k_pp_regs60_RNIHUUP8: 2 loads, 2 LSLICEs
1010 
     Net cpu0/state_cnst_i_a15_1_0_RNI7NDU[5]: 4 loads, 4 LSLICEs
1011 
     Net cpu0/k_new_pc29_0_o2_0_RNIRRPH4: 4 loads, 4 LSLICEs
1012 
     Net cpu0/k_new_pc29_0_o2_0_RNI939S3: 4 loads, 4 LSLICEs
1013 
     Net cpu0/un1_state_50_1_i_o2_RNI0FLID: 4 loads, 4 LSLICEs
1014 
     Net cpu0/un1_state_21_RNIMEOJ: 4 loads, 4 LSLICEs
1015 
     Net cpu0/regs/cff_1_sqmuxa_2_RNI9H8F: 7 loads, 7 LSLICEs
1016 5 ale500 
     Net cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEs
1017 9 ale500 
     Net cpu0/regs/PC_1_sqmuxa_2_RNIDL992: 16 loads, 16 LSLICEs
1018 
     Net cpu0/regs/IY_1_sqmuxa_2_1_0_RNISJTR1: 8 loads, 8 LSLICEs
1019 
     Net cpu0/regs/IX_0_sqmuxa_1_1_RNIVGKH3: 8 loads, 8 LSLICEs
1020 
     Net cpu0/regs/DP_1_sqmuxa_1_1_0_RNIFF9C1: 5 loads, 5 LSLICEs
1021 
     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIIOBV: 4 loads, 4 LSLICEs
1022 
     Net cpu0/regs/un1_right_reg_4_RNIM2L32: 4 loads, 4 LSLICEs
1023 
     Net cpu0/un1_k_opcode_3_3_RNIC8F8I: 14 loads, 14 LSLICEs
1024 
     Net cpu0/state57_RNI9L0F7[0]: 2 loads, 2 LSLICEs
1025 
     Net cpu0/un1_state_73_RNI7H5S5: 2 loads, 2 LSLICEs
1026 7 ale500 
   Number of local set/reset loads for net reset_o_c merged into GSR:  6
1027 9 ale500 
   Number of LSRs:  1
1028 7 ale500 
     Net textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEs
1029 4 ale500 
   Number of nets driven by tri-state buffers:  0
1030 
   Top 10 highest fanout non-clock nets:
1031 9 ale500 
     Net cpu_clk: 101 loads
1032 
     Net cpu0/alu/rop_in[1]: 100 loads
1033 
     Net state_o_c[1]: 84 loads
1034 
     Net state_o_c[5]: 77 loads
1035 
     Net cpu0/use_s_1: 75 loads
1036 
     Net state_o_c[2]: 75 loads
1037 
     Net state_o_c[4]: 74 loads
1038 
     Net cpu0/alu/rop_in[0]: 71 loads
1039 
     Net state_o_c[3]: 68 loads
1040 
     Net cpu0/k_opcode[3]: 66 loads
1041 4 ale500 
 
1042 7 ale500 
   Number of warnings:  11
1043 4 ale500 
   Number of errors:    0
1044 
 
1045 
 
1046 6 ale500 
Total CPU Time: 0 secs
1047 4 ale500 
Total REAL Time: 0 secs
1048 7 ale500 
Peak Memory Usage: 195 MB
1049 4 ale500 
 
1050 
Dumping design to file P6809_P6809_map.ncd.
1051 
 
1052 
trce -f "P6809_P6809.mt" -o "P6809_P6809.tw1" "P6809_P6809_map.ncd" "P6809_P6809.prf"
1053 
trce:  version Diamond (64-bit) 2.2.0.101
1054 
 
1055 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1056 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1057 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1058 
Copyright (c) 2001 Agere Systems   All rights reserved.
1059 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1060 
 
1061 
Loading design for application trce from file P6809_P6809_map.ncd.
1062 
Design name: CC3_top
1063 
NCD version: 3.2
1064 
Vendor:      LATTICE
1065 
Device:      LCMXO2-7000HE
1066 
Package:     TQFP144
1067 
Performance: 4
1068 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1069 
Package Status:                     Final          Version 1.36
1070 
Performance Hardware Data Status:   Final)         Version 23.4
1071 
Setup and Hold Report
1072 
 
1073 
--------------------------------------------------------------------------------
1074 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
1075 9 ale500 
Mon Jan  6 06:54:33 2014
1076 4 ale500 
 
1077 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1078 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1079 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1080 
Copyright (c) 2001 Agere Systems   All rights reserved.
1081 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1082 
 
1083 
Report Information
1084 
------------------
1085 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
1086 
Design file:     P6809_P6809_map.ncd
1087 
Preference file: P6809_P6809.prf
1088 
Device,speed:    LCMXO2-7000HE,4
1089 
Report level:    verbose report, limited to 1 item per preference
1090 
--------------------------------------------------------------------------------
1091 
 
1092 
BLOCK ASYNCPATHS
1093 
BLOCK RESETPATHS
1094 
--------------------------------------------------------------------------------
1095 
 
1096 
 
1097 
 
1098 
Timing summary (Setup):
1099 
---------------
1100 
 
1101 9 ale500 
Timing errors: 672  Score: 491074
1102 
Cumulative negative slack: 491074
1103 4 ale500 
 
1104 9 ale500 
Constraints cover 1007472 paths, 1 nets, and 9180 connections (96.2% coverage)
1105 4 ale500 
 
1106 
--------------------------------------------------------------------------------
1107 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
1108 9 ale500 
Mon Jan  6 06:54:33 2014
1109 4 ale500 
 
1110 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1111 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1112 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1113 
Copyright (c) 2001 Agere Systems   All rights reserved.
1114 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1115 
 
1116 
Report Information
1117 
------------------
1118 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
1119 
Design file:     P6809_P6809_map.ncd
1120 
Preference file: P6809_P6809.prf
1121 
Device,speed:    LCMXO2-7000HE,M
1122 
Report level:    verbose report, limited to 1 item per preference
1123 
--------------------------------------------------------------------------------
1124 
 
1125 
BLOCK ASYNCPATHS
1126 
BLOCK RESETPATHS
1127 
--------------------------------------------------------------------------------
1128 
 
1129 
 
1130 
 
1131 
Timing summary (Hold):
1132 
---------------
1133 
 
1134 
Timing errors: 0  Score: 0
1135 
Cumulative negative slack: 0
1136 
 
1137 9 ale500 
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
1138 4 ale500 
 
1139 
 
1140 
 
1141 
Timing summary (Setup and Hold):
1142 
---------------
1143 
 
1144 9 ale500 
Timing errors: 672 (setup), 0 (hold)
1145 
Score: 491074 (setup), 0 (hold)
1146 
Cumulative negative slack: 491074 (491074+0)
1147 4 ale500 
--------------------------------------------------------------------------------
1148 
 
1149 
--------------------------------------------------------------------------------
1150 
 
1151 
Total time: 0 secs
1152 6 ale500 
 
1153 
mpartrce -p "P6809_P6809.p2t" -f "P6809_P6809.p3t" -tf "P6809_P6809.pt" "P6809_P6809_map.ncd" "P6809_P6809.ncd"
1154 
 
1155 
---- MParTrce Tool ----
1156 
Removing old design directory at request of -rem command line option to this program.
1157 
Running par. Please wait . . .
1158 
 
1159 
Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
1160 9 ale500 
Mon Jan  6 06:54:33 2014
1161 6 ale500 
 
1162 
PAR: Place And Route Diamond (64-bit) 2.2.0.101.
1163 
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
1164 
Preference file: P6809_P6809.prf.
1165 
Placement level-cost: 5-1.
1166 
Routing Iterations: 6
1167 
 
1168 
Loading design for application par from file P6809_P6809_map.ncd.
1169 
Design name: CC3_top
1170 
NCD version: 3.2
1171 
Vendor:      LATTICE
1172 
Device:      LCMXO2-7000HE
1173 
Package:     TQFP144
1174 
Performance: 4
1175 
Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1176 
Package Status:                     Final          Version 1.36
1177 
Performance Hardware Data Status:   Final)         Version 23.4
1178 
License checked out.
1179 
 
1180 
 
1181 
Ignore Preference Error(s):  True
1182 
Device utilization summary:
1183 
 
1184 
   PIO (prelim)   49+4(JTAG)/336     14% used
1185 
                  49+4(JTAG)/115     42% bonded
1186 7 ale500 
   IOLOGIC           10/336           2% used
1187 6 ale500 
 
1188 9 ale500 
   SLICE           1218/3432         35% used
1189 6 ale500 
 
1190 
   GSR                1/1           100% used
1191 7 ale500 
   EBR               10/26           38% used
1192 6 ale500 
 
1193 
 
1194 
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
1195 
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
1196 9 ale500 
Number of Signals: 2816
1197 
Number of Connections: 9541
1198 6 ale500 
 
1199 
Pin Constraint Summary:
1200 
   49 out of 49 pins locked (100% locked).
1201 
 
1202 
The following 1 signal is selected to use the primary clock routing resources:
1203 9 ale500 
    cpu_clkgen (driver: clk40_i, clk load #: 290)
1204 6 ale500 
 
1205 
 
1206 7 ale500 
The following 4 signals are selected to use the secondary clock routing resources:
1207 9 ale500 
    cpu_clk (driver: SLICE_383, clk load #: 0, sr load #: 0, ce load #: 80)
1208 
    cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_689, clk load #: 0, sr load #: 0, ce load #: 16)
1209 
    cpu0/regs/PC_1_sqmuxa_2_RNIDL992 (driver: SLICE_383, clk load #: 0, sr load #: 0, ce load #: 16)
1210 
    cpu0/un1_k_opcode_3_3_RNIC8F8I (driver: cpu0/regs/SLICE_634, clk load #: 0, sr load #: 0, ce load #: 14)
1211 6 ale500 
 
1212 7 ale500 
Signal reset_o_c is selected as Global Set/Reset.
1213 6 ale500 
Starting Placer Phase 0.
1214 9 ale500 
............
1215 
Finished Placer Phase 0.  REAL time: 4 secs
1216 6 ale500 
 
1217 
Starting Placer Phase 1.
1218 
......................
1219 9 ale500 
Placer score = 892427.
1220 
Finished Placer Phase 1.  REAL time: 12 secs
1221 6 ale500 
 
1222 
Starting Placer Phase 2.
1223 
.
1224 9 ale500 
Placer score =  881873
1225 
Finished Placer Phase 2.  REAL time: 13 secs
1226 6 ale500 
 
1227 
 
1228 
------------------ Clock Report ------------------
1229 
 
1230 
Global Clock Resources:
1231 
  CLK_PIN    : 1 out of 8 (12%)
1232 
  PLL        : 0 out of 2 (0%)
1233 
  DCM        : 0 out of 2 (0%)
1234 
  DCC        : 0 out of 8 (0%)
1235 
 
1236 
Quadrants All (TL, TR, BL, BR) - Global Clocks:
1237 9 ale500 
  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 290
1238 
  SECONDARY "cpu_clk" from Q0 on comp "SLICE_383" on site "R2C25B", clk load = 0, ce load = 80, sr load = 0
1239 
  SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_689" on site "R15C40A", clk load = 0, ce load = 16, sr load = 0
1240 
  SECONDARY "cpu0/regs/PC_1_sqmuxa_2_RNIDL992" from F1 on comp "SLICE_383" on site "R2C25B", clk load = 0, ce load = 16, sr load = 0
1241 
  SECONDARY "cpu0/un1_k_opcode_3_3_RNIC8F8I" from F0 on comp "cpu0/regs/SLICE_634" on site "R25C35C", clk load = 0, ce load = 14, sr load = 0
1242 6 ale500 
 
1243 
  PRIMARY  : 1 out of 8 (12%)
1244 7 ale500 
  SECONDARY: 4 out of 8 (50%)
1245 6 ale500 
 
1246 
Edge Clocks:
1247 
  No edge clock selected.
1248 
 
1249 
--------------- End of Clock Report ---------------
1250 
 
1251 
 
1252 
I/O Usage Summary (final):
1253 
   49 out of 336 (14.6%) PIO sites used.
1254 
   49 out of 115 (42.6%) bonded PIO sites used.
1255 
   Number of PIO comps: 49; differential: 0
1256 
   Number of Vref pins used: 0
1257 
 
1258 
I/O Bank Usage Summary:
1259 
+----------+----------------+------------+-----------+
1260 
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
1261 
+----------+----------------+------------+-----------+
1262 
| 0        | 12 / 28 ( 42%) | 2.5V       | -         |
1263 
| 1        | 13 / 29 ( 44%) | 2.5V       | -         |
1264 
| 2        | 23 / 29 ( 79%) | 2.5V       | -         |
1265 
| 3        | 1 / 9 ( 11%)   | 2.5V       | -         |
1266 
| 4        | 0 / 10 (  0%)  | -          | -         |
1267 
| 5        | 0 / 10 (  0%)  | -          | -         |
1268 
+----------+----------------+------------+-----------+
1269 
 
1270 7 ale500 
Total placer CPU time: 13 secs
1271 6 ale500 
 
1272 
Dumping design to file P6809_P6809.dir/5_1.ncd.
1273 
 
1274 9 ale500 
 
1275 6 ale500 
Starting router resource preassignment
1276 
 
1277 9 ale500 
Completed router resource preassignment. Real time: 16 secs
1278 6 ale500 
 
1279 9 ale500 
Start NBR router at Mon Jan 06 06:54:49 CET 2014
1280 6 ale500 
 
1281 
*****************************************************************
1282 
Info: NBR allows conflicts(one node used by more than one signal)
1283 
      in the earlier iterations. In each iteration, it tries to
1284 
      solve the conflicts while keeping the critical connections
1285 
      routed as short as possible. The routing process is said to
1286 
      be completed when no conflicts exist and all connections
1287 
      are routed.
1288 
Note: NBR uses a different method to calculate timing slacks. The
1289 
      worst slack and total negative slack may not be the same as
1290 
      that in TRCE report. You should always run TRCE to verify
1291 
      your design. Thanks.
1292 
*****************************************************************
1293 
 
1294 9 ale500 
Start NBR special constraint process at Mon Jan 06 06:54:49 CET 2014
1295 6 ale500 
 
1296 
Start NBR section for initial routing
1297 
Level 1, iteration 1
1298 9 ale500 
91(0.02%) conflicts; 8164(85.57%) untouched conns; 0 (nbr) score;
1299 
Estimated worst slack/total negative slack: 0.240ns/0.000ns; real time: 18 secs
1300 6 ale500 
Level 2, iteration 1
1301 9 ale500 
14(0.00%) conflicts; 8033(84.19%) untouched conns; 0 (nbr) score;
1302 
Estimated worst slack/total negative slack: 0.378ns/0.000ns; real time: 18 secs
1303 6 ale500 
Level 3, iteration 1
1304 9 ale500 
53(0.01%) conflicts; 6834(71.63%) untouched conns; 0 (nbr) score;
1305 
Estimated worst slack/total negative slack: 1.074ns/0.000ns; real time: 19 secs
1306 6 ale500 
Level 4, iteration 1
1307 9 ale500 
396(0.10%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1308 
Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
1309 6 ale500 
 
1310 7 ale500 
Info: Initial congestion level at 75% usage is 0
1311 9 ale500 
Info: Initial congestion area  at 75% usage is 5 (0.50%)
1312 6 ale500 
 
1313 
Start NBR section for normal routing
1314 
Level 1, iteration 1
1315 9 ale500 
13(0.00%) conflicts; 564(5.91%) untouched conns; 0 (nbr) score;
1316 
Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
1317 7 ale500 
Level 2, iteration 1
1318 9 ale500 
10(0.00%) conflicts; 565(5.92%) untouched conns; 0 (nbr) score;
1319 
Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
1320 7 ale500 
Level 3, iteration 1
1321 9 ale500 
17(0.00%) conflicts; 541(5.67%) untouched conns; 0 (nbr) score;
1322 
Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
1323 6 ale500 
Level 4, iteration 1
1324 9 ale500 
192(0.05%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1325 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 22 secs
1326 6 ale500 
Level 4, iteration 2
1327 9 ale500 
92(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1328 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 22 secs
1329 6 ale500 
Level 4, iteration 3
1330 9 ale500 
36(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1331 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 22 secs
1332 6 ale500 
Level 4, iteration 4
1333 9 ale500 
11(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1334 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 22 secs
1335 6 ale500 
Level 4, iteration 5
1336 9 ale500 
7(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1337 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
1338 6 ale500 
Level 4, iteration 6
1339 9 ale500 
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1340 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
1341 6 ale500 
Level 4, iteration 7
1342 9 ale500 
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1343 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
1344 6 ale500 
Level 4, iteration 8
1345 9 ale500 
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
1346 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
1347 6 ale500 
Level 4, iteration 9
1348 9 ale500 
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
1349 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
1350 6 ale500 
 
1351 
Start NBR section for re-routing
1352 
Level 4, iteration 1
1353 9 ale500 
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
1354 
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
1355 6 ale500 
 
1356 
Start NBR section for post-routing
1357 
 
1358 
End NBR router with 0 unrouted connection
1359 
 
1360 
NBR Summary
1361 
-----------
1362 
  Number of unrouted connections : 0 (0.00%)
1363 9 ale500 
  Number of connections with timing violations : 0 (0.00%)
1364 
  Estimated worst slack : 1.054ns
1365 
  Timing score : 0
1366 6 ale500 
-----------
1367 
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
1368 
 
1369 
 
1370 
 
1371 9 ale500 
Hold time optimization iteration 0:
1372 
All hold time violations have been successfully corrected in speed grade M
1373 6 ale500 
 
1374 
Total CPU time 26 secs
1375 
Total REAL time: 27 secs
1376 
Completely routed.
1377 9 ale500 
End of route.  9541 routed (100.00%); 0 unrouted.
1378 6 ale500 
Checking DRC ...
1379 
No errors found.
1380 
 
1381 
Hold time timing score: 0, hold timing errors: 0
1382 
 
1383 9 ale500 
Timing score: 0
1384 6 ale500 
 
1385 
Dumping design to file P6809_P6809.dir/5_1.ncd.
1386 
 
1387 
 
1388 
PAR_SUMMARY::Run status = completed
1389 
PAR_SUMMARY::Number of unrouted conns = 0
1390 9 ale500 
PAR_SUMMARY::Worst  slack> = 1.054
1391 
PAR_SUMMARY::Timing score> = 0.000
1392 
PAR_SUMMARY::Worst  slack> = 0.180
1393 
PAR_SUMMARY::Timing score> = 0.000
1394 6 ale500 
 
1395 
Total CPU  time to completion: 27 secs
1396 9 ale500 
Total REAL time to completion: 27 secs
1397 6 ale500 
 
1398 
par done!
1399 
 
1400 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1401 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1402 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1403 
Copyright (c) 2001 Agere Systems   All rights reserved.
1404 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1405 
Exiting par with exit code 0
1406 
Exiting mpartrce with exit code 0
1407 
 
1408 
trce -f "P6809_P6809.pt" -o "P6809_P6809.twr" "P6809_P6809.ncd" "P6809_P6809.prf"
1409 
trce:  version Diamond (64-bit) 2.2.0.101
1410 
 
1411 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1412 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1413 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1414 
Copyright (c) 2001 Agere Systems   All rights reserved.
1415 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1416 
 
1417 
Loading design for application trce from file P6809_P6809.ncd.
1418 
Design name: CC3_top
1419 
NCD version: 3.2
1420 
Vendor:      LATTICE
1421 
Device:      LCMXO2-7000HE
1422 
Package:     TQFP144
1423 
Performance: 4
1424 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1425 
Package Status:                     Final          Version 1.36
1426 
Performance Hardware Data Status:   Final)         Version 23.4
1427 
Setup and Hold Report
1428 
 
1429 
--------------------------------------------------------------------------------
1430 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
1431 9 ale500 
Mon Jan  6 06:55:04 2014
1432 6 ale500 
 
1433 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1434 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1435 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1436 
Copyright (c) 2001 Agere Systems   All rights reserved.
1437 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1438 
 
1439 
Report Information
1440 
------------------
1441 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
1442 
Design file:     P6809_P6809.ncd
1443 
Preference file: P6809_P6809.prf
1444 
Device,speed:    LCMXO2-7000HE,4
1445 
Report level:    verbose report, limited to 10 items per preference
1446 
--------------------------------------------------------------------------------
1447 
 
1448 
BLOCK ASYNCPATHS
1449 
BLOCK RESETPATHS
1450 
--------------------------------------------------------------------------------
1451 
 
1452 
 
1453 
 
1454 
Timing summary (Setup):
1455 
---------------
1456 
 
1457 9 ale500 
Timing errors: 0  Score: 0
1458 
Cumulative negative slack: 0
1459 6 ale500 
 
1460 9 ale500 
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
1461 6 ale500 
 
1462 
--------------------------------------------------------------------------------
1463 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
1464 9 ale500 
Mon Jan  6 06:55:04 2014
1465 6 ale500 
 
1466 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1467 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1468 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1469 
Copyright (c) 2001 Agere Systems   All rights reserved.
1470 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1471 
 
1472 
Report Information
1473 
------------------
1474 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
1475 
Design file:     P6809_P6809.ncd
1476 
Preference file: P6809_P6809.prf
1477 
Device,speed:    LCMXO2-7000HE,m
1478 
Report level:    verbose report, limited to 10 items per preference
1479 
--------------------------------------------------------------------------------
1480 
 
1481 
BLOCK ASYNCPATHS
1482 
BLOCK RESETPATHS
1483 
--------------------------------------------------------------------------------
1484 
 
1485 
 
1486 
 
1487 
Timing summary (Hold):
1488 
---------------
1489 
 
1490 
Timing errors: 0  Score: 0
1491 
Cumulative negative slack: 0
1492 
 
1493 9 ale500 
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
1494 6 ale500 
 
1495 
 
1496 
 
1497 
Timing summary (Setup and Hold):
1498 
---------------
1499 
 
1500 9 ale500 
Timing errors: 0 (setup), 0 (hold)
1501 
Score: 0 (setup), 0 (hold)
1502 
Cumulative negative slack: 0 (0+0)
1503 6 ale500 
--------------------------------------------------------------------------------
1504 
 
1505 
--------------------------------------------------------------------------------
1506 
 
1507 
Total time: 0 secs

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