1 |
4 |
ale500 |
<HTML> <HEAD><TITLE></TITLE> <STYLE TYPE="text/css"> <!-- body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; } --> </STYLE> </HEAD> <BODY> <PRE>Setting log file to '/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/hdla_gen_hierarchy.html'.
|
2 |
|
|
INFO: (VHDL-1504) The default vhdl library search path is now "/usr/local/diamond/2.2_x64/cae_library/vhdl_packages/vdbs"
|
3 |
|
|
-- (VERI-1482) Analyzing Verilog file /usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v
|
4 |
|
|
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v
|
5 |
|
|
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v
|
6 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(12,10-12,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
|
7 |
|
|
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v
|
8 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(8,10-8,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
|
9 |
|
|
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
|
10 |
|
|
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v
|
11 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(9,10-9,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
|
12 |
6 |
ale500 |
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(727,24-727,29) WARNING: (VERI-1208) literal value truncated to fit in 4 bits
|
13 |
4 |
ale500 |
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v
|
14 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(4,10-4,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
|
15 |
|
|
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v
|
16 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,8-10,15) INFO: (VERI-1018) compiling module CC3_top
|
17 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,1-109,10) INFO: (VERI-9000) elaborating module 'CC3_top'
|
18 |
6 |
ale500 |
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(10,1-1027,10) INFO: (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
|
19 |
4 |
ale500 |
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v(8,1-171,10) INFO: (VERI-9000) elaborating module 'bios2k_uniq_1'
|
20 |
6 |
ale500 |
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(15,1-55,10) INFO: (VERI-9000) elaborating module 'alu_uniq_1'
|
21 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(7,1-254,10) INFO: (VERI-9000) elaborating module 'regblock_uniq_1'
|
22 |
5 |
ale500 |
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(9,1-128,10) INFO: (VERI-9000) elaborating module 'decode_regs_uniq_1'
|
23 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(131,1-254,10) INFO: (VERI-9000) elaborating module 'decode_op_uniq_1'
|
24 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(259,1-283,10) INFO: (VERI-9000) elaborating module 'decode_ea_uniq_1'
|
25 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(285,1-356,10) INFO: (VERI-9000) elaborating module 'decode_alu_uniq_1'
|
26 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(358,1-394,10) INFO: (VERI-9000) elaborating module 'test_condition_uniq_1'
|
27 |
4 |
ale500 |
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_1'
|
28 |
|
|
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_1'
|
29 |
|
|
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_2'
|
30 |
|
|
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_1'
|
31 |
6 |
ale500 |
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(57,1-322,10) INFO: (VERI-9000) elaborating module 'alu8_uniq_1'
|
32 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(325,1-648,10) INFO: (VERI-9000) elaborating module 'alu16_uniq_1'
|
33 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(650,1-674,10) INFO: (VERI-9000) elaborating module 'mul8x8_uniq_1'
|
34 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(32,19-32,29) WARNING: (VERI-1330) actual bit length 8 differs from formal bit length 16 for port a_in
|
35 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(32,31-32,41) WARNING: (VERI-1330) actual bit length 8 differs from formal bit length 16 for port b_in
|
36 |
|
|
Design load finished with (0) errors, and (3) warnings.
|
37 |
4 |
ale500 |
|
38 |
|
|
</PRE></BODY></HTML>
|