URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
4 |
ale500 |
SCUBA, Version Diamond_2.2_Production (99)
|
2 |
10 |
ale500 |
Thu Feb 6 15:31:10 2014
|
3 |
4 |
ale500 |
|
4 |
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
5 |
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
6 |
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
7 |
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
8 |
|
|
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
|
9 |
|
|
|
10 |
|
|
BEGIN SCUBA Module Synthesis
|
11 |
|
|
|
12 |
10 |
ale500 |
Issued command : /usr/local/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n bios2k -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-7000HE -aaddr_width 11 -widtha 8 -baddr_width 11 -widthb 8 -anum_words 2048 -bnum_words 2048 -cascade -1 -memfile /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/test1.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL -e
|
13 |
|
|
Circuit name : bios2k
|
14 |
4 |
ale500 |
Module type : RAM_DP_TRUE
|
15 |
|
|
Module Version : 7.2
|
16 |
|
|
Ports :
|
17 |
10 |
ale500 |
Inputs : DataInA[7:0], DataInB[7:0], AddressA[10:0], AddressB[10:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
|
18 |
4 |
ale500 |
Outputs : QA[7:0], QB[7:0]
|
19 |
|
|
I/O buffer : not inserted
|
20 |
10 |
ale500 |
Memory file : /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/test1.mem
|
21 |
4 |
ale500 |
EDIF output : suppressed
|
22 |
10 |
ale500 |
Verilog output : bios2k.v
|
23 |
|
|
Verilog template : bios2k_tmpl.v
|
24 |
|
|
Verilog testbench: tb_bios2k_tmpl.v
|
25 |
4 |
ale500 |
Verilog purpose : for synthesis and simulation
|
26 |
|
|
Bus notation : big endian
|
27 |
10 |
ale500 |
Report output : bios2k.srp
|
28 |
4 |
ale500 |
Estimated Resource Usage:
|
29 |
10 |
ale500 |
EBR : 2
|
30 |
4 |
ale500 |
|
31 |
|
|
END SCUBA Module Synthesis
|
32 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.