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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [msg_file.log] - Blame information for rev 4

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Line No. Rev Author Line
1 4 ale500 
SCUBA, Version Diamond_2.2_Production (99)
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Sat Dec 28 21:50:48 2013
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp.   All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
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Copyright (c) 2001 Agere Systems   All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
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BEGIN SCUBA Module Synthesis
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    Issued command   : /usr/local/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n bios2k -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-7000HE -aaddr_width 11 -widtha 8 -baddr_width 11 -widthb 8 -anum_words 2048 -bnum_words 2048 -cascade -1 -memfile test1.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL -e
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    Circuit name     : bios2k
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    Module type      : RAM_DP_TRUE
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    Module Version   : 7.2
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    Ports            :
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    Inputs       : DataInA[7:0], DataInB[7:0], AddressA[10:0], AddressB[10:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
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    Outputs      : QA[7:0], QB[7:0]
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    I/O buffer       : not inserted
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    Memory file      : test1.mem
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    EDIF output      : suppressed
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    Verilog output   : bios2k.v
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    Verilog template : bios2k_tmpl.v
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    Verilog testbench: tb_bios2k_tmpl.v
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    Verilog purpose  : for synthesis and simulation
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    Bus notation     : big endian
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    Report output    : bios2k.srp
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    Estimated Resource Usage:
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            EBR : 2
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END   SCUBA Module Synthesis
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