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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [tb_bios2k_tmpl.v] - Blame information for rev 8

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Line No. Rev Author Line
1 4 ale500 
//Verilog testbench template generated by SCUBA Diamond_2.2_Production (99)
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`timescale 1 ns / 1 ps
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module tb;
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    reg [7:0] DataInA = 8'b0;
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    reg [7:0] DataInB = 8'b0;
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    reg [10:0] AddressA = 11'b0;
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    reg [10:0] AddressB = 11'b0;
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    reg ClockA = 0;
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    reg ClockB = 0;
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    reg ClockEnA = 0;
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    reg ClockEnB = 0;
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    reg WrA = 0;
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    reg WrB = 0;
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    reg ResetA = 0;
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    reg ResetB = 0;
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    wire [7:0] QA;
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    wire [7:0] QB;
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    integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i12 = 0, i13 = 0;
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    GSR GSR_INST (.GSR(1'b1));
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    PUR PUR_INST (.PUR(1'b1));
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    bios2k u1 (.DataInA(DataInA), .DataInB(DataInB), .AddressA(AddressA),
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        .AddressB(AddressB), .ClockA(ClockA), .ClockB(ClockB), .ClockEnA(ClockEnA),
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        .ClockEnB(ClockEnB), .WrA(WrA), .WrB(WrB), .ResetA(ResetA), .ResetB(ResetB),
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        .QA(QA), .QB(QB)
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    );
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    initial
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    begin
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       DataInA <= 0;
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      #100;
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      @(ResetA == 1'b0);
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      for (i1 = 0; i1 < 2051; i1 = i1 + 1) begin
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        @(posedge ClockA);
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        #1  DataInA <= DataInA + 1'b1;
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      end
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    end
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    initial
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    begin
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       DataInB <= 0;
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      #100;
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      @(ResetB == 1'b0);
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      @(WrB == 1'b1);
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      for (i2 = 0; i2 < 2051; i2 = i2 + 1) begin
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        @(posedge ClockB);
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        #1  DataInB <= DataInB + 1'b1;
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      end
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    end
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    initial
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    begin
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       AddressA <= 0;
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      #100;
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      @(ResetA == 1'b0);
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      for (i3 = 0; i3 < 4102; i3 = i3 + 1) begin
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        @(posedge ClockA);
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        #1  AddressA <= AddressA + 1'b1;
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      end
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    end
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    initial
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    begin
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       AddressB <= 0;
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      #100;
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      @(ResetB == 1'b0);
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      @(WrB == 1'b1);
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      for (i4 = 0; i4 < 4102; i4 = i4 + 1) begin
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        @(posedge ClockB);
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        #1  AddressB <= AddressB + 1'b1;
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      end
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    end
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    always
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    #5.00 ClockA <= ~ ClockA;
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    always
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    #5.00 ClockB <= ~ ClockB;
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    initial
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    begin
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       ClockEnA <= 1'b0;
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      #100;
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      @(ResetA == 1'b0);
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       ClockEnA <= 1'b1;
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    end
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    initial
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    begin
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       ClockEnB <= 1'b0;
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      #100;
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      @(ResetB == 1'b0);
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       ClockEnB <= 1'b1;
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    end
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    initial
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    begin
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       WrA <= 1'b0;
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      @(ResetA == 1'b0);
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      for (i9 = 0; i9 < 2051; i9 = i9 + 1) begin
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        @(posedge ClockA);
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        #1  WrA <= 1'b1;
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      end
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       WrA <= 1'b0;
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    end
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    initial
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    begin
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       WrB <= 1'b0;
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      @(ResetB == 1'b0);
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      @(WrA == 1'b1);
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      @(WrA == 1'b0);
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      for (i10 = 0; i10 < 2051; i10 = i10 + 1) begin
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        @(posedge ClockA);
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      end
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      for (i10 = 0; i10 < 2051; i10 = i10 + 1) begin
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        @(posedge ClockB);
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        #1  WrB <= 1'b1;
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      end
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       WrB <= 1'b0;
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    end
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    initial
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    begin
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       ResetA <= 1'b1;
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      #100;
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       ResetA <= 1'b0;
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    end
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    initial
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    begin
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       ResetB <= 1'b1;
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      #100;
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       ResetB <= 1'b0;
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    end
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endmodule

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