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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [vgatext.v] - Blame information for rev 8

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module vgatext(
        input wire CLK,
        input wire RESET,
        output wire HSYNC,
        output wire VSYNC,
        output wire RED,
        output wire GREEN,
        output wire BLUE,
        input wire CPU_CLK,
        input wire [11:0] CPU_ADDR,
        input wire CPU_OE_EN,
        input wire CPU_WR_EN,
        input wire [7:0] CPU_DATA_O,
        output wire [7:0] CPU_DATA_I
        );
`ifdef CLK25
`define LINE_LENGTH    11'd831
`define HSYNC_START    11'd704+11'd64+11'd32
`define HVISIBLE_START 11'd16+11'd64
`define HVISIBLE_END   11'd656+11'd64
`define VVISIBLE_START 11'd10
`define VVISIBLE_END   11'd490
`define FRAME_END      11'd525
`define VSYNC_START    11'd524
`else
/* For 40 MHz clk 800x600 60 Hz */
`define LINE_LENGTH    11'd1055
`define HSYNC_START    11'd840+11'd88
`define HVISIBLE_START 11'd40
`define HVISIBLE_END   11'd840
`define VVISIBLE_START 11'd16
`define VVISIBLE_END   11'd616
`define FRAME_END      11'd627
`define VSYNC_START    11'd624
`endif
reg [10:0] hsync_cnt, vsync_cnt;
reg [3:0] redr, greenr, bluer;
reg hsyncr, vsyncr;
 
assign HSYNC = hsyncr;
assign VSYNC = vsyncr;
reg visible;
 
reg [5:0] blink_cnt;
 
assign RED = visible ? redr[0]:0;
assign GREEN = visible ? greenr[0]:0;
assign BLUE = visible ? bluer[0]:0;
 
always @(posedge CLK)
        begin
                if (RESET == 1'b1)
                        begin
                                hsync_cnt <= 11'h0;
                                vsync_cnt <= 11'h0;
                        end
                else
                        begin
                                if (hsync_cnt == `LINE_LENGTH) // end of line
                                        begin
                                                hsync_cnt <= 0;
                                                hsyncr <= 1'b1;
                                                if (vsync_cnt == `FRAME_END)
                                                        begin
                                                                vsync_cnt <= 11'd0;
                                                                blink_cnt <= blink_cnt + 6'h1; // blinking cursor counter
                                                        end
                                                else
                                                        vsync_cnt <= vsync_cnt + 11'd1;
                                        end
                                else
                                        hsync_cnt <= hsync_cnt + 11'd1;
                        end
                hsyncr <= hsync_cnt >= `HSYNC_START ? 0:1;
                vsyncr <= vsync_cnt >= `VSYNC_START ? 0:1;
                visible <= (hsync_cnt >= `HVISIBLE_START) && (hsync_cnt < `HVISIBLE_END) && (vsync_cnt >= `VVISIBLE_START) && (vsync_cnt < `VVISIBLE_END);
        end
 
wire enable = (hsync_cnt >= `HVISIBLE_START-11'd8) && (hsync_cnt < `HVISIBLE_END) && (vsync_cnt >= `VVISIBLE_START) && (vsync_cnt < `VVISIBLE_END);
reg [6:0] x_cnt, y_cnt, cur_x, cur_y;
reg [3:0] line_cnt;
reg [7:0] chars_data, font_data, tshift, shift;
wire [7:0] font_bus, chars_bus;
 
wire [11:0] yptr;
assign yptr = { y_cnt[5:0], 6'h0 } + { y_cnt[5:0], 5'h0 } + { y_cnt[5:0], 2'h0 } + { 4'h0, x_cnt };
 
fontrom font(.Address({ chars_data, line_cnt }), .OutClock(CLK), .OutClockEn(1'b1), .Reset(1'b0), .Q(font_bus));
 
textmem4k chars(
//.WrAddress(WrAddr), .RdAddress(yptr), .Data(WrData), .WE(WrEn), .RdClock(CLK), .RdClockEn(1'b1), 
//    .Reset(1'b0), .WrClock(WrClk), .WrClockEn(1'b1), .Q(chars_bus));
 
        .DataInA(),
        .AddressA(yptr),
        .ClockA(CLK),
        .ClockEnA(1'b1),
        .WrA(1'b0),
        .ResetA(1'b0),
        .QA(chars_bus),
 
        .DataInB(CPU_DATA_O),
        .AddressB(CPU_ADDR),
        .ClockB(CPU_CLK),
    .ClockEnB(CPU_WR_EN | CPU_OE_EN),
        .WrB(CPU_WR_EN),
        .ResetB(1'b0),
        .QB(CPU_DATA_I)
        );
 
 
always @(posedge CLK) // read memory
        begin
                chars_data <= chars_bus;//[{ y_cnt[4:0], x_cnt }];
                font_data <= font_bus;
        end
 
always @(posedge CLK)
        begin
                if (hsync_cnt == 0)
                        begin
                                x_cnt <= 0;
                                cur_x <= 3; // not needed
                        end
                if (vsync_cnt == 0)
                        begin
                                y_cnt <= 0;
                                line_cnt <= 0;
                                cur_y <= 1;
                        end
                if ((hsync_cnt == `LINE_LENGTH) && (vsync_cnt >= `VVISIBLE_START))
                        begin
                                $display(" ");
                                line_cnt <= line_cnt + 1;
                                if (line_cnt == 4'hf)
                                        y_cnt <= y_cnt + 1;
                        end
                if (enable)
                        begin
 
                                case (hsync_cnt[2:0]) // start of group of 8 consecutive pixels
                                        0: // read new char/color
                                                begin
                                                         shift <= shift << 1;
                                                    x_cnt <= x_cnt + 1;
                                                end
                                        1: // reads font
                                                shift <= shift << 1;
                                        2: // load font data into shift register
                                                begin
                                                        shift <= shift << 1;
                                                        tshift <= font_data;
                                                end
                                        3, 4, 5, 6:
                                                shift <= shift << 1;
                                        7: // uses read shift register
                                                begin
                                                        shift <= tshift;
 
                                                end
                                endcase
                                if ((cur_x == x_cnt) && (cur_y == y_cnt) && (line_cnt > 4'd13) && blink_cnt[5])
                                        begin
                                                redr <= 4'hf;
                                                greenr <= 4'hf;
                                                bluer <= 4'hf;
                                                $write("!");
                                        end
                                else
                                        begin
                                                redr <= shift[7] ? 4'hf:4'h0;
                                                greenr <= shift[7] ? 4'hf:4'h0;
                                                bluer <= shift[7] ? 4'hf:4'h0;
                                                $write("%c", shift[7] ? 33:32);
                                        end
                        end
                else
                        begin
                                redr <= 4'h0;
                                greenr <= 4'h0;
                                bluer <= 4'h0;
                        end
        end
initial
        begin
                redr = 0;
                greenr = 0;
                bluer = 0;
                vsync_cnt = 0;
                hsync_cnt = 0;
        end
endmodule

Line No.	Rev	Author	Line
1	8	ale500
2			`module vgatext(`
3			`input wire CLK,`
4			`input wire RESET,`
5			`output wire HSYNC,`
6			`output wire VSYNC,`
7			`output wire RED,`
8			`output wire GREEN,`
9			`output wire BLUE,`
10			`input wire CPU_CLK,`
11			`input wire [11:0] CPU_ADDR,`
12			`input wire CPU_OE_EN,`
13			`input wire CPU_WR_EN,`
14			`input wire [7:0] CPU_DATA_O,`
15			`output wire [7:0] CPU_DATA_I`
16			`);`
17			`ifdef CLK25
18			`define LINE_LENGTH 11'd831
19			`define HSYNC_START 11'd704+11'd64+11'd32
20			`define HVISIBLE_START 11'd16+11'd64
21			`define HVISIBLE_END 11'd656+11'd64
22			`define VVISIBLE_START 11'd10
23			`define VVISIBLE_END 11'd490
24			`define FRAME_END 11'd525
25			`define VSYNC_START 11'd524
26			`else
27			`/* For 40 MHz clk 800x600 60 Hz */`
28			`define LINE_LENGTH 11'd1055
29			`define HSYNC_START 11'd840+11'd88
30			`define HVISIBLE_START 11'd40
31			`define HVISIBLE_END 11'd840
32			`define VVISIBLE_START 11'd16
33			`define VVISIBLE_END 11'd616
34			`define FRAME_END 11'd627
35			`define VSYNC_START 11'd624
36			`endif
37			`reg [10:0] hsync_cnt, vsync_cnt;`
38			`reg [3:0] redr, greenr, bluer;`
39			`reg hsyncr, vsyncr;`
40
41			`assign HSYNC = hsyncr;`
42			`assign VSYNC = vsyncr;`
43			`reg visible;`
44
45			`reg [5:0] blink_cnt;`
46
47			`assign RED = visible ? redr[0]:0;`
48			`assign GREEN = visible ? greenr[0]:0;`
49			`assign BLUE = visible ? bluer[0]:0;`
50
51			`always @(posedge CLK)`
52			`begin`
53			`if (RESET == 1'b1)`
54			`begin`
55			`hsync_cnt <= 11'h0;`
56			`vsync_cnt <= 11'h0;`
57			`end`
58			`else`
59			`begin`
60			if (hsync_cnt == `LINE_LENGTH) // end of line
61			`begin`
62			`hsync_cnt <= 0;`
63			`hsyncr <= 1'b1;`
64			if (vsync_cnt == `FRAME_END)
65			`begin`
66			`vsync_cnt <= 11'd0;`
67			`blink_cnt <= blink_cnt + 6'h1; // blinking cursor counter`
68			`end`
69			`else`
70			`vsync_cnt <= vsync_cnt + 11'd1;`
71			`end`
72			`else`
73			`hsync_cnt <= hsync_cnt + 11'd1;`
74			`end`
75			hsyncr <= hsync_cnt >= `HSYNC_START ? 0:1;
76			vsyncr <= vsync_cnt >= `VSYNC_START ? 0:1;
77			visible <= (hsync_cnt >= `HVISIBLE_START) && (hsync_cnt < `HVISIBLE_END) && (vsync_cnt >= `VVISIBLE_START) && (vsync_cnt < `VVISIBLE_END);
78			`end`
79
80			wire enable = (hsync_cnt >= `HVISIBLE_START-11'd8) && (hsync_cnt < `HVISIBLE_END) && (vsync_cnt >= `VVISIBLE_START) && (vsync_cnt < `VVISIBLE_END);
81			`reg [6:0] x_cnt, y_cnt, cur_x, cur_y;`
82			`reg [3:0] line_cnt;`
83			`reg [7:0] chars_data, font_data, tshift, shift;`
84			`wire [7:0] font_bus, chars_bus;`
85
86			`wire [11:0] yptr;`
87			`assign yptr = { y_cnt[5:0], 6'h0 } + { y_cnt[5:0], 5'h0 } + { y_cnt[5:0], 2'h0 } + { 4'h0, x_cnt };`
88
89			`fontrom font(.Address({ chars_data, line_cnt }), .OutClock(CLK), .OutClockEn(1'b1), .Reset(1'b0), .Q(font_bus));`
90
91			`textmem4k chars(`
92			`//.WrAddress(WrAddr), .RdAddress(yptr), .Data(WrData), .WE(WrEn), .RdClock(CLK), .RdClockEn(1'b1),`
93			`// .Reset(1'b0), .WrClock(WrClk), .WrClockEn(1'b1), .Q(chars_bus));`
94
95			`.DataInA(),`
96			`.AddressA(yptr),`
97			`.ClockA(CLK),`
98			`.ClockEnA(1'b1),`
99			`.WrA(1'b0),`
100			`.ResetA(1'b0),`
101			`.QA(chars_bus),`
102
103			`.DataInB(CPU_DATA_O),`
104			`.AddressB(CPU_ADDR),`
105			`.ClockB(CPU_CLK),`
106			`.ClockEnB(CPU_WR_EN \| CPU_OE_EN),`
107			`.WrB(CPU_WR_EN),`
108			`.ResetB(1'b0),`
109			`.QB(CPU_DATA_I)`
110			`);`
111
112
113			`always @(posedge CLK) // read memory`
114			`begin`
115			`chars_data <= chars_bus;//[{ y_cnt[4:0], x_cnt }];`
116			`font_data <= font_bus;`
117			`end`
118
119			`always @(posedge CLK)`
120			`begin`
121			`if (hsync_cnt == 0)`
122			`begin`
123			`x_cnt <= 0;`
124			`cur_x <= 3; // not needed`
125			`end`
126			`if (vsync_cnt == 0)`
127			`begin`
128			`y_cnt <= 0;`
129			`line_cnt <= 0;`
130			`cur_y <= 1;`
131			`end`
132			if ((hsync_cnt == `LINE_LENGTH) && (vsync_cnt >= `VVISIBLE_START))
133			`begin`
134			`$display(" ");`
135			`line_cnt <= line_cnt + 1;`
136			`if (line_cnt == 4'hf)`
137			`y_cnt <= y_cnt + 1;`
138			`end`
139			`if (enable)`
140			`begin`
141
142			`case (hsync_cnt[2:0]) // start of group of 8 consecutive pixels`
143			`0: // read new char/color`
144			`begin`
145			`shift <= shift << 1;`
146			`x_cnt <= x_cnt + 1;`
147			`end`
148			`1: // reads font`
149			`shift <= shift << 1;`
150			`2: // load font data into shift register`
151			`begin`
152			`shift <= shift << 1;`
153			`tshift <= font_data;`
154			`end`
155			`3, 4, 5, 6:`
156			`shift <= shift << 1;`
157			`7: // uses read shift register`
158			`begin`
159			`shift <= tshift;`
160
161			`end`
162			`endcase`
163			`if ((cur_x == x_cnt) && (cur_y == y_cnt) && (line_cnt > 4'd13) && blink_cnt[5])`
164			`begin`
165			`redr <= 4'hf;`
166			`greenr <= 4'hf;`
167			`bluer <= 4'hf;`
168			`$write("!");`
169			`end`
170			`else`
171			`begin`
172			`redr <= shift[7] ? 4'hf:4'h0;`
173			`greenr <= shift[7] ? 4'hf:4'h0;`
174			`bluer <= shift[7] ? 4'hf:4'h0;`
175			`$write("%c", shift[7] ? 33:32);`
176			`end`
177			`end`
178			`else`
179			`begin`
180			`redr <= 4'h0;`
181			`greenr <= 4'h0;`
182			`bluer <= 4'h0;`
183			`end`
184			`end`
185			`initial`
186			`begin`
187			`redr = 0;`
188			`greenr = 0;`
189			`bluer = 0;`
190			`vsync_cnt = 0;`
191			`hsync_cnt = 0;`
192			`end`
193			`endmodule`

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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [vgatext.v] - Blame information for rev 8