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riedelx |
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-- 68HC05 microcontroller implementation
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-- Ulrich Riedel
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-- v1.0 2006.01.21 first version
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-----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity fadd is -- full adder stage, interface
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port(a : in std_logic;
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b : in std_logic;
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cin : in std_logic;
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s : out std_logic;
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cout : out std_logic);
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end entity fadd;
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architecture behavior of fadd is -- full adder stage, body
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begin -- circuits of fadd
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s <= a xor b xor cin after 1 ns;
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cout <= (a and b) or (a and cin) or (b and cin) after 1 ns;
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end architecture behavior; -- fadd
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-------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity add8 is -- simple 8 bit ripple carry adder
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port(a : in std_logic_vector(7 downto 0);
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b : in std_logic_vector(7 downto 0);
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cin : in std_logic;
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sum : out std_logic_vector(7 downto 0);
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cout : out std_logic);
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end entity add8;
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architecture behavior of add8 is
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signal c : std_logic_vector(0 to 6); -- internal carry signals
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component fadd -- duplicates entity port
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port(a : in std_logic;
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b : in std_logic;
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cin : in std_logic;
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s : out std_logic;
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cout : out std_logic);
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end component fadd ;
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begin
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a0: fadd port map(a(0), b(0), cin, sum(0), c(0));
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stage: for I in 1 to 6 generate
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as: fadd port map(a(I), b(I), c(I-1) , sum(I), c(I));
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end generate stage;
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a31: fadd port map(a(7), b(7), c(6) , sum(7), cout);
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end architecture behavior; -- add8
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-------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity add8c is -- one stage of carry save adder for multiplier
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port(
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b : in std_logic; -- a multiplier bit
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a : in std_logic_vector(7 downto 0); -- multiplicand
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sum_in : in std_logic_vector(7 downto 0); -- sums from previous stage
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cin : in std_logic_vector(7 downto 0); -- carrys from previous stage
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sum_out : out std_logic_vector(7 downto 0); -- sums to next stage
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cout : out std_logic_vector(7 downto 0)); -- carrys to next stage
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end add8c;
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architecture behavior of add8c is
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signal zero : std_logic_vector(7 downto 0) := x"00";
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signal aa : std_logic_vector(7 downto 0) := x"00";
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component fadd
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port(a : in std_logic;
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b : in std_logic;
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cin : in std_logic;
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s : out std_logic;
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cout : out std_logic);
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end component fadd;
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begin
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aa <= a when b = '1' else zero after 1 ns;
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stage: for I in 0 to 7 generate
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sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
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end generate stage;
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end architecture behavior; -- add8csa
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-------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity mul8 is -- 8 x 8 = 16 bit unsigned product multiplier
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port(a : in std_logic_vector(7 downto 0); -- multiplicand
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b : in std_logic_vector(7 downto 0); -- multiplier
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prod : out std_logic_vector(15 downto 0)); -- product
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end mul8;
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architecture behavior of mul8 is
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signal zero : std_logic_vector(7 downto 0) := x"00";
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signal nc1 : std_logic;
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type arr8 is array(0 to 7) of std_logic_vector(7 downto 0);
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signal s : arr8; -- partial sums
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signal c : arr8; -- partial carries
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signal ss : arr8; -- shifted sums
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component add8c is
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port(b : in std_logic;
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a : in std_logic_vector(7 downto 0);
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sum_in : in std_logic_vector(7 downto 0);
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cin : in std_logic_vector(7 downto 0);
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sum_out : out std_logic_vector(7 downto 0);
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cout : out std_logic_vector(7 downto 0));
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end component add8c;
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component add8
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port(a : in std_logic_vector(7 downto 0);
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b : in std_logic_vector(7 downto 0);
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cin : in std_logic;
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sum : out std_logic_vector(7 downto 0);
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cout : out std_logic);
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end component add8;
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begin
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st0: add8c port map(b(0), a, zero , zero, s(0), c(0)); -- CSA stage
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ss(0) <= '0' & s(0)(7 downto 1) after 1 ns;
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prod(0) <= s(0)(0) after 1 ns;
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stage: for I in 1 to 7 generate
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st: add8c port map(b(I), a, ss(I-1) , c(I-1), s(I), c(I)); -- CSA stage
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ss(I) <= '0' & s(I)(7 downto 1) after 1 ns;
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prod(I) <= s(I)(0) after 1 ns;
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end generate stage;
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add: add8 port map(ss(7), c(7), '0' , prod(15 downto 8), nc1); -- adder
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end architecture behavior; -- mul8
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-------------------------------------------------------------------------
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-- begin of 6805
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.all;
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ENTITY UR6805 IS
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PORT(
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clk : in std_logic;
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rst : in std_logic;
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irq : in std_logic;
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addr : out std_logic_vector(15 downto 0);
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wr : out std_logic;
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datain : in std_logic_vector(7 downto 0);
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state : out std_logic_vector(3 downto 0);
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dataout : out std_logic_vector(7 downto 0)
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);
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END UR6805;
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ARCHITECTURE behavior OF UR6805 IS
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component mul8 port(
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a : in std_logic_vector(7 downto 0);
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b : in std_logic_vector(7 downto 0);
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prod : out std_logic_vector(15 downto 0)
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);
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end component mul8;
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constant CPUread : std_logic := '1';
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constant CPUwrite : std_logic := '0';
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constant addrPC : std_logic_vector(2 downto 0) := "000";
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constant addrSP : std_logic_vector(2 downto 0) := "001";
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constant addrHX : std_logic_vector(2 downto 0) := "010";
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constant addrTM : std_logic_vector(2 downto 0) := "011";
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constant addrX2 : std_logic_vector(2 downto 0) := "100";
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constant addrS2 : std_logic_vector(2 downto 0) := "101";
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constant addrX1 : std_logic_vector(2 downto 0) := "110";
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constant addrS1 : std_logic_vector(2 downto 0) := "111";
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constant outA : std_logic_vector(3 downto 0) := "0000";
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constant outH : std_logic_vector(3 downto 0) := "0001";
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constant outX : std_logic_vector(3 downto 0) := "0010";
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constant outSPL : std_logic_vector(3 downto 0) := "0011";
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constant outSPH : std_logic_vector(3 downto 0) := "0100";
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constant outPCL : std_logic_vector(3 downto 0) := "0101";
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constant outPCH : std_logic_vector(3 downto 0) := "0110";
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constant outTL : std_logic_vector(3 downto 0) := "0111";
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constant outTH : std_logic_vector(3 downto 0) := "1000";
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constant outHelp : std_logic_vector(3 downto 0) := "1001";
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constant outCode : std_logic_vector(3 downto 0) := "1010";
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type masker is array (0 to 7) of std_logic_vector(7 downto 0);
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signal mask0 : masker;
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signal mask1 : masker;
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signal regA : std_logic_vector(7 downto 0);
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signal regX : std_logic_vector(7 downto 0);
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signal regSP : std_logic_vector(15 downto 0);
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signal regPC : std_logic_vector(15 downto 0);
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signal flagH : std_logic;
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signal flagI : std_logic;
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signal flagN : std_logic;
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signal flagZ : std_logic;
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signal flagC : std_logic;
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signal help : std_logic_vector(7 downto 0);
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signal temp : std_logic_vector(15 downto 0);
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signal mainFSM : std_logic_vector(3 downto 0);
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signal addrMux : std_logic_vector(2 downto 0);
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signal dataMux : std_logic_vector(3 downto 0);
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signal opcode : std_logic_vector(7 downto 0);
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signal prod : std_logic_vector(15 downto 0);
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signal irq_d : std_logic;
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signal irqRequest : std_logic;
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signal trace : std_logic;
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signal trace_i : std_logic;
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signal traceOpCode : std_logic_vector(7 downto 0);
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begin
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mul: mul8 port map(
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a => regA,
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b => regX,
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prod => prod
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);
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addr <= regPC when addrMux = addrPC else
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regSP when addrMux = addrSP else
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x"00" & regX when addrMux = addrHX else
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temp when addrMux = addrTM else
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((x"00" & regX) + temp) when addrMux = addrX2 else
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(regSP + temp) when addrMux = addrS2 else
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((x"00" & regX) + (x"00" & temp(7 downto 0))) when addrMux = addrX1 else
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(regSP + (x"00" & temp(7 downto 0)));
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dataout <= regA when dataMux = outA else
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regX when dataMux = outH else
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regX when dataMux = outX else
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regSP( 7 downto 0) when dataMux = outSPL else
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regSP(15 downto 8) when dataMux = outSPH else
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regPC( 7 downto 0) when dataMux = outPCL else
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regPC(15 downto 8) when dataMux = outPCH else
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temp ( 7 downto 0) when dataMux = outTL else
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temp (15 downto 8) when dataMux = outTH else
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help when dataMux = outHelp else
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traceOpCode;
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state <= mainFSM;
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process(clk, rst)
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variable tres : std_logic_vector(7 downto 0);
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variable lres : std_logic_vector(15 downto 0);
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begin
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if rst = '0' then
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trace <= '0';
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trace_i <= '0';
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mask0(0) <= "11111110";
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mask0(1) <= "11111101";
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mask0(2) <= "11111011";
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mask0(3) <= "11110111";
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mask0(4) <= "11101111";
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mask0(5) <= "11011111";
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mask0(6) <= "10111111";
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mask0(7) <= "01111111";
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mask1(0) <= "00000001";
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mask1(1) <= "00000010";
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mask1(2) <= "00000100";
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mask1(3) <= "00001000";
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mask1(4) <= "00010000";
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mask1(5) <= "00100000";
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mask1(6) <= "01000000";
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mask1(7) <= "10000000";
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wr <= CPUread;
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flagH <= '0';
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flagI <= '1'; -- irq disabled
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flagN <= '0';
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flagZ <= '0';
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flagC <= '0';
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regA <= x"00";
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regX <= x"00";
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regSP <= x"00FF";
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regPC <= x"FFFE";
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temp <= x"FFFE";
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help <= x"00";
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dataMux <= outA;
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addrMux <= addrTM;
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irq_d <= '1';
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irqRequest <= '0';
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mainFSM <= "0000";
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else
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if rising_edge(clk) then
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irq_d <= irq;
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if (irq <= '0') and (irq_d = '1') and (flagI = '0') then -- irq falling edge ?
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irqRequest <= '1';
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end if;
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case mainFSM is
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when "0000" => --############# reset fetch PCH from FFFE
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regPC(15 downto 8) <= datain;
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temp <= temp + 1;
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mainFSM <= "0001";
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when "0001" => --############# reset fetch PCL from FFFF
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regPC(7 downto 0) <= datain;
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addrMux <= addrPC;
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mainFSM <= "0010";
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when "0010" => --##################### fetch opcode, instruction cycle 1
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trace <= trace_i;
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if trace = '1' then
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opcode <= x"83"; -- special SWI trace
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traceOpCode <= datain;
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addrMux <= addrSP;
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mainFSM <= "0011";
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elsif irqRequest = '1' then
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opcode <= x"83"; -- special SWI interrupt
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addrMux <= addrSP;
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mainFSM <= "0011";
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else
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opcode <= datain;
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case datain is
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when x"82" => -- RTT return trace special propietary instruction
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trace_i <= '1'; -- arm trace for next instruction
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regSP <= regSP + 1;
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addrMux <= addrSP;
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mainFSM <= "0011";
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when x"00" | x"02" | x"04" | x"06" | x"08" | x"0A" | x"0C" | x"0E" | -- BRSET n,opr8a,rel
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x"01" | x"03" | x"05" | x"07" | x"09" | x"0B" | x"0D" | x"0F" | -- BRCLR n,opr8a,rel
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x"10" | x"12" | x"14" | x"16" | x"18" | x"1A" | x"1C" | x"1E" | -- BSET n,opr8a
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x"11" | x"13" | x"15" | x"17" | x"19" | x"1B" | x"1D" | x"1F" | -- BCLR n,opr8a
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x"30" | x"33" | x"34" | -- NEG opr8a, COM opr8a, LSR opr8a
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x"36" | x"37" | x"38" | -- ROR opr8a, ASR opr8a, LSL opr8a
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x"39" | x"3A" | x"3C" | -- ROL opr8a, DEC opr8a, INC opr8a
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x"3D" | x"3F" | -- TST opr8a, CLR opr8a
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|
|
x"B0" | x"B1" | x"B2" | x"B3" | -- SUB opr8a, CMP opr8a, SBC opr8a, CPX opr8a
|
317 |
|
|
x"B4" | x"B5" | x"B6" | x"B7" | -- AND opr8a, BIT opr8a, LDA opr8a, STA opr8a
|
318 |
|
|
x"B8" | x"B9" | x"BA" | x"BB" | -- EOR opr8a, ADC opr8a, ORA opr8a, ADD opr8a
|
319 |
|
|
x"BC" | x"BE" | x"BF" => -- JMP opr8a, LDX opr8a, STX opr8a
|
320 |
|
|
temp <= x"0000";
|
321 |
|
|
regPC <= regPC + 1;
|
322 |
|
|
mainFSM <= "0011";
|
323 |
|
|
when x"20" | x"21" | x"22" | x"23" | x"24" | x"25" | x"26" | x"27" |
|
324 |
|
|
x"28" | x"29" | x"2A" | x"2B" | x"2C" | x"2D" | x"2E" | x"2F" | -- branches
|
325 |
|
|
x"C0" | x"C1" | x"C2" | x"C3" | -- SUB opr16a, CMP opr16a, SBC opr16a, CPX opr16a
|
326 |
|
|
x"C4" | x"C5" | x"C6" | x"C7" | -- AND opr16a, BIT opr16a, LDA opr16a, STA opr16a
|
327 |
|
|
x"C8" | x"C9" | x"CA" | x"CB" | -- EOR opr16a, ADC opr16a, ORA opr16a, ADD opr16a
|
328 |
|
|
x"CC" | x"CE" | x"CF" | -- JMP opr16a, LDX opr16a, STX opr16a
|
329 |
|
|
x"D0" | x"D1" | x"D2" | x"D3" | -- SUB oprx16,X, CMP oprx16,X, SBC oprx16,X, CPX oprx16,X
|
330 |
|
|
x"D4" | x"D5" | x"D6" | x"D7" | -- AND oprx16,X, BIT oprx16,X, LDA oprx16,X, STA oprx16,X
|
331 |
|
|
x"D8" | x"D9" | x"DA" | x"DB" | -- EOR oprx16,X, ADC oprx16,X, ORA oprx16,X, ADD oprx16,X
|
332 |
|
|
x"DC" | x"DE" | x"DF" => -- JMP oprx16,X, LDX oprx16,X, STX oprx16,X
|
333 |
|
|
regPC <= regPC + 1;
|
334 |
|
|
mainFSM <= "0011";
|
335 |
|
|
when x"70" | x"73" | x"74" | x"76" | x"77" | -- NEG ,X, COM ,X, LSR ,X, ROR ,X, ASR ,X
|
336 |
|
|
x"78" | x"79" | x"7A" | x"7C" | x"7D" => -- LSL ,X, ROL ,X, DEC ,X, INC ,X, TXT ,X
|
337 |
|
|
addrMux <= addrHX;
|
338 |
|
|
regPC <= regPC + 1;
|
339 |
|
|
mainFSM <= "0100";
|
340 |
|
|
when x"A0" | x"A1" | x"A2" | x"A3" | -- SUB #opr8i, CMP #opr8i, SBC #opr8i, CPX #opr8i
|
341 |
|
|
x"A4" | x"A5" | x"A6" | -- AND #opr8i, BIT #opr8i, LDA #opr8i
|
342 |
|
|
x"A8" | x"A9" | x"AA" | x"AB" | -- EOR #opr8i, ADC #opr8i, ORA #opr8i, ADD #opr8i
|
343 |
|
|
x"AE" => -- LDX #opr8i
|
344 |
|
|
regPC <= regPC + 1;
|
345 |
|
|
mainFSM <= "0101";
|
346 |
|
|
when x"E0" | x"E1" | x"E2" | x"E3" | -- SUB oprx8,X, CMP oprx8,X, SBC oprx8,X, CPX oprx8,X
|
347 |
|
|
x"E4" | x"E5" | x"E6" | x"E7" | -- AND oprx8,X, BIT oprx8,X, LDA oprx8,X, STA oprx8,X
|
348 |
|
|
x"E8" | x"E9" | x"EA" | x"EB" | -- EOR oprx8,X, ADC oprx8,X, ORA oprx8,X, ADD oprx8,X
|
349 |
|
|
x"EC" | x"EE" | x"EF" => -- JMP oprx8,X, LDX oprx8,X, STX oprx8,X
|
350 |
|
|
regPC <= regPC + 1;
|
351 |
|
|
mainFSM <= "0100";
|
352 |
|
|
when x"F0" | x"F1" | x"F2" | x"F3" | -- SUB ,X, CMP ,X, SBC ,X, CPX ,X
|
353 |
|
|
x"F4" | x"F5" | x"F6" | -- AND ,X, BIT ,X, LDA ,X
|
354 |
|
|
x"F8" | x"F9" | x"FA" | x"FB" | -- EOR ,X, ADC ,X, ORA ,X, ADD ,X
|
355 |
|
|
x"FE" => -- LDX ,X
|
356 |
|
|
addrMux <= addrHX;
|
357 |
|
|
regPC <= regPC + 1;
|
358 |
|
|
mainFSM <= "0101";
|
359 |
|
|
when x"FC" => -- JMP ,X
|
360 |
|
|
regPC <= x"00" & regX;
|
361 |
|
|
mainFSM <= "0010";
|
362 |
|
|
when x"F7" => -- STA ,X
|
363 |
|
|
wr <= CPUwrite;
|
364 |
|
|
flagN <= regA(7);
|
365 |
|
|
if regA = x"00" then
|
366 |
|
|
flagZ <= '1';
|
367 |
|
|
else
|
368 |
|
|
flagZ <= '0';
|
369 |
|
|
end if;
|
370 |
|
|
dataMux <= outA;
|
371 |
|
|
addrMux <= addrHX;
|
372 |
|
|
regPC <= regPC + 1;
|
373 |
|
|
mainFSM <= "0101";
|
374 |
|
|
when x"FF" => -- STX ,X
|
375 |
|
|
wr <= CPUwrite;
|
376 |
|
|
flagN <= regX(7);
|
377 |
|
|
if regX = x"00" then
|
378 |
|
|
flagZ <= '1';
|
379 |
|
|
else
|
380 |
|
|
flagZ <= '0';
|
381 |
|
|
end if;
|
382 |
|
|
dataMux <= outX;
|
383 |
|
|
addrMux <= addrHX;
|
384 |
|
|
regPC <= regPC + 1;
|
385 |
|
|
mainFSM <= "0101";
|
386 |
|
|
when x"40" => -- NEGA
|
387 |
|
|
regA <= x"00" - regA;
|
388 |
|
|
tres := x"00" - regA;
|
389 |
|
|
flagN <= tres(7);
|
390 |
|
|
if tres = x"00" then
|
391 |
|
|
flagZ <= '1';
|
392 |
|
|
flagC <= '0';
|
393 |
|
|
else
|
394 |
|
|
flagC <= '1';
|
395 |
|
|
flagZ <= '0';
|
396 |
|
|
end if;
|
397 |
|
|
regPC <= regPC + 1;
|
398 |
|
|
mainFSM <= "0010";
|
399 |
|
|
when x"42" => -- MUL
|
400 |
|
|
flagH <= '0';
|
401 |
|
|
flagC <= '0';
|
402 |
|
|
regA <= prod(7 downto 0);
|
403 |
|
|
regX <= prod(15 downto 8);
|
404 |
|
|
regPC <= regPC + 1;
|
405 |
|
|
mainFSM <= "0010";
|
406 |
|
|
when x"43" => -- COMA
|
407 |
|
|
regA <= regA xor x"FF";
|
408 |
|
|
tres := regA xor x"FF";
|
409 |
|
|
flagC <= '1';
|
410 |
|
|
flagN <= tres(7);
|
411 |
|
|
if tres = x"00" then
|
412 |
|
|
flagZ <= '1';
|
413 |
|
|
else
|
414 |
|
|
flagZ <= '0';
|
415 |
|
|
end if;
|
416 |
|
|
regPC <= regPC + 1;
|
417 |
|
|
mainFSM <= "0010";
|
418 |
|
|
when x"44" => -- LSRA
|
419 |
|
|
regA <= "0" & regA(7 downto 1);
|
420 |
|
|
tres := "0" & regA(7 downto 1);
|
421 |
|
|
flagN <= '0';
|
422 |
|
|
flagC <= regA(0);
|
423 |
|
|
if tres = x"00" then
|
424 |
|
|
flagZ <= '1';
|
425 |
|
|
else
|
426 |
|
|
flagZ <= '0';
|
427 |
|
|
end if;
|
428 |
|
|
regPC <= regPC + 1;
|
429 |
|
|
mainFSM <= "0010";
|
430 |
|
|
when x"46" => -- RORA
|
431 |
|
|
regA <= flagC & regA(7 downto 1);
|
432 |
|
|
tres := flagC & regA(7 downto 1);
|
433 |
|
|
flagN <= flagC;
|
434 |
|
|
flagC <= regA(0);
|
435 |
|
|
if tres = x"00" then
|
436 |
|
|
flagZ <= '1';
|
437 |
|
|
else
|
438 |
|
|
flagZ <= '0';
|
439 |
|
|
end if;
|
440 |
|
|
regPC <= regPC + 1;
|
441 |
|
|
mainFSM <= "0010";
|
442 |
|
|
when x"47" => -- ASRA
|
443 |
|
|
regA <= regA(7) & regA(7 downto 1);
|
444 |
|
|
tres := regA(7) & regA(7 downto 1);
|
445 |
|
|
flagN <= regA(7);
|
446 |
|
|
flagC <= regA(0);
|
447 |
|
|
if tres = x"00" then
|
448 |
|
|
flagZ <= '1';
|
449 |
|
|
else
|
450 |
|
|
flagZ <= '0';
|
451 |
|
|
end if;
|
452 |
|
|
regPC <= regPC + 1;
|
453 |
|
|
mainFSM <= "0010";
|
454 |
|
|
when x"48" => -- LSLA
|
455 |
|
|
regA <= regA(6 downto 0) & "0";
|
456 |
|
|
tres := regA(6 downto 0) & "0";
|
457 |
|
|
flagN <= regA(6);
|
458 |
|
|
flagC <= regA(7);
|
459 |
|
|
if tres = x"00" then
|
460 |
|
|
flagZ <= '1';
|
461 |
|
|
else
|
462 |
|
|
flagZ <= '0';
|
463 |
|
|
end if;
|
464 |
|
|
regPC <= regPC + 1;
|
465 |
|
|
mainFSM <= "0010";
|
466 |
|
|
when x"49" => -- ROLA
|
467 |
|
|
regA <= regA(6 downto 0) & flagC;
|
468 |
|
|
tres := regA(6 downto 0) & flagC;
|
469 |
|
|
flagN <= regA(6);
|
470 |
|
|
flagC <= regA(7);
|
471 |
|
|
if tres = x"00" then
|
472 |
|
|
flagZ <= '1';
|
473 |
|
|
else
|
474 |
|
|
flagZ <= '0';
|
475 |
|
|
end if;
|
476 |
|
|
regPC <= regPC + 1;
|
477 |
|
|
mainFSM <= "0010";
|
478 |
|
|
when x"4A" => -- DECA
|
479 |
|
|
regA <= regA - 1;
|
480 |
|
|
tres := regA - 1;
|
481 |
|
|
flagN <= tres(7);
|
482 |
|
|
if tres = x"00" then
|
483 |
|
|
flagZ <= '1';
|
484 |
|
|
else
|
485 |
|
|
flagZ <= '0';
|
486 |
|
|
end if;
|
487 |
|
|
regPC <= regPC + 1;
|
488 |
|
|
mainFSM <= "0010";
|
489 |
|
|
when x"4C" => -- INCA
|
490 |
|
|
regA <= regA + 1;
|
491 |
|
|
tres := regA + 1;
|
492 |
|
|
flagN <= tres(7);
|
493 |
|
|
if tres = x"00" then
|
494 |
|
|
flagZ <= '1';
|
495 |
|
|
else
|
496 |
|
|
flagZ <= '0';
|
497 |
|
|
end if;
|
498 |
|
|
regPC <= regPC + 1;
|
499 |
|
|
mainFSM <= "0010";
|
500 |
|
|
when x"4D" => -- TSTA
|
501 |
|
|
flagN <= regA(7);
|
502 |
|
|
if regA = x"00" then
|
503 |
|
|
flagZ <= '1';
|
504 |
|
|
else
|
505 |
|
|
flagZ <= '0';
|
506 |
|
|
end if;
|
507 |
|
|
regPC <= regPC + 1;
|
508 |
|
|
mainFSM <= "0010";
|
509 |
|
|
when x"4F" => -- CLRA
|
510 |
|
|
regA <= x"00";
|
511 |
|
|
flagN <= '0';
|
512 |
|
|
flagZ <= '1';
|
513 |
|
|
regPC <= regPC + 1;
|
514 |
|
|
mainFSM <= "0010";
|
515 |
|
|
when x"50" => -- NEGX
|
516 |
|
|
regX <= x"00" - regX;
|
517 |
|
|
tres := x"00" - regX;
|
518 |
|
|
flagN <= tres(7);
|
519 |
|
|
if tres = x"00" then
|
520 |
|
|
flagZ <= '1';
|
521 |
|
|
flagC <= '0';
|
522 |
|
|
else
|
523 |
|
|
flagC <= '1';
|
524 |
|
|
flagZ <= '0';
|
525 |
|
|
end if;
|
526 |
|
|
regPC <= regPC + 1;
|
527 |
|
|
mainFSM <= "0010";
|
528 |
|
|
when x"53" => -- COMX
|
529 |
|
|
regX <= regX xor x"FF";
|
530 |
|
|
tres := regX xor x"FF";
|
531 |
|
|
flagC <= '1';
|
532 |
|
|
flagN <= tres(7);
|
533 |
|
|
if tres = x"00" then
|
534 |
|
|
flagZ <= '1';
|
535 |
|
|
else
|
536 |
|
|
flagZ <= '0';
|
537 |
|
|
end if;
|
538 |
|
|
regPC <= regPC + 1;
|
539 |
|
|
mainFSM <= "0010";
|
540 |
|
|
when x"54" => -- LSRX
|
541 |
|
|
regX <= "0" & regX(7 downto 1);
|
542 |
|
|
tres := "0" & regX(7 downto 1);
|
543 |
|
|
flagN <= '0';
|
544 |
|
|
flagC <= regX(0);
|
545 |
|
|
if tres = x"00" then
|
546 |
|
|
flagZ <= '1';
|
547 |
|
|
else
|
548 |
|
|
flagZ <= '0';
|
549 |
|
|
end if;
|
550 |
|
|
regPC <= regPC + 1;
|
551 |
|
|
mainFSM <= "0010";
|
552 |
|
|
when x"56" => -- RORX
|
553 |
|
|
regX <= flagC & regX(7 downto 1);
|
554 |
|
|
tres := flagC & regX(7 downto 1);
|
555 |
|
|
flagN <= flagC;
|
556 |
|
|
flagC <= regX(0);
|
557 |
|
|
if tres = x"00" then
|
558 |
|
|
flagZ <= '1';
|
559 |
|
|
else
|
560 |
|
|
flagZ <= '0';
|
561 |
|
|
end if;
|
562 |
|
|
regPC <= regPC + 1;
|
563 |
|
|
mainFSM <= "0010";
|
564 |
|
|
when x"57" => -- ASRX
|
565 |
|
|
regX <= regX(7) & regX(7 downto 1);
|
566 |
|
|
tres := regX(7) & regX(7 downto 1);
|
567 |
|
|
flagN <= regX(7);
|
568 |
|
|
flagC <= regX(0);
|
569 |
|
|
if tres = x"00" then
|
570 |
|
|
flagZ <= '1';
|
571 |
|
|
else
|
572 |
|
|
flagZ <= '0';
|
573 |
|
|
end if;
|
574 |
|
|
regPC <= regPC + 1;
|
575 |
|
|
mainFSM <= "0010";
|
576 |
|
|
when x"58" => -- LSLX
|
577 |
|
|
regX <= regX(6 downto 0) & "0";
|
578 |
|
|
tres := regX(6 downto 0) & "0";
|
579 |
|
|
flagN <= regX(6);
|
580 |
|
|
flagC <= regX(7);
|
581 |
|
|
if tres = x"00" then
|
582 |
|
|
flagZ <= '1';
|
583 |
|
|
else
|
584 |
|
|
flagZ <= '0';
|
585 |
|
|
end if;
|
586 |
|
|
regPC <= regPC + 1;
|
587 |
|
|
mainFSM <= "0010";
|
588 |
|
|
when x"59" => -- ROLX
|
589 |
|
|
regX <= regX(6 downto 0) & flagC;
|
590 |
|
|
tres := regX(6 downto 0) & flagC;
|
591 |
|
|
flagN <= regX(6);
|
592 |
|
|
flagC <= regX(7);
|
593 |
|
|
if tres = x"00" then
|
594 |
|
|
flagZ <= '1';
|
595 |
|
|
else
|
596 |
|
|
flagZ <= '0';
|
597 |
|
|
end if;
|
598 |
|
|
regPC <= regPC + 1;
|
599 |
|
|
mainFSM <= "0010";
|
600 |
|
|
when x"5A" => -- DECX
|
601 |
|
|
regX <= regX(7 downto 0) - 1;
|
602 |
|
|
tres := regX(7 downto 0) - 1;
|
603 |
|
|
flagN <= tres(7);
|
604 |
|
|
if tres = x"00" then
|
605 |
|
|
flagZ <= '1';
|
606 |
|
|
else
|
607 |
|
|
flagZ <= '0';
|
608 |
|
|
end if;
|
609 |
|
|
regPC <= regPC + 1;
|
610 |
|
|
mainFSM <= "0010";
|
611 |
|
|
when x"5C" => -- INCX
|
612 |
|
|
regX <= regX(7 downto 0) + 1;
|
613 |
|
|
tres := regX(7 downto 0) + 1;
|
614 |
|
|
flagN <= tres(7);
|
615 |
|
|
if tres = x"00" then
|
616 |
|
|
flagZ <= '1';
|
617 |
|
|
else
|
618 |
|
|
flagZ <= '0';
|
619 |
|
|
end if;
|
620 |
|
|
regPC <= regPC + 1;
|
621 |
|
|
mainFSM <= "0010";
|
622 |
|
|
when x"5D" => -- TSTX
|
623 |
|
|
flagN <= regX(7);
|
624 |
|
|
if regX = x"00" then
|
625 |
|
|
flagZ <= '1';
|
626 |
|
|
else
|
627 |
|
|
flagZ <= '0';
|
628 |
|
|
end if;
|
629 |
|
|
regPC <= regPC + 1;
|
630 |
|
|
mainFSM <= "0010";
|
631 |
|
|
when x"5F" => -- CLRX
|
632 |
|
|
regX <= x"00";
|
633 |
|
|
flagN <= '0';
|
634 |
|
|
flagZ <= '1';
|
635 |
|
|
regPC <= regPC + 1;
|
636 |
|
|
mainFSM <= "0010";
|
637 |
|
|
when x"60" | x"63" | x"64" | x"66" | -- NEG oprx8,X, COM oprx8,X, LSR oprx8,X, ROR oprx8,X
|
638 |
|
|
x"67" | x"68" | x"69" | x"6A" | -- ASR oprx8,X, LSL oprx8,X, ROL oprx8,X, DEC oprx8,X
|
639 |
|
|
x"6C" | x"6D" | x"6F" => -- INC oprx8,X, TST oprx8,X, CLR oprx8,X
|
640 |
|
|
temp <= x"00" & regX;
|
641 |
|
|
regPC <= regPC + 1;
|
642 |
|
|
mainFSM <= "0011";
|
643 |
|
|
when x"7F" => -- CLR ,X
|
644 |
|
|
flagN <= '0';
|
645 |
|
|
flagZ <= '1';
|
646 |
|
|
addrMux <= addrHX;
|
647 |
|
|
dataMux <= outHelp;
|
648 |
|
|
wr <= CPUwrite;
|
649 |
|
|
help <= x"00";
|
650 |
|
|
regPC <= regPC + 1;
|
651 |
|
|
mainFSM <= "0011";
|
652 |
|
|
when x"80" | x"81" => -- RTI, RTS
|
653 |
|
|
regSP <= regSP + 1;
|
654 |
|
|
addrMux <= addrSP;
|
655 |
|
|
mainFSM <= "0011";
|
656 |
|
|
when x"83" => -- SWI
|
657 |
|
|
regPC <= regPC + 1;
|
658 |
|
|
addrMux <= addrSP;
|
659 |
|
|
mainFSM <= "0011";
|
660 |
|
|
when x"8E" => -- STOP currently unsupported
|
661 |
|
|
regPC <= regPC + 1;
|
662 |
|
|
mainFSM <= "0010";
|
663 |
|
|
when x"8F" => -- WAIT currently unsupported
|
664 |
|
|
regPC <= regPC + 1;
|
665 |
|
|
mainFSM <= "0010";
|
666 |
|
|
when x"97" => -- TAX
|
667 |
|
|
regX <= regA;
|
668 |
|
|
regPC <= regPC + 1;
|
669 |
|
|
mainFSM <= "0010";
|
670 |
|
|
when x"98" | x"99" => -- CLC, SEC
|
671 |
|
|
flagC <= datain(0);
|
672 |
|
|
regPC <= regPC + 1;
|
673 |
|
|
mainFSM <= "0010";
|
674 |
|
|
when x"9A" | x"9B" => -- CLI, SEI ATTENTION!!!
|
675 |
|
|
flagI <= datain(0);
|
676 |
|
|
regPC <= regPC + 1;
|
677 |
|
|
mainFSM <= "0010";
|
678 |
|
|
when x"9C" => -- RSP
|
679 |
|
|
regSP <= x"00FF";
|
680 |
|
|
regPC <= regPC + 1;
|
681 |
|
|
mainFSM <= "0010";
|
682 |
|
|
when x"31" | x"41" | x"35" | x"3B" | x"45" |
|
683 |
|
|
x"4B" | x"4E" | x"51" | x"52" | x"55" |
|
684 |
|
|
x"5B" | x"5E" | x"61" | x"62" | x"65" |
|
685 |
|
|
x"6B" | x"6E" | x"71" | x"72" | x"75" | x"7B" | x"7E" |
|
686 |
|
|
x"84" | x"85" | x"86" | x"87" | x"88" |
|
687 |
|
|
x"89" | x"8A" | x"8B" | x"8C" | x"8D" |
|
688 |
|
|
x"90" | x"91" | x"92" | x"93" | x"94" | x"95" | x"9D" | x"9E" |
|
689 |
|
|
x"A7" | x"AC" | x"AF" => -- NOP
|
690 |
|
|
regPC <= regPC + 1;
|
691 |
|
|
mainFSM <= "0010";
|
692 |
|
|
when x"9F" => -- TXA
|
693 |
|
|
regA <= regX;
|
694 |
|
|
regPC <= regPC + 1;
|
695 |
|
|
mainFSM <= "0010";
|
696 |
|
|
when x"AD" | x"BD" | x"ED" => -- BSR rel, JSR opr8a, JSR oprx8,X
|
697 |
|
|
temp <= regPC + 2;
|
698 |
|
|
regPC <= regPC + 1;
|
699 |
|
|
mainFSM <= "0011";
|
700 |
|
|
when x"CD" | x"DD" => -- JSR opr16a, JSR oprx16,X
|
701 |
|
|
temp <= regPC + 3;
|
702 |
|
|
regPC <= regPC + 1;
|
703 |
|
|
mainFSM <= "0011";
|
704 |
|
|
when x"FD" => -- JSR ,X
|
705 |
|
|
temp <= regPC + 1;
|
706 |
|
|
wr <= CPUwrite;
|
707 |
|
|
addrMux <= addrSP;
|
708 |
|
|
dataMux <= outTL;
|
709 |
|
|
regPC <= regPC + 1;
|
710 |
|
|
mainFSM <= "0100";
|
711 |
|
|
|
712 |
|
|
|
713 |
|
|
when others =>
|
714 |
|
|
mainFSM <= "0000";
|
715 |
|
|
end case; -- datain
|
716 |
|
|
end if; -- trace = '1'
|
717 |
|
|
|
718 |
|
|
when "0011" => --##################### instruction cycle 2
|
719 |
|
|
case opcode is
|
720 |
|
|
when x"00" | x"02" | x"04" | x"06" | x"08" | x"0A" | x"0C" | x"0E" | -- BRSET n,opr8a,rel
|
721 |
|
|
x"01" | x"03" | x"05" | x"07" | x"09" | x"0B" | x"0D" | x"0F" | -- BRCLR n,opr8a,rel
|
722 |
|
|
x"10" | x"12" | x"14" | x"16" | x"18" | x"1A" | x"1C" | x"1E" | -- BSET n,opr8a
|
723 |
|
|
x"11" | x"13" | x"15" | x"17" | x"19" | x"1B" | x"1D" | x"1F" | -- BCLR n,opr8a
|
724 |
|
|
x"30" | x"33" | x"34" | x"36" | -- NEG opr8a, COM opr8a, LSR opr8a, ROR opr8a
|
725 |
|
|
x"37" | x"38" | x"39" | x"3A" | x"3C" | -- ASR opr8a, LSL opr8a, ROL opr8a, DEC opr8a, INC opr8a
|
726 |
|
|
x"3D" => -- TST opr8a
|
727 |
|
|
temp(7 downto 0) <= datain;
|
728 |
|
|
addrMux <= addrTM;
|
729 |
|
|
regPC <= regPC + 1;
|
730 |
|
|
mainFSM <= "0100";
|
731 |
|
|
when x"C0" | x"C1" | x"C2" | x"C3" | -- SUB opr16a, CMP opr16a, SBC opr16a, CPX opr16a
|
732 |
|
|
x"C4" | x"C5" | x"C6" | x"C7" | -- AND opr16a, BIT opr16a, LDA opr16a, STA opr16a
|
733 |
|
|
x"C8" | x"C9" | x"CA" | x"CB" | -- EOR opr16a, ADC opr16a, ORA opr16a, ADD opr16a
|
734 |
|
|
x"CC" | x"CE" | x"CF" | -- JMP opr16a, LDX opr16a, STX opr16a
|
735 |
|
|
x"D0" | x"D1" | x"D2" | x"D3" | -- SUB oprx16,X, CMP oprx16,X, SBC oprx16,X, CPX oprx16,X
|
736 |
|
|
x"D4" | x"D5" | x"D6" | x"D7" | -- AND oprx16,X, BIT oprx16,X, LDA oprx16,X, STA oprx16,X
|
737 |
|
|
x"D8" | x"D9" | x"DA" | x"DB" | -- EOR oprx16,X, ADC oprx16,X, ORA oprx16,X, ADD oprx16,X
|
738 |
|
|
x"DC" | x"DE" | x"DF" => -- JMP oprx16,X, LDX oprx16,X, STX oprx16,X
|
739 |
|
|
temp(15 downto 8) <= datain;
|
740 |
|
|
regPC <= regPC + 1;
|
741 |
|
|
mainFSM <= "0100";
|
742 |
|
|
when x"B7" => -- STA opr8a
|
743 |
|
|
wr <= CPUwrite;
|
744 |
|
|
dataMux <= outA;
|
745 |
|
|
temp(7 downto 0) <= datain;
|
746 |
|
|
addrMux <= addrTM;
|
747 |
|
|
regPC <= regPC + 1;
|
748 |
|
|
mainFSM <= "0101";
|
749 |
|
|
when x"BF" => -- STX opr8a
|
750 |
|
|
wr <= CPUwrite;
|
751 |
|
|
dataMux <= outX;
|
752 |
|
|
temp(7 downto 0) <= datain;
|
753 |
|
|
addrMux <= addrTM;
|
754 |
|
|
regPC <= regPC + 1;
|
755 |
|
|
mainFSM <= "0101";
|
756 |
|
|
when x"B0" | x"B1" | x"B2" | x"B3" | -- SUB opr8a, CMP opr8a, SBC opr8a, CPX opr8a
|
757 |
|
|
x"B4" | x"B5" | x"B6" | -- AND opr8a, BIT opr8a, LDA opr8a
|
758 |
|
|
x"B8" | x"B9" | x"BA" | x"BB" | -- EOR opr8a, ADC opr8a, ORA opr8a, ADD opr8a
|
759 |
|
|
x"BE" => -- LDX opr8a
|
760 |
|
|
temp(7 downto 0) <= datain;
|
761 |
|
|
addrMux <= addrTM;
|
762 |
|
|
regPC <= regPC + 1;
|
763 |
|
|
mainFSM <= "0101";
|
764 |
|
|
|
765 |
|
|
when x"20" => -- BRA
|
766 |
|
|
if datain(7) = '0' then
|
767 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
768 |
|
|
else
|
769 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
770 |
|
|
end if;
|
771 |
|
|
mainFSM <= "0010";
|
772 |
|
|
when x"21" => -- BRN
|
773 |
|
|
regPC <= regPC + 1;
|
774 |
|
|
mainFSM <= "0010";
|
775 |
|
|
when x"22" | x"23" => -- BHI, BLS
|
776 |
|
|
if (flagC or flagZ) = opcode(0) then
|
777 |
|
|
if datain(7) = '0' then
|
778 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
779 |
|
|
else
|
780 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
781 |
|
|
end if;
|
782 |
|
|
else
|
783 |
|
|
regPC <= regPC + 1;
|
784 |
|
|
end if;
|
785 |
|
|
mainFSM <= "0010";
|
786 |
|
|
when x"24" | x"25" => -- BCC, BCS
|
787 |
|
|
if (flagC = opcode(0)) then
|
788 |
|
|
if datain(7) = '0' then
|
789 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
790 |
|
|
else
|
791 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
792 |
|
|
end if;
|
793 |
|
|
else
|
794 |
|
|
regPC <= regPC + 1;
|
795 |
|
|
end if;
|
796 |
|
|
mainFSM <= "0010";
|
797 |
|
|
when x"26" | x"27" => -- BNE, BEQ
|
798 |
|
|
if (flagZ = opcode(0)) then
|
799 |
|
|
if datain(7) = '0' then
|
800 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
801 |
|
|
else
|
802 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
803 |
|
|
end if;
|
804 |
|
|
else
|
805 |
|
|
regPC <= regPC + 1;
|
806 |
|
|
end if;
|
807 |
|
|
mainFSM <= "0010";
|
808 |
|
|
when x"28" | x"29" => -- BHCC, BHCS
|
809 |
|
|
if (flagH = opcode(0)) then
|
810 |
|
|
if datain(7) = '0' then
|
811 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
812 |
|
|
else
|
813 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
814 |
|
|
end if;
|
815 |
|
|
else
|
816 |
|
|
regPC <= regPC + 1;
|
817 |
|
|
end if;
|
818 |
|
|
mainFSM <= "0010";
|
819 |
|
|
when x"2A" | x"2B" => -- BPL, BMI
|
820 |
|
|
if (flagN = opcode(0)) then
|
821 |
|
|
if datain(7) = '0' then
|
822 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
823 |
|
|
else
|
824 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
825 |
|
|
end if;
|
826 |
|
|
else
|
827 |
|
|
regPC <= regPC + 1;
|
828 |
|
|
end if;
|
829 |
|
|
mainFSM <= "0010";
|
830 |
|
|
when x"2C" | x"2D" => -- BMC, BMS
|
831 |
|
|
if (flagI = opcode(0)) then
|
832 |
|
|
if datain(7) = '0' then
|
833 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
834 |
|
|
else
|
835 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
836 |
|
|
end if;
|
837 |
|
|
else
|
838 |
|
|
regPC <= regPC + 1;
|
839 |
|
|
end if;
|
840 |
|
|
mainFSM <= "0010";
|
841 |
|
|
when x"2E" | x"2F" => -- BIL, BIH
|
842 |
|
|
if (irq = opcode(0)) then
|
843 |
|
|
if datain(7) = '0' then
|
844 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
845 |
|
|
else
|
846 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
847 |
|
|
end if;
|
848 |
|
|
else
|
849 |
|
|
regPC <= regPC + 1;
|
850 |
|
|
end if;
|
851 |
|
|
mainFSM <= "0010";
|
852 |
|
|
when x"3F" | x"6F" => -- CLR opr8a, CLR oprx8,X
|
853 |
|
|
wr <= CPUwrite;
|
854 |
|
|
case opcode is
|
855 |
|
|
when x"3F" =>
|
856 |
|
|
temp(7 downto 0) <= datain;
|
857 |
|
|
when x"6F" =>
|
858 |
|
|
temp <= temp + (x"00" & datain);
|
859 |
|
|
when others =>
|
860 |
|
|
temp <= x"0000";
|
861 |
|
|
end case;
|
862 |
|
|
addrMux <= addrTM;
|
863 |
|
|
dataMux <= outHelp;
|
864 |
|
|
flagZ <= '1';
|
865 |
|
|
flagN <= '0';
|
866 |
|
|
help <= x"00";
|
867 |
|
|
regPC <= regPC + 1;
|
868 |
|
|
mainFSM <= "0100";
|
869 |
|
|
when x"60" | x"63" | x"64" | x"66" | -- NEG oprx8,X, COM oprx8,X, LSR oprx8,X, ROR oprx8,X
|
870 |
|
|
x"67" | x"68" | x"69" | x"6A" | -- ASR oprx8,X, LSL oprx8,X, ROL oprx8,X, DEC oprx8,X
|
871 |
|
|
x"6C" | x"6D" => -- INC oprx8,X, TST oprx8,X
|
872 |
|
|
temp <= temp + (x"00" & datain);
|
873 |
|
|
regPC <= regPC + 1;
|
874 |
|
|
addrMux <= addrTM;
|
875 |
|
|
mainFSM <= "0100";
|
876 |
|
|
when x"7F" => -- CLR ,X
|
877 |
|
|
wr <= CPUread;
|
878 |
|
|
addrMux <= addrPC;
|
879 |
|
|
mainFSM <= "0010";
|
880 |
|
|
when x"80" | x"82" => -- RTI, RTT
|
881 |
|
|
flagH <= datain(4);
|
882 |
|
|
flagI <= datain(3); ------- PLEASE RESTORE AT LATER TIME
|
883 |
|
|
flagN <= datain(2);
|
884 |
|
|
flagZ <= datain(1);
|
885 |
|
|
flagC <= datain(0);
|
886 |
|
|
regSP <= regSP + 1;
|
887 |
|
|
mainFSM <= "0100";
|
888 |
|
|
when x"81" => -- RTS
|
889 |
|
|
regPC(15 downto 8) <= datain;
|
890 |
|
|
regSP <= regSP + 1;
|
891 |
|
|
mainFSM <= "0100";
|
892 |
|
|
when x"83" => -- SWI
|
893 |
|
|
wr <= CPUwrite;
|
894 |
|
|
dataMux <= outPCL;
|
895 |
|
|
mainFSM <= "0100";
|
896 |
|
|
when x"AD" | x"BD" | x"ED" => -- BSR rel, JSR opr8a, JSR oprx8,X
|
897 |
|
|
regPC <= regPC + 1;
|
898 |
|
|
wr <= CPUwrite;
|
899 |
|
|
help <= datain;
|
900 |
|
|
addrMux <= addrSP;
|
901 |
|
|
dataMux <= outPCL;
|
902 |
|
|
mainFSM <= "0100";
|
903 |
|
|
when x"BC" => -- JMP opr8a
|
904 |
|
|
regPC <= (x"00" & datain);
|
905 |
|
|
mainFSM <= "0010";
|
906 |
|
|
when x"CD" | x"DD" => -- JSR opr16a, JSR oprx16,X
|
907 |
|
|
temp(15 downto 8) <= datain;
|
908 |
|
|
regPC <= regPC + 1;
|
909 |
|
|
mainFSM <= "0100";
|
910 |
|
|
|
911 |
|
|
when others =>
|
912 |
|
|
mainFSM <= "0000";
|
913 |
|
|
end case; -- opcode
|
914 |
|
|
|
915 |
|
|
when "0100" => --##################### instruction cycle 3
|
916 |
|
|
case opcode is
|
917 |
|
|
when x"00" | x"02" | x"04" | x"06" | x"08" | x"0A" | x"0C" | x"0E" | -- BRSET n,opr8a,rel
|
918 |
|
|
x"01" | x"03" | x"05" | x"07" | x"09" | x"0B" | x"0D" | x"0F" => -- BRCLR n,opr8a,rel
|
919 |
|
|
if (datain and mask1(conv_integer(opcode(3 downto 1)))) /= x"00" then
|
920 |
|
|
flagC <= '1';
|
921 |
|
|
else
|
922 |
|
|
flagC <= '0';
|
923 |
|
|
end if;
|
924 |
|
|
addrMux <= addrPC;
|
925 |
|
|
mainFSM <= "0101";
|
926 |
|
|
when x"10" | x"12" | x"14" | x"16" | x"18" | x"1A" | x"1C" | x"1E" | -- BSET n,opr8a
|
927 |
|
|
x"11" | x"13" | x"15" | x"17" | x"19" | x"1B" | x"1D" | x"1F" => -- BCLR n,opr8a
|
928 |
|
|
wr <= CPUwrite;
|
929 |
|
|
dataMux <= outHelp;
|
930 |
|
|
if opcode(0) = '0' then
|
931 |
|
|
help <= datain or mask1(conv_integer(opcode(3 downto 1)));
|
932 |
|
|
else
|
933 |
|
|
help <= datain and mask0(conv_integer(opcode(3 downto 1)));
|
934 |
|
|
end if;
|
935 |
|
|
mainFSM <= "0101";
|
936 |
|
|
when x"C0" | x"C1" | x"C2" | x"C3" | -- SUB opr16a, CMP opr16a, SBC opr16a, CPX opr16a
|
937 |
|
|
x"C4" | x"C5" | x"C6" | -- AND opr16a, BIT opr16a, LDA opr16a
|
938 |
|
|
x"C8" | x"C9" | x"CA" | x"CB" | -- EOR opr16a, ADC opr16a, ORA opr16a, ADD opr16a
|
939 |
|
|
x"CE" | -- LDX opr16a
|
940 |
|
|
x"D0" | x"D1" | x"D2" | x"D3" | -- SUB oprx16,X, CMP oprx16,X, SBC oprx16,X, CPX oprx16,X
|
941 |
|
|
x"D4" | x"D5" | x"D6" | -- AND oprx16,X, BIT oprx16,X, LDA oprx16,X
|
942 |
|
|
x"D8" | x"D9" | x"DA" | x"DB" | -- EOR oprx16,X, ADC oprx16,X, ORA oprx16,X, ADD oprx16,X
|
943 |
|
|
x"DE" | -- LDX oprx16,X
|
944 |
|
|
x"E0" | x"E1" | x"E2" | x"E3" | -- SUB oprx8,X, CMP oprx8,X, SBC oprx8,X, CPX oprx8,X
|
945 |
|
|
x"E4" | x"E5" | x"E6" | -- AND oprx8,X, BIT oprx8,X, LDA oprx8,X
|
946 |
|
|
x"E8" | x"E9" | x"EA" | x"EB" | -- EOR oprx8,X, ADC oprx8,X, ORA oprx8,X, ADD oprx8,X
|
947 |
|
|
x"EE" => -- LDX oprx8,X
|
948 |
|
|
temp(7 downto 0) <= datain;
|
949 |
|
|
case opcode(7 downto 4) is
|
950 |
|
|
when x"C" =>
|
951 |
|
|
addrMux <= addrTM;
|
952 |
|
|
when x"D" =>
|
953 |
|
|
addrMux <= addrX2;
|
954 |
|
|
when x"E" =>
|
955 |
|
|
addrMux <= addrX1;
|
956 |
|
|
when others =>
|
957 |
|
|
null;
|
958 |
|
|
end case;
|
959 |
|
|
regPC <= regPC + 1;
|
960 |
|
|
mainFSM <= "0101";
|
961 |
|
|
when x"CC" => -- JMP opr16a
|
962 |
|
|
regPC <= temp(15 downto 8) & datain;
|
963 |
|
|
mainFSM <= "0010";
|
964 |
|
|
when x"DC" => -- JMP oprx16,X
|
965 |
|
|
regPC <= (temp(15 downto 8) & datain) + (x"00" & regX);
|
966 |
|
|
mainFSM <= "0010";
|
967 |
|
|
when x"EC" => -- JMP oprx8,X
|
968 |
|
|
regPC <= (x"00" & datain) + (x"00" & regX);
|
969 |
|
|
mainFSM <= "0010";
|
970 |
|
|
when x"C7" => -- STA opr16a
|
971 |
|
|
wr <= CPUwrite;
|
972 |
|
|
flagN <= regA(7);
|
973 |
|
|
if regA = x"00" then
|
974 |
|
|
flagZ <= '1';
|
975 |
|
|
else
|
976 |
|
|
flagZ <= '0';
|
977 |
|
|
end if;
|
978 |
|
|
dataMux <= outA;
|
979 |
|
|
temp(7 downto 0) <= datain;
|
980 |
|
|
addrMux <= addrTM;
|
981 |
|
|
regPC <= regPC + 1;
|
982 |
|
|
mainFSM <= "0101";
|
983 |
|
|
when x"D7" => -- STA oprx16,X
|
984 |
|
|
wr <= CPUwrite;
|
985 |
|
|
flagN <= regA(7);
|
986 |
|
|
if regA = x"00" then
|
987 |
|
|
flagZ <= '1';
|
988 |
|
|
else
|
989 |
|
|
flagZ <= '0';
|
990 |
|
|
end if;
|
991 |
|
|
dataMux <= outA;
|
992 |
|
|
temp(7 downto 0) <= datain;
|
993 |
|
|
addrMux <= addrX2;
|
994 |
|
|
regPC <= regPC + 1;
|
995 |
|
|
mainFSM <= "0101";
|
996 |
|
|
when x"E7" => -- STA oprx8,X
|
997 |
|
|
wr <= CPUwrite;
|
998 |
|
|
flagN <= regA(7);
|
999 |
|
|
if regA = x"00" then
|
1000 |
|
|
flagZ <= '1';
|
1001 |
|
|
else
|
1002 |
|
|
flagZ <= '0';
|
1003 |
|
|
end if;
|
1004 |
|
|
dataMux <= outA;
|
1005 |
|
|
temp(7 downto 0) <= datain;
|
1006 |
|
|
addrMux <= addrX1;
|
1007 |
|
|
regPC <= regPC + 1;
|
1008 |
|
|
mainFSM <= "0101";
|
1009 |
|
|
when x"CF" => -- STX opr16a
|
1010 |
|
|
wr <= CPUwrite;
|
1011 |
|
|
flagN <= regX(7);
|
1012 |
|
|
if regX = x"00" then
|
1013 |
|
|
flagZ <= '1';
|
1014 |
|
|
else
|
1015 |
|
|
flagZ <= '0';
|
1016 |
|
|
end if;
|
1017 |
|
|
dataMux <= outX;
|
1018 |
|
|
temp(7 downto 0) <= datain;
|
1019 |
|
|
addrMux <= addrTM;
|
1020 |
|
|
regPC <= regPC + 1;
|
1021 |
|
|
mainFSM <= "0101";
|
1022 |
|
|
when x"DF" => -- STX oprx16,X
|
1023 |
|
|
wr <= CPUwrite;
|
1024 |
|
|
flagN <= regX(7);
|
1025 |
|
|
if regX = x"00" then
|
1026 |
|
|
flagZ <= '1';
|
1027 |
|
|
else
|
1028 |
|
|
flagZ <= '0';
|
1029 |
|
|
end if;
|
1030 |
|
|
dataMux <= outX;
|
1031 |
|
|
temp(7 downto 0) <= datain;
|
1032 |
|
|
addrMux <= addrX2;
|
1033 |
|
|
regPC <= regPC + 1;
|
1034 |
|
|
mainFSM <= "0101";
|
1035 |
|
|
when x"EF" => -- STX oprx8,X
|
1036 |
|
|
wr <= CPUwrite;
|
1037 |
|
|
flagN <= regX(7);
|
1038 |
|
|
if regX = x"00" then
|
1039 |
|
|
flagZ <= '1';
|
1040 |
|
|
else
|
1041 |
|
|
flagZ <= '0';
|
1042 |
|
|
end if;
|
1043 |
|
|
dataMux <= outX;
|
1044 |
|
|
temp(7 downto 0) <= datain;
|
1045 |
|
|
addrMux <= addrX1;
|
1046 |
|
|
regPC <= regPC + 1;
|
1047 |
|
|
mainFSM <= "0101";
|
1048 |
|
|
when x"30" | x"60" | x"70" => -- NEG opr8a, NEG oprx8,X, NEG ,X
|
1049 |
|
|
wr <= CPUwrite;
|
1050 |
|
|
dataMux <= outHelp;
|
1051 |
|
|
help <= x"00" - datain;
|
1052 |
|
|
tres := x"00" - datain;
|
1053 |
|
|
flagN <= tres(7);
|
1054 |
|
|
if tres = x"00" then
|
1055 |
|
|
flagZ <= '1';
|
1056 |
|
|
flagC <= '0';
|
1057 |
|
|
else
|
1058 |
|
|
flagC <= '1';
|
1059 |
|
|
flagZ <= '0';
|
1060 |
|
|
end if;
|
1061 |
|
|
mainFSM <= "0101";
|
1062 |
|
|
when x"33" | x"63" | x"73" => -- COM opr8a, COM oprx8,X, COM ,X
|
1063 |
|
|
wr <= CPUwrite;
|
1064 |
|
|
dataMux <= outHelp;
|
1065 |
|
|
help <= datain xor x"FF";
|
1066 |
|
|
tres := datain xor x"FF";
|
1067 |
|
|
flagC <= '1';
|
1068 |
|
|
flagN <= tres(7);
|
1069 |
|
|
if tres = x"00" then
|
1070 |
|
|
flagZ <= '1';
|
1071 |
|
|
else
|
1072 |
|
|
flagZ <= '0';
|
1073 |
|
|
end if;
|
1074 |
|
|
mainFSM <= "0101";
|
1075 |
|
|
when x"34" | x"64" | x"74" => -- LSR opr8a, LSR oprx8,X, LSR ,X
|
1076 |
|
|
wr <= CPUwrite;
|
1077 |
|
|
dataMux <= outHelp;
|
1078 |
|
|
help <= "0" & datain(7 downto 1);
|
1079 |
|
|
tres := "0" & datain(7 downto 1);
|
1080 |
|
|
flagN <= '0';
|
1081 |
|
|
flagC <= datain(0);
|
1082 |
|
|
if tres = x"00" then
|
1083 |
|
|
flagZ <= '1';
|
1084 |
|
|
else
|
1085 |
|
|
flagZ <= '0';
|
1086 |
|
|
end if;
|
1087 |
|
|
mainFSM <= "0101";
|
1088 |
|
|
when x"36" | x"66" | x"76" => -- ROR opr8a, ROR oprx8,X, ROR ,X
|
1089 |
|
|
wr <= CPUwrite;
|
1090 |
|
|
dataMux <= outHelp;
|
1091 |
|
|
help <= flagC & datain(7 downto 1);
|
1092 |
|
|
tres := flagC & datain(7 downto 1);
|
1093 |
|
|
flagN <= flagC;
|
1094 |
|
|
flagC <= datain(0);
|
1095 |
|
|
if tres = x"00" then
|
1096 |
|
|
flagZ <= '1';
|
1097 |
|
|
else
|
1098 |
|
|
flagZ <= '0';
|
1099 |
|
|
end if;
|
1100 |
|
|
mainFSM <= "0101";
|
1101 |
|
|
when x"37" | x"67" | x"77" => -- ASR opr8a, ASR oprx8,X, ASR ,X
|
1102 |
|
|
wr <= CPUwrite;
|
1103 |
|
|
dataMux <= outHelp;
|
1104 |
|
|
help <= datain(7) & datain(7 downto 1);
|
1105 |
|
|
tres := datain(7) & datain(7 downto 1);
|
1106 |
|
|
flagN <= datain(7);
|
1107 |
|
|
flagC <= datain(0);
|
1108 |
|
|
if tres = x"00" then
|
1109 |
|
|
flagZ <= '1';
|
1110 |
|
|
else
|
1111 |
|
|
flagZ <= '0';
|
1112 |
|
|
end if;
|
1113 |
|
|
mainFSM <= "0101";
|
1114 |
|
|
when x"38" | x"68" | x"78" => -- LSL opr8a, LSL oprx8,X, LSL ,X
|
1115 |
|
|
wr <= CPUwrite;
|
1116 |
|
|
dataMux <= outHelp;
|
1117 |
|
|
help <= datain(6 downto 0) & "0";
|
1118 |
|
|
tres := datain(6 downto 0) & "0";
|
1119 |
|
|
flagN <= datain(6);
|
1120 |
|
|
flagC <= datain(7);
|
1121 |
|
|
if tres = x"00" then
|
1122 |
|
|
flagZ <= '1';
|
1123 |
|
|
else
|
1124 |
|
|
flagZ <= '0';
|
1125 |
|
|
end if;
|
1126 |
|
|
mainFSM <= "0101";
|
1127 |
|
|
when x"39" | x"69" | x"79" => -- ROL opr8a, ROL oprx8,X, ROL ,X
|
1128 |
|
|
wr <= CPUwrite;
|
1129 |
|
|
dataMux <= outHelp;
|
1130 |
|
|
help <= datain(6 downto 0) & flagC;
|
1131 |
|
|
tres := datain(6 downto 0) & flagC;
|
1132 |
|
|
flagN <= datain(6);
|
1133 |
|
|
flagC <= datain(7);
|
1134 |
|
|
if tres = x"00" then
|
1135 |
|
|
flagZ <= '1';
|
1136 |
|
|
else
|
1137 |
|
|
flagZ <= '0';
|
1138 |
|
|
end if;
|
1139 |
|
|
mainFSM <= "0101";
|
1140 |
|
|
when x"3A" | x"6A" | x"7A" => -- DEC opr8a, DEC oprx8,X, DEC ,X
|
1141 |
|
|
wr <= CPUwrite;
|
1142 |
|
|
dataMux <= outHelp;
|
1143 |
|
|
help <= datain - 1;
|
1144 |
|
|
tres := datain - 1;
|
1145 |
|
|
flagN <= tres(7);
|
1146 |
|
|
if tres = x"00" then
|
1147 |
|
|
flagZ <= '1';
|
1148 |
|
|
else
|
1149 |
|
|
flagZ <= '0';
|
1150 |
|
|
end if;
|
1151 |
|
|
mainFSM <= "0101";
|
1152 |
|
|
when x"3C" | x"6C" | x"7C" => -- INC opr8a, INC oprx8,X, INC ,X
|
1153 |
|
|
wr <= CPUwrite;
|
1154 |
|
|
dataMux <= outHelp;
|
1155 |
|
|
help <= datain + 1;
|
1156 |
|
|
tres := datain + 1;
|
1157 |
|
|
flagN <= tres(7);
|
1158 |
|
|
if tres = x"00" then
|
1159 |
|
|
flagZ <= '1';
|
1160 |
|
|
else
|
1161 |
|
|
flagZ <= '0';
|
1162 |
|
|
end if;
|
1163 |
|
|
mainFSM <= "0101";
|
1164 |
|
|
when x"3D" | x"6D" | x"7D" => -- TST opr8a, TST oprx8,X, TST ,X
|
1165 |
|
|
flagN <= datain(7);
|
1166 |
|
|
if datain = x"00" then
|
1167 |
|
|
flagZ <= '1';
|
1168 |
|
|
else
|
1169 |
|
|
flagZ <= '0';
|
1170 |
|
|
end if;
|
1171 |
|
|
addrMux <= addrPC;
|
1172 |
|
|
mainFSM <= "0010";
|
1173 |
|
|
when x"3F" | x"6F" => -- CLR opr8a, CLR oprx8,X
|
1174 |
|
|
wr <= CPUread;
|
1175 |
|
|
addrMux <= addrPC;
|
1176 |
|
|
mainFSM <= "0010";
|
1177 |
|
|
when x"80" | x"82" => -- RTI, RTT
|
1178 |
|
|
regA <= datain;
|
1179 |
|
|
regSP <= regSP + 1;
|
1180 |
|
|
mainFSM <= "0101";
|
1181 |
|
|
when x"81" => -- RTS
|
1182 |
|
|
regPC(7 downto 0) <= datain;
|
1183 |
|
|
addrMux <= addrPC;
|
1184 |
|
|
mainFSM <= "0010";
|
1185 |
|
|
when x"83" => -- SWI
|
1186 |
|
|
regSP <= regSP - 1;
|
1187 |
|
|
dataMux <= outPCH;
|
1188 |
|
|
mainFSM <= "0101";
|
1189 |
|
|
when x"AD" | x"BD" | x"ED" => -- BSR rel, JSR opr8a, JSR oprx8,X
|
1190 |
|
|
regSP <= regSP - 1;
|
1191 |
|
|
dataMux <= outPCH;
|
1192 |
|
|
mainFSM <= "0101";
|
1193 |
|
|
when x"FD" => -- JSR ,X
|
1194 |
|
|
regSP <= regSP - 1;
|
1195 |
|
|
dataMux <= outTH;
|
1196 |
|
|
mainFSM <= "0101";
|
1197 |
|
|
when x"CD" | x"DD" => -- JSR opr16a, JSR oprx16,X
|
1198 |
|
|
wr <= CPUwrite;
|
1199 |
|
|
temp(7 downto 0) <= datain;
|
1200 |
|
|
regPC <= regPC + 1;
|
1201 |
|
|
addrMux <= addrSP;
|
1202 |
|
|
dataMux <= outPCL;
|
1203 |
|
|
mainFSM <= "0101";
|
1204 |
|
|
|
1205 |
|
|
when others =>
|
1206 |
|
|
mainFSM <= "0000";
|
1207 |
|
|
end case; -- opcode
|
1208 |
|
|
|
1209 |
|
|
when "0101" => --##################### instruction cycle 4
|
1210 |
|
|
case opcode is
|
1211 |
|
|
when x"00" | x"02" | x"04" | x"06" | x"08" | x"0A" | x"0C" | x"0E" | -- BRSET n,opr8a,rel
|
1212 |
|
|
x"01" | x"03" | x"05" | x"07" | x"09" | x"0B" | x"0D" | x"0F" => -- BRCLR n,opr8a,rel
|
1213 |
|
|
if (opcode(0) xor flagC) = '1' then
|
1214 |
|
|
if datain(7) = '0' then
|
1215 |
|
|
regPC <= regPC + (x"00" & datain) + x"0001";
|
1216 |
|
|
else
|
1217 |
|
|
regPC <= regPC + (x"FF" & datain) + x"0001";
|
1218 |
|
|
end if;
|
1219 |
|
|
else
|
1220 |
|
|
regPC <= regPC + 1;
|
1221 |
|
|
end if;
|
1222 |
|
|
addrMux <= addrPC;
|
1223 |
|
|
mainFSM <= "0010";
|
1224 |
|
|
when x"10" | x"12" | x"14" | x"16" | x"18" | x"1A" | x"1C" | x"1E" | -- BSET n,opr8a
|
1225 |
|
|
x"11" | x"13" | x"15" | x"17" | x"19" | x"1B" | x"1D" | x"1F" | -- BCLR n,opr8a
|
1226 |
|
|
x"30" | x"33" | x"34" | x"36" | -- NEG opr8a, COM opr8a, LSR opr8a, ROR opr8a
|
1227 |
|
|
x"37" | x"38" | x"39" | x"3A" | x"3C" | -- ASR opr8a, LSL opr8a, ROL opr8a, DEC opr8a, INC opr8a
|
1228 |
|
|
x"60" | x"63" | x"64" | x"66" | x"67" | -- NEG oprx8,X, COM oprx8,X, LSR oprx8,X, ROR oprx8,X, ASR oprx8,X
|
1229 |
|
|
x"68" | x"69" | x"6A" | x"6C" | -- LSL oprx8,X, ROL oprx8,X, DEC oprx8,X, INC oprx8,X
|
1230 |
|
|
x"70" | x"73" | x"74" | x"76" | x"77" | x"78" | x"79" | -- NEG ,X, COM ,X, LSR ,X, ROR ,X, ASR ,X, LSL ,X, ROL ,X
|
1231 |
|
|
x"7A" | x"7C" | -- DEC ,X, INC ,X
|
1232 |
|
|
x"B7" | x"BF" | x"C7" | x"CF" | -- STA opr8a, STX opr8a, STA opr16a, STX opr16a
|
1233 |
|
|
x"D7" | x"DF" | x"E7" | x"EF" | -- STA oprx16,X, STX oprx16,X, STA oprx8,X, STX oprx8,X
|
1234 |
|
|
x"F7" | x"FF" => -- STA ,X, STX ,X
|
1235 |
|
|
wr <= CPUread;
|
1236 |
|
|
addrMux <= addrPC;
|
1237 |
|
|
mainFSM <= "0010";
|
1238 |
|
|
when x"80" | x"82" => -- RTI, RTT
|
1239 |
|
|
regX <= datain;
|
1240 |
|
|
regSP <= regSP + 1;
|
1241 |
|
|
mainFSM <= "0110";
|
1242 |
|
|
when x"83" => -- SWI
|
1243 |
|
|
regSP <= regSP - 1;
|
1244 |
|
|
dataMux <= outX;
|
1245 |
|
|
help(7) <= '1';
|
1246 |
|
|
help(6) <= '1';
|
1247 |
|
|
help(5) <= '1';
|
1248 |
|
|
help(4) <= flagH;
|
1249 |
|
|
help(3) <= flagI;
|
1250 |
|
|
help(2) <= flagN;
|
1251 |
|
|
help(1) <= flagZ;
|
1252 |
|
|
help(0) <= flagC;
|
1253 |
|
|
mainFSM <= "0110";
|
1254 |
|
|
when x"A0" | x"B0" | x"C0" | x"D0" | x"E0" | x"F0" => -- SUB #opr8i, SUB opr8a, SUB opr16a, SUB oprx16,X, SUB oprx8,X, SUB ,X
|
1255 |
|
|
addrMux <= addrPC;
|
1256 |
|
|
regA <= regA - datain;
|
1257 |
|
|
tres := regA - datain;
|
1258 |
|
|
flagN <= tres(7);
|
1259 |
|
|
if tres = x"00" then
|
1260 |
|
|
flagZ <= '1';
|
1261 |
|
|
else
|
1262 |
|
|
flagZ <= '0';
|
1263 |
|
|
end if;
|
1264 |
|
|
flagC <= ((not regA(7)) and datain(7)) or
|
1265 |
|
|
(datain(7) and tres(7)) or
|
1266 |
|
|
(tres(7) and (not regA(7)));
|
1267 |
|
|
if opcode = x"A0" then
|
1268 |
|
|
regPC <= regPC + 1;
|
1269 |
|
|
end if;
|
1270 |
|
|
mainFSM <= "0010";
|
1271 |
|
|
when x"A1" | x"B1" | x"C1" | x"D1" | x"E1" | x"F1" => -- CMP #opr8i, CMP opr8a, CMP opr16a, CMP oprx16,X, CMP oprx8,X, CMP ,X
|
1272 |
|
|
addrMux <= addrPC;
|
1273 |
|
|
tres := regA - datain;
|
1274 |
|
|
flagN <= tres(7);
|
1275 |
|
|
if tres = x"00" then
|
1276 |
|
|
flagZ <= '1';
|
1277 |
|
|
else
|
1278 |
|
|
flagZ <= '0';
|
1279 |
|
|
end if;
|
1280 |
|
|
flagC <= ((not regA(7)) and datain(7)) or
|
1281 |
|
|
(datain(7) and tres(7)) or
|
1282 |
|
|
(tres(7) and (not regA(7)));
|
1283 |
|
|
if opcode = x"A1" then
|
1284 |
|
|
regPC <= regPC + 1;
|
1285 |
|
|
end if;
|
1286 |
|
|
mainFSM <= "0010";
|
1287 |
|
|
when x"A2" | x"B2" | x"C2" | x"D2" | x"E2" | x"F2" => -- SBC #opr8i, SBC opr8a, SBC opr16a, SBC oprx16,X, SBC oprx8,X, SBC ,X
|
1288 |
|
|
addrMux <= addrPC;
|
1289 |
|
|
regA <= regA - datain - ("0000000" & flagC);
|
1290 |
|
|
tres := regA - datain - ("0000000" & flagC);
|
1291 |
|
|
flagN <= tres(7);
|
1292 |
|
|
if tres = x"00" then
|
1293 |
|
|
flagZ <= '1';
|
1294 |
|
|
else
|
1295 |
|
|
flagZ <= '0';
|
1296 |
|
|
end if;
|
1297 |
|
|
flagC <= ((not regA(7)) and datain(7)) or
|
1298 |
|
|
(datain(7) and tres(7)) or
|
1299 |
|
|
(tres(7) and (not regA(7)));
|
1300 |
|
|
if opcode = x"A2" then
|
1301 |
|
|
regPC <= regPC + 1;
|
1302 |
|
|
end if;
|
1303 |
|
|
mainFSM <= "0010";
|
1304 |
|
|
when x"A3" | x"B3" | x"C3" | x"D3" | x"E3" | x"F3" => -- CPX #opr8i, CPX opr8a, CPX opr16a, CPX oprx16,X, CPX oprx8,X, CPX ,X
|
1305 |
|
|
addrMux <= addrPC;
|
1306 |
|
|
tres := regX - datain;
|
1307 |
|
|
flagN <= tres(7);
|
1308 |
|
|
if tres = x"00" then
|
1309 |
|
|
flagZ <= '1';
|
1310 |
|
|
else
|
1311 |
|
|
flagZ <= '0';
|
1312 |
|
|
end if;
|
1313 |
|
|
flagC <= ((not regX(7)) and datain(7)) or
|
1314 |
|
|
(datain(7) and tres(7)) or
|
1315 |
|
|
(tres(7) and (not regX(7)));
|
1316 |
|
|
if opcode = x"A3" then
|
1317 |
|
|
regPC <= regPC + 1;
|
1318 |
|
|
end if;
|
1319 |
|
|
mainFSM <= "0010";
|
1320 |
|
|
when x"A4" | x"B4" | x"C4" | x"D4" | x"E4" | x"F4" => -- AND #opr8i, AND opr8a, AND opr16a, AND oprx16,X, AND oprx8,X, AND ,X
|
1321 |
|
|
addrMux <= addrPC;
|
1322 |
|
|
regA <= regA and datain;
|
1323 |
|
|
tres := regA and datain;
|
1324 |
|
|
flagN <= tres(7);
|
1325 |
|
|
if tres = x"00" then
|
1326 |
|
|
flagZ <= '1';
|
1327 |
|
|
else
|
1328 |
|
|
flagZ <= '0';
|
1329 |
|
|
end if;
|
1330 |
|
|
if opcode = x"A4" then
|
1331 |
|
|
regPC <= regPC + 1;
|
1332 |
|
|
end if;
|
1333 |
|
|
mainFSM <= "0010";
|
1334 |
|
|
when x"A5" | x"B5" | x"C5" | x"D5" | x"E5" | x"F5" => -- BIT #opr8i, BIT opr8a, BIT opr16a, BIT oprx16,X, BIT oprx8,X, BIT ,X
|
1335 |
|
|
addrMux <= addrPC;
|
1336 |
|
|
tres := regA and datain;
|
1337 |
|
|
flagN <= tres(7);
|
1338 |
|
|
if tres = x"00" then
|
1339 |
|
|
flagZ <= '1';
|
1340 |
|
|
else
|
1341 |
|
|
flagZ <= '0';
|
1342 |
|
|
end if;
|
1343 |
|
|
if opcode = x"A5" then
|
1344 |
|
|
regPC <= regPC + 1;
|
1345 |
|
|
end if;
|
1346 |
|
|
mainFSM <= "0010";
|
1347 |
|
|
when x"A6" | x"B6" | x"C6" | x"D6" | x"E6" | x"F6" => -- LDA #opr8i, LDA opr8a, LDA opr16a, LDA oprx16,X, LDA oprx8,X, LDA ,X
|
1348 |
|
|
addrMux <= addrPC;
|
1349 |
|
|
regA <= datain;
|
1350 |
|
|
flagN <= datain(7);
|
1351 |
|
|
if datain = x"00" then
|
1352 |
|
|
flagZ <= '1';
|
1353 |
|
|
else
|
1354 |
|
|
flagZ <= '0';
|
1355 |
|
|
end if;
|
1356 |
|
|
if opcode = x"A6" then
|
1357 |
|
|
regPC <= regPC + 1;
|
1358 |
|
|
end if;
|
1359 |
|
|
mainFSM <= "0010";
|
1360 |
|
|
when x"A8" | x"B8" | x"C8" | x"D8" | x"E8" | x"F8" => -- EOR #opr8i, EOR opr8a, EOR opr16a, EOR oprx16,X, EOR oprx8,X, EOR ,X
|
1361 |
|
|
addrMux <= addrPC;
|
1362 |
|
|
regA <= regA xor datain;
|
1363 |
|
|
tres := regA xor datain;
|
1364 |
|
|
flagN <= tres(7);
|
1365 |
|
|
if tres = x"00" then
|
1366 |
|
|
flagZ <= '1';
|
1367 |
|
|
else
|
1368 |
|
|
flagZ <= '0';
|
1369 |
|
|
end if;
|
1370 |
|
|
if opcode = x"A8" then
|
1371 |
|
|
regPC <= regPC + 1;
|
1372 |
|
|
end if;
|
1373 |
|
|
mainFSM <= "0010";
|
1374 |
|
|
when x"A9" | x"B9" | x"C9" | x"D9" | x"E9" | x"F9" => -- ADC #opr8i, ADC opr8a, ADC opr16a, ADC oprx16,X, ADC oprx8,X, ADC ,X
|
1375 |
|
|
addrMux <= addrPC;
|
1376 |
|
|
regA <= regA + datain + ("0000000" & flagC);
|
1377 |
|
|
tres := regA + datain + ("0000000" & flagC);
|
1378 |
|
|
flagN <= tres(7);
|
1379 |
|
|
if tres = x"00" then
|
1380 |
|
|
flagZ <= '1';
|
1381 |
|
|
else
|
1382 |
|
|
flagZ <= '0';
|
1383 |
|
|
end if;
|
1384 |
|
|
flagH <= (regA(3) and datain(3)) or
|
1385 |
|
|
(datain(3) and (not tres(3))) or
|
1386 |
|
|
((not tres(3)) and regA(3));
|
1387 |
|
|
flagC <= (regA(7) and datain(7)) or
|
1388 |
|
|
(datain(7) and (not tres(7))) or
|
1389 |
|
|
((not tres(7)) and regA(7));
|
1390 |
|
|
if opcode = x"A9" then
|
1391 |
|
|
regPC <= regPC + 1;
|
1392 |
|
|
end if;
|
1393 |
|
|
mainFSM <= "0010";
|
1394 |
|
|
when x"AA" | x"BA" | x"CA" | x"DA" | x"EA" | x"FA" => -- ORA #opr8i, ORA opr8a, ORA opr16a, ORA oprx16,X, ORA oprx8,X, ORA ,X
|
1395 |
|
|
addrMux <= addrPC;
|
1396 |
|
|
regA <= regA or datain;
|
1397 |
|
|
tres := regA or datain;
|
1398 |
|
|
flagN <= tres(7);
|
1399 |
|
|
if tres = x"00" then
|
1400 |
|
|
flagZ <= '1';
|
1401 |
|
|
else
|
1402 |
|
|
flagZ <= '0';
|
1403 |
|
|
end if;
|
1404 |
|
|
if opcode = x"AA" then
|
1405 |
|
|
regPC <= regPC + 1;
|
1406 |
|
|
end if;
|
1407 |
|
|
mainFSM <= "0010";
|
1408 |
|
|
when x"AB" | x"BB" | x"CB" | x"DB" | x"EB" | x"FB" => -- ADD #opr8i, ADD opr8a, ADD opr16a, ADD oprx16,X, ADD oprx8,X, ADD ,X
|
1409 |
|
|
addrMux <= addrPC;
|
1410 |
|
|
regA <= regA + datain;
|
1411 |
|
|
tres := regA + datain;
|
1412 |
|
|
flagN <= tres(7);
|
1413 |
|
|
if tres = x"00" then
|
1414 |
|
|
flagZ <= '1';
|
1415 |
|
|
else
|
1416 |
|
|
flagZ <= '0';
|
1417 |
|
|
end if;
|
1418 |
|
|
flagH <= (regA(3) and datain(3)) or
|
1419 |
|
|
(datain(3) and (not tres(3))) or
|
1420 |
|
|
((not tres(3)) and regA(3));
|
1421 |
|
|
flagC <= (regA(7) and datain(7)) or
|
1422 |
|
|
(datain(7) and (not tres(7))) or
|
1423 |
|
|
((not tres(7)) and regA(7));
|
1424 |
|
|
if opcode = x"AB" then
|
1425 |
|
|
regPC <= regPC + 1;
|
1426 |
|
|
end if;
|
1427 |
|
|
mainFSM <= "0010";
|
1428 |
|
|
when x"AE" | x"BE" | x"CE" | x"DE" | x"EE" | x"FE" => -- LDX #opr8i, LDX opr8a, LDX opr16a, LDX oprx16,X, LDX oprx8,X, LDX ,X
|
1429 |
|
|
addrMux <= addrPC;
|
1430 |
|
|
regX <= datain;
|
1431 |
|
|
flagN <= datain(7);
|
1432 |
|
|
if datain = x"00" then
|
1433 |
|
|
flagZ <= '1';
|
1434 |
|
|
else
|
1435 |
|
|
flagZ <= '0';
|
1436 |
|
|
end if;
|
1437 |
|
|
if opcode = x"AE" then
|
1438 |
|
|
regPC <= regPC + 1;
|
1439 |
|
|
end if;
|
1440 |
|
|
mainFSM <= "0010";
|
1441 |
|
|
when x"AD" => -- BSR rel
|
1442 |
|
|
wr <= CPUread;
|
1443 |
|
|
addrMux <= addrPC;
|
1444 |
|
|
if help(7) = '0' then
|
1445 |
|
|
regPC <= regPC + (x"00" & help);
|
1446 |
|
|
else
|
1447 |
|
|
regPC <= regPC + (x"FF" & help);
|
1448 |
|
|
end if;
|
1449 |
|
|
regSP <= regSP - 1;
|
1450 |
|
|
mainFSM <= "0010";
|
1451 |
|
|
when x"BD" => -- JSR opr8a
|
1452 |
|
|
wr <= CPUread;
|
1453 |
|
|
addrMux <= addrPC;
|
1454 |
|
|
regPC <= x"00" & help;
|
1455 |
|
|
regSP <= regSP - 1;
|
1456 |
|
|
mainFSM <= "0010";
|
1457 |
|
|
when x"CD" | x"DD" => -- JSR opr16a, JSR oprx16,X
|
1458 |
|
|
regSP <= regSP - 1;
|
1459 |
|
|
dataMux <= outPCH;
|
1460 |
|
|
mainFSM <= "0110";
|
1461 |
|
|
when x"ED" => -- JSR oprx8,X
|
1462 |
|
|
wr <= CPUread;
|
1463 |
|
|
addrMux <= addrPC;
|
1464 |
|
|
regPC <= (x"00" & help) + (x"00" & regX);
|
1465 |
|
|
regSP <= regSP - 1;
|
1466 |
|
|
mainFSM <= "0010";
|
1467 |
|
|
when x"FD" => -- JSR ,X
|
1468 |
|
|
wr <= CPUread;
|
1469 |
|
|
addrMux <= addrPC;
|
1470 |
|
|
regPC <= (x"00" & regX);
|
1471 |
|
|
regSP <= regSP - 1;
|
1472 |
|
|
mainFSM <= "0010";
|
1473 |
|
|
|
1474 |
|
|
when others =>
|
1475 |
|
|
mainFSM <= "0000";
|
1476 |
|
|
end case; -- opcode
|
1477 |
|
|
|
1478 |
|
|
when "0110" => --##################### instruction cycle 5
|
1479 |
|
|
case opcode is
|
1480 |
|
|
when x"80" | x"82" => -- RTI, RTT
|
1481 |
|
|
regPC(15 downto 8) <= datain;
|
1482 |
|
|
regSP <= regSP + 1;
|
1483 |
|
|
mainFSM <= "0111";
|
1484 |
|
|
when x"83" => -- SWI
|
1485 |
|
|
regSP <= regSP - 1;
|
1486 |
|
|
dataMux <= outA;
|
1487 |
|
|
mainFSM <= "0111";
|
1488 |
|
|
when x"CD" => -- JSR opr16a
|
1489 |
|
|
wr <= CPUread;
|
1490 |
|
|
addrMUX <= addrPC;
|
1491 |
|
|
regSP <= regSP - 1;
|
1492 |
|
|
regPC <= temp;
|
1493 |
|
|
mainFSM <= "0010";
|
1494 |
|
|
when x"DD" => -- JSR oprx16,X
|
1495 |
|
|
wr <= CPUread;
|
1496 |
|
|
addrMUX <= addrPC;
|
1497 |
|
|
regSP <= regSP - 1;
|
1498 |
|
|
regPC <= temp + (x"00" & regX);
|
1499 |
|
|
mainFSM <= "0010";
|
1500 |
|
|
|
1501 |
|
|
when others =>
|
1502 |
|
|
mainFSM <= "0000";
|
1503 |
|
|
end case; -- opcode
|
1504 |
|
|
|
1505 |
|
|
when "0111" => --##################### instruction cycle 6
|
1506 |
|
|
case opcode is
|
1507 |
|
|
when x"80" | x"82" => -- RTI, RTT
|
1508 |
|
|
regPC(7 downto 0) <= datain;
|
1509 |
|
|
addrMux <= addrPC;
|
1510 |
|
|
mainFSM <= "0010";
|
1511 |
|
|
when x"83" => -- SWI
|
1512 |
|
|
regSP <= regSP - 1;
|
1513 |
|
|
dataMux <= outHelp;
|
1514 |
|
|
flagI <= '1';
|
1515 |
|
|
if trace = '0' then
|
1516 |
|
|
if irqRequest = '0' then
|
1517 |
|
|
temp <= x"FFFC"; -- SWI vector
|
1518 |
|
|
else
|
1519 |
|
|
irqRequest <= '0';
|
1520 |
|
|
temp <= x"FFFA"; -- IRQ vector
|
1521 |
|
|
end if;
|
1522 |
|
|
mainFSM <= "1000";
|
1523 |
|
|
else
|
1524 |
|
|
temp <= x"FFF8"; -- trace vector
|
1525 |
|
|
mainFSM <= "1011";
|
1526 |
|
|
end if;
|
1527 |
|
|
|
1528 |
|
|
when others =>
|
1529 |
|
|
mainFSM <= "0000";
|
1530 |
|
|
end case; -- opcode
|
1531 |
|
|
when "1000" => --##################### instruction cycle 7
|
1532 |
|
|
case opcode is
|
1533 |
|
|
when x"83" => -- SWI
|
1534 |
|
|
wr <= CPUread;
|
1535 |
|
|
addrMux <= addrTM;
|
1536 |
|
|
regSP <= regSP - 1;
|
1537 |
|
|
mainFSM <= "1001";
|
1538 |
|
|
|
1539 |
|
|
when others =>
|
1540 |
|
|
mainFSM <= "0000";
|
1541 |
|
|
end case;
|
1542 |
|
|
when "1001" => --##################### instruction cycle 8
|
1543 |
|
|
case opcode is
|
1544 |
|
|
when x"83" => -- SWI
|
1545 |
|
|
regPC(15 downto 8) <= datain;
|
1546 |
|
|
temp <= temp + 1;
|
1547 |
|
|
mainFSM <= "1010";
|
1548 |
|
|
|
1549 |
|
|
when others =>
|
1550 |
|
|
mainFSM <= "0000";
|
1551 |
|
|
end case;
|
1552 |
|
|
when "1010" => --##################### instruction cycle 9
|
1553 |
|
|
case opcode is
|
1554 |
|
|
when x"83" => -- SWI
|
1555 |
|
|
regPC(7 downto 0) <= datain;
|
1556 |
|
|
addrMux <= addrPC;
|
1557 |
|
|
mainFSM <= "0010";
|
1558 |
|
|
|
1559 |
|
|
when others =>
|
1560 |
|
|
mainFSM <= "0000";
|
1561 |
|
|
end case;
|
1562 |
|
|
when "1011" => --##################### instruction cycle 6a, trace
|
1563 |
|
|
regSP <= regSP - 1;
|
1564 |
|
|
dataMux <= outCode;
|
1565 |
|
|
trace <= '0';
|
1566 |
|
|
trace_i <= '0';
|
1567 |
|
|
mainFSM <= "1000";
|
1568 |
|
|
|
1569 |
|
|
when others =>
|
1570 |
|
|
mainFSM <= "0000";
|
1571 |
|
|
end case; -- mainFSM
|
1572 |
|
|
end if;
|
1573 |
|
|
end if;
|
1574 |
|
|
end process;
|
1575 |
|
|
|
1576 |
|
|
end behavior;
|