URL https://opencores.org/ocsvn/8051/8051/trunk

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[/] [8051/] [tags/] [rel0/] [asm/] [hex/] [serial_test.hex] - Blame information for rev 186

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1	2	simont	`8C`
2			`FD`
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165
166			`///`
167			`/// created by oc8051 rom maker`
168			`/// author: Simon Teran (simont@opencores.org)`
169			`///`
170			`/// source file: D:\tmp\asm\TEMP\interrupt_test.hex`
171			`/// date: 16.7.02`
172
173			`///`
174
175			`module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);`
176
177			`parameter INT_ROM_WID= 9;`
178
179			`input rst, clk;`
180			`input [15:0] addr;`
181			`output ea_int;`
182			`output [7:0] data1, data2, data3;`
183			`reg [7:0] data1, data2, data3;`
184
185			`integer i;`
186
187			`wire ea;`
188
189
190			`assign ea_int = ! ea;`

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[/] [8051/] [tags/] [rel0/] [asm/] [hex/] [serial_test.hex] - Blame information for rev 186