OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel0/] [syn/] [src/] [verilog/] [disp.v] - Blame information for rev 186

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 simont
//
2
// decoder for 7 led display
3
//
4
 
5
module disp (in, out);
6
 
7
input [7:0] in;
8
output [13:0] out;
9
 
10
reg [13:0] out;
11
 
12
always @(in)
13
begin
14
  case (in[7:4])
15
    4'h0: out[13:7] = 7'b1110111;
16
    4'h1: out[13:7] = 7'b0100100;
17
    4'h2: out[13:7] = 7'b1011101;
18
    4'h3: out[13:7] = 7'b1101101;
19
    4'h4: out[13:7] = 7'b0101110;
20
    4'h5: out[13:7] = 7'b1101011;
21
    4'h6: out[13:7] = 7'b1111011;
22
    4'h7: out[13:7] = 7'b0100111;
23
    4'h8: out[13:7] = 7'b1111111;
24
    4'h9: out[13:7] = 7'b1101111;
25
    4'ha: out[13:7] = 7'b0111111;
26
    4'hb: out[13:7] = 7'b1111010;
27
    4'hc: out[13:7] = 7'b1010011;
28
    4'hd: out[13:7] = 7'b1111100;
29
    4'he: out[13:7] = 7'b1011011;
30
    4'hf: out[13:7] = 7'b0011011;
31
    default: out[13:7] = 7'b0000000;
32
  endcase
33
 
34
  case (in[3:0])
35
    4'h0: out[6:0] = 7'b1110111;
36
    4'h1: out[6:0] = 7'b0100100;
37
    4'h2: out[6:0] = 7'b1011101;
38
    4'h3: out[6:0] = 7'b1101101;
39
    4'h4: out[6:0] = 7'b0101110;
40
    4'h5: out[6:0] = 7'b1101011;
41
    4'h6: out[6:0] = 7'b1111011;
42
    4'h7: out[6:0] = 7'b0100111;
43
    4'h8: out[6:0] = 7'b1111111;
44
    4'h9: out[6:0] = 7'b1101111;
45
    4'ha: out[6:0] = 7'b0111111;
46
    4'hb: out[6:0] = 7'b1111010;
47
    4'hc: out[6:0] = 7'b1010011;
48
    4'hd: out[6:0] = 7'b1111100;
49
    4'he: out[6:0] = 7'b1011011;
50
    4'hf: out[6:0] = 7'b0011011;
51
    default: out[6:0] = 7'b0000000;
52
  endcase
53
end
54
 
55
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.