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[/] [8051/] [tags/] [rel_1/] [asm/] [counter_test.asm] - Blame information for rev 186

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; r0: counter 0 owerflov counter
; r1: counter 1 owerflov counter
; r2: error code
; r3: counter high expected value
; r4: counter low expected value
; r5: owerflov counter expected value
 
        ajmp start;
 
        org 03h         ;external interrupt 0
        reti;
 
        org 0bh         ;t/c 0 interrupt
        inc r0;
        reti;
 
        org 13h         ;external interrupt 1
        reti;
 
        org 1bh         ;t/c 1 interrupt
        inc r1;
        reti;
 
        org 23h         ;serial interface interrupt
        reti;
 
 
test0:
        mov a, th0      ;
        subb a, r3      ;
        jnz error       ;
        inc r2          ;
        mov a,tl0       ;
        subb a, r4      ;
        jnz error       ;
        inc r2          ;
        mov a, r0       ;
        subb a, r5      ;
        jnz error       ;
        ret;
 
test1:
        mov a, th1      ;
        subb a, r3      ;
        jnz error       ;
        inc r2          ;
        mov a,tl1       ;
        subb a, r4      ;
        jnz error       ;
        inc r2          ;
        mov a, r1       ;
        subb a, r5      ;
        jnz error       ;
        ret;
 
wait:
        dec a           ; 1
        nop             ; 1
        nop             ; 1
        nop             ; 1
        nop             ; 1
        nop             ; 1
        nop             ; 1
        nop             ; 1
        nop             ; 1
        nop             ; 1
        jnz wait        ; 2
        reti            ; 4
 
 
error:
        mov p0, r2;
        nop;
        ajmp error;
 
 
start:
        clr a;
        mov r0, a;
        mov r1, a;
        mov ie, #08ah   ;enable interrupts
        clr c;
 
;
; timer 0 test
;
; mode 0
;
        mov tmod, #004h ;t/c 0 and t/c 1 in counter mode 0
        mov th0, #000h  ;load counter 0
        mov tl0, #000h  ;
        mov tcon, #010h ;start counter 0;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0
        mov r2, #010h   ;
        mov r3, #000h   ;
        mov r4, #003h   ;
        mov r5, #000h   ;
        acall test0     ;
 
        mov tl0, #01ch  ; load counter 0
        setb tcon.4     ;start counter0
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0
        mov r2, #020h   ;
        mov r3, #001h   ;
        mov r4, #000h   ;
        mov r5, #000h   ;
        acall test0     ;
 
        mov tl0, #01ch  ;
        mov th0, #0ffh  ;
        setb tcon.4     ;start counter 0
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0
        mov r2, #030h   ;
        mov r3, #000h   ;
        mov r4, #001h   ;
        mov r5, #001h   ;
        acall test0     ;
;
; mode 1
;
        mov tmod, #005h ; t/c 0 in mode 1
        mov th0, #000h  ;load counter 0
        mov tl0, #000h  ;
        setb tcon.4     ;start counter 0;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0
        mov r2, #040h   ;
        mov r3, #000h   ;
        mov r4, #004h   ;
        mov r5, #001h   ;
        acall test0     ;
 
        mov tl0, #0fch  ; load counter 0
        setb tcon.4     ;start counter 0;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0;
        mov r2, #050h   ;
        mov r3, #001h   ;
        mov r4, #001h   ;
        mov r5, #001h   ;
        acall test0     ;
 
        mov tl0, #0fch  ;
        mov th0, #0ffh  ;
        setb tcon.4     ;start counter 0
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0
        mov r2, #060h   ;
        mov r3, #000h   ;
        mov r4, #002h   ;
        mov r5, #002h   ;
        acall test0     ;
;
; mode 2
;
        mov tmod, #006h ; t/c 0 in mode 2
        mov th0, #000h  ;load counter 0
        mov tl0, #005h  ;
        setb tcon.4     ;start counter 0;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0
        mov r2, #070h   ;
        mov r3, #000h   ;
        mov r4, #009h   ;
        mov r5, #002h   ;
        acall test0     ;
 
        mov tl0, #0fch  ; load counter 0
        mov th0, #050h  ;
        setb tcon.4     ;start counter 0;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0;
        mov r2, #080h   ;
        mov r3, #050h   ;
        mov r4, #051h   ;
        mov r5, #003h   ;
        acall test0     ;
;
; mode 3
;
        mov tmod, #007h ; t/c 0 in mode 3
        mov th0, #000h  ;load counter 0
        mov tl0, #000h  ;
        setb tcon.4     ;start counter 0;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0
        mov r2, #090h   ;
        mov r3, #000h   ;
        mov r4, #004h   ;
        mov r5, #003h   ;
        acall test0     ;
 
        mov tl0, #0fch  ; load counter 0
        mov th0, #000h  ;
        setb tcon.4     ;start counter 0
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        cpl p3.5;
        clr tcon.4      ;stop counter 0
        mov r2, #0a0h   ;
        mov r3, #000h   ;
        mov r4, #002h   ;
        mov r5, #004h   ;
        acall test0     ;
 
        mov tl0, #000h  ; load counter 0
        mov th0, #000h  ;
        setb tcon.6     ; start counter 1
        mov a, #03h     ;
        acall wait      ;
        nop;
        nop;
        nop;
        nop;
        clr tcon.6      ; stop counter 1
        mov r2, #0b0h   ;
        mov r3, #004h   ;
        mov r4, #000h   ;
        mov r5, #004h   ;
        acall test0     ;
 
        mov tl0, #000h  ; load counter 0
        mov th0, #0fch  ;
        setb tcon.6     ;start counter 1
        mov a, #05h     ;
        acall wait      ;
        nop;
        nop;
        nop;
        nop;
        clr tcon.6      ;stop counter 1
        mov r2, #0c0h   ;
        mov r3, #003h   ;
        mov r4, #000h   ;
        mov r5, #001h   ;
        mov r0, 01h     ;
        acall test0     ;
 
        mov p0, #001h   ; test counter 0 done!
        mov r1, #000h   ;
 
;
; timer 1 test
;
; mode 0
;
        mov tmod, #040h ;t/c 0 and t/c 1 in counter mode 0
        mov th1, #000h  ;load counter 1
        mov tl1, #000h  ;
        mov tcon, #040h ;start counter 1;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #018h   ;
        mov r3, #000h   ;
        mov r4, #004h   ;
        mov r5, #000h   ;
        acall test1     ;
 
        mov tl1, #01ch  ; load counter 1
        setb tcon.6     ;start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #028h   ;
        mov r3, #001h   ;
        mov r4, #001h   ;
        mov r5, #000h   ;
        acall test1     ;
 
        mov tl1, #01ch  ;
        mov th1, #0ffh  ;
        setb tcon.6     ;start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #038h   ;
        mov r3, #000h   ;
        mov r4, #002h   ;
        mov r5, #001h   ;
        acall test1     ;
;
; mode 1
;
        mov tmod, #050h ; t/c 1 in counter 1
        mov th1, #000h  ;load counter 1
        mov tl1, #000h  ;
        setb tcon.6     ;start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #048h   ;
        mov r3, #000h   ;
        mov r4, #004h   ;
        mov r5, #001h   ;
        acall test1     ;
 
        mov tl1, #0fch  ; load counter 1
        setb tcon.6     ; start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #058h   ;
        mov r3, #001h   ;
        mov r4, #001h   ;
        mov r5, #001h   ;
        acall test1     ;
 
        mov tl1, #0fch  ;
        mov th1, #0ffh  ;
        setb tcon.6     ;start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #068h   ;
        mov r3, #000h   ;
        mov r4, #002h   ;
        mov r5, #002h   ;
        acall test1     ;
;
; mode 2
;
        mov tmod, #060h ; t/c 1 in mode 2
        mov th1, #000h  ;load counter 1
        mov tl1, #005h  ;
        setb tcon.6     ;start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #078h   ;
        mov r3, #000h   ;
        mov r4, #009h   ;
        mov r5, #002h   ;
        acall test1     ;
 
        mov tl1, #0fch  ; load counter 1
        mov th1, #050h  ;
        setb tcon.6     ;start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #088h   ;
        mov r3, #050h   ;
        mov r4, #051h   ;
        mov r5, #003h   ;
        acall test1     ;
;
; mode 3
;
        mov tmod, #070h ; t/c 1 in mode 3
        mov th1, #000h  ;load counter 1
        mov tl1, #000h  ;
        setb tcon.6     ;start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #098h   ;
        mov r3, #000h   ;
        mov r4, #000h   ;
        mov r5, #003h   ;
        acall test1     ;
 
        mov tl1, #0fch  ; load counter 1
        mov th1, #0ffh  ;
        setb tcon.6     ;start counter 1
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
 
 
        cpl p3.6;
        cpl p3.6;
        cpl p3.6;
        clr tcon.6      ;stop counter 1
        mov r2, #0a8h   ;
        mov r3, #0ffh   ;
        mov r4, #0fch   ;
        mov r5, #003h   ;
        acall test1     ;
 
        mov p0, #002h   ; test counter 1 done!
 
 
end

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[/] [8051/] [tags/] [rel_1/] [asm/] [counter_test.asm] - Blame information for rev 186

Line No.	Rev	Author	Line
1	131	simont	`; r0: counter 0 owerflov counter`
2			`; r1: counter 1 owerflov counter`
3			`; r2: error code`
4			`; r3: counter high expected value`
5			`; r4: counter low expected value`
6			`; r5: owerflov counter expected value`
7
8			`ajmp start;`
9
10			`org 03h ;external interrupt 0`
11			`reti;`
12
13			`org 0bh ;t/c 0 interrupt`
14			`inc r0;`
15			`reti;`
16
17			`org 13h ;external interrupt 1`
18			`reti;`
19
20			`org 1bh ;t/c 1 interrupt`
21			`inc r1;`
22			`reti;`
23
24			`org 23h ;serial interface interrupt`
25			`reti;`
26
27
28			`test0:`
29			`mov a, th0 ;`
30			`subb a, r3 ;`
31			`jnz error ;`
32			`inc r2 ;`
33			`mov a,tl0 ;`
34			`subb a, r4 ;`
35			`jnz error ;`
36			`inc r2 ;`
37			`mov a, r0 ;`
38			`subb a, r5 ;`
39			`jnz error ;`
40			`ret;`
41
42			`test1:`
43			`mov a, th1 ;`
44			`subb a, r3 ;`
45			`jnz error ;`
46			`inc r2 ;`
47			`mov a,tl1 ;`
48			`subb a, r4 ;`
49			`jnz error ;`
50			`inc r2 ;`
51			`mov a, r1 ;`
52			`subb a, r5 ;`
53			`jnz error ;`
54			`ret;`
55
56			`wait:`
57			`dec a ; 1`
58			`nop ; 1`
59			`nop ; 1`
60			`nop ; 1`
61			`nop ; 1`
62			`nop ; 1`
63			`nop ; 1`
64			`nop ; 1`
65			`nop ; 1`
66			`nop ; 1`
67			`jnz wait ; 2`
68			`reti ; 4`
69
70
71			`error:`
72			`mov p0, r2;`
73			`nop;`
74			`ajmp error;`
75
76
77			`start:`
78			`clr a;`
79			`mov r0, a;`
80			`mov r1, a;`
81			`mov ie, #08ah ;enable interrupts`
82			`clr c;`
83
84			`;`
85			`; timer 0 test`
86			`;`
87			`; mode 0`
88			`;`
89			`mov tmod, #004h ;t/c 0 and t/c 1 in counter mode 0`
90			`mov th0, #000h ;load counter 0`
91			`mov tl0, #000h ;`
92			`mov tcon, #010h ;start counter 0;`
93			`cpl p3.5;`
94			`cpl p3.5;`
95			`cpl p3.5;`
96			`cpl p3.5;`
97			`cpl p3.5;`
98			`cpl p3.5;`
99			`clr tcon.4 ;stop counter 0`
100			`mov r2, #010h ;`
101			`mov r3, #000h ;`
102			`mov r4, #003h ;`
103			`mov r5, #000h ;`
104			`acall test0 ;`
105
106			`mov tl0, #01ch ; load counter 0`
107			`setb tcon.4 ;start counter0`
108			`cpl p3.5;`
109			`cpl p3.5;`
110			`cpl p3.5;`
111			`cpl p3.5;`
112			`cpl p3.5;`
113			`cpl p3.5;`
114			`cpl p3.5;`
115			`cpl p3.5;`
116			`clr tcon.4 ;stop counter 0`
117			`mov r2, #020h ;`
118			`mov r3, #001h ;`
119			`mov r4, #000h ;`
120			`mov r5, #000h ;`
121			`acall test0 ;`
122
123			`mov tl0, #01ch ;`
124			`mov th0, #0ffh ;`
125			`setb tcon.4 ;start counter 0`
126			`cpl p3.5;`
127			`cpl p3.5;`
128			`cpl p3.5;`
129			`cpl p3.5;`
130			`cpl p3.5;`
131			`cpl p3.5;`
132			`cpl p3.5;`
133			`cpl p3.5;`
134			`cpl p3.5;`
135			`cpl p3.5;`
136			`clr tcon.4 ;stop counter 0`
137			`mov r2, #030h ;`
138			`mov r3, #000h ;`
139			`mov r4, #001h ;`
140			`mov r5, #001h ;`
141			`acall test0 ;`
142			`;`
143			`; mode 1`
144			`;`
145			`mov tmod, #005h ; t/c 0 in mode 1`
146			`mov th0, #000h ;load counter 0`
147			`mov tl0, #000h ;`
148			`setb tcon.4 ;start counter 0;`
149			`cpl p3.5;`
150			`cpl p3.5;`
151			`cpl p3.5;`
152			`cpl p3.5;`
153			`cpl p3.5;`
154			`cpl p3.5;`
155			`cpl p3.5;`
156			`cpl p3.5;`
157			`clr tcon.4 ;stop counter 0`
158			`mov r2, #040h ;`
159			`mov r3, #000h ;`
160			`mov r4, #004h ;`
161			`mov r5, #001h ;`
162			`acall test0 ;`
163
164			`mov tl0, #0fch ; load counter 0`
165			`setb tcon.4 ;start counter 0;`
166			`cpl p3.5;`
167			`cpl p3.5;`
168			`cpl p3.5;`
169			`cpl p3.5;`
170			`cpl p3.5;`
171			`cpl p3.5;`
172			`cpl p3.5;`
173			`cpl p3.5;`
174			`cpl p3.5;`
175			`cpl p3.5;`
176			`clr tcon.4 ;stop counter 0;`
177			`mov r2, #050h ;`
178			`mov r3, #001h ;`
179			`mov r4, #001h ;`
180			`mov r5, #001h ;`
181			`acall test0 ;`
182
183			`mov tl0, #0fch ;`
184			`mov th0, #0ffh ;`
185			`setb tcon.4 ;start counter 0`
186			`cpl p3.5;`
187			`cpl p3.5;`
188			`cpl p3.5;`
189			`cpl p3.5;`
190			`cpl p3.5;`
191			`cpl p3.5;`
192			`cpl p3.5;`
193			`cpl p3.5;`
194			`cpl p3.5;`
195			`cpl p3.5;`
196			`cpl p3.5;`
197			`cpl p3.5;`
198			`clr tcon.4 ;stop counter 0`
199			`mov r2, #060h ;`
200			`mov r3, #000h ;`
201			`mov r4, #002h ;`
202			`mov r5, #002h ;`
203			`acall test0 ;`
204			`;`
205			`; mode 2`
206			`;`
207			`mov tmod, #006h ; t/c 0 in mode 2`
208			`mov th0, #000h ;load counter 0`
209			`mov tl0, #005h ;`
210			`setb tcon.4 ;start counter 0;`
211			`cpl p3.5;`
212			`cpl p3.5;`
213			`cpl p3.5;`
214			`cpl p3.5;`
215			`cpl p3.5;`
216			`cpl p3.5;`
217			`cpl p3.5;`
218			`cpl p3.5;`
219			`clr tcon.4 ;stop counter 0`
220			`mov r2, #070h ;`
221			`mov r3, #000h ;`
222			`mov r4, #009h ;`
223			`mov r5, #002h ;`
224			`acall test0 ;`
225
226			`mov tl0, #0fch ; load counter 0`
227			`mov th0, #050h ;`
228			`setb tcon.4 ;start counter 0;`
229			`cpl p3.5;`
230			`cpl p3.5;`
231			`cpl p3.5;`
232			`cpl p3.5;`
233			`cpl p3.5;`
234			`cpl p3.5;`
235			`cpl p3.5;`
236			`cpl p3.5;`
237			`cpl p3.5;`
238			`cpl p3.5;`
239			`clr tcon.4 ;stop counter 0;`
240			`mov r2, #080h ;`
241			`mov r3, #050h ;`
242			`mov r4, #051h ;`
243			`mov r5, #003h ;`
244			`acall test0 ;`
245			`;`
246			`; mode 3`
247			`;`
248			`mov tmod, #007h ; t/c 0 in mode 3`
249			`mov th0, #000h ;load counter 0`
250			`mov tl0, #000h ;`
251			`setb tcon.4 ;start counter 0;`
252			`cpl p3.5;`
253			`cpl p3.5;`
254			`cpl p3.5;`
255			`cpl p3.5;`
256			`cpl p3.5;`
257			`cpl p3.5;`
258			`cpl p3.5;`
259			`cpl p3.5;`
260			`clr tcon.4 ;stop counter 0`
261			`mov r2, #090h ;`
262			`mov r3, #000h ;`
263			`mov r4, #004h ;`
264			`mov r5, #003h ;`
265			`acall test0 ;`
266
267			`mov tl0, #0fch ; load counter 0`
268			`mov th0, #000h ;`
269			`setb tcon.4 ;start counter 0`
270			`cpl p3.5;`
271			`cpl p3.5;`
272			`cpl p3.5;`
273			`cpl p3.5;`
274			`cpl p3.5;`
275			`cpl p3.5;`
276			`cpl p3.5;`
277			`cpl p3.5;`
278			`cpl p3.5;`
279			`cpl p3.5;`
280			`cpl p3.5;`
281			`cpl p3.5;`
282			`clr tcon.4 ;stop counter 0`
283			`mov r2, #0a0h ;`
284			`mov r3, #000h ;`
285			`mov r4, #002h ;`
286			`mov r5, #004h ;`
287			`acall test0 ;`
288
289			`mov tl0, #000h ; load counter 0`
290			`mov th0, #000h ;`
291			`setb tcon.6 ; start counter 1`
292			`mov a, #03h ;`
293			`acall wait ;`
294			`nop;`
295			`nop;`
296			`nop;`
297			`nop;`
298			`clr tcon.6 ; stop counter 1`
299			`mov r2, #0b0h ;`
300			`mov r3, #004h ;`
301			`mov r4, #000h ;`
302			`mov r5, #004h ;`
303			`acall test0 ;`
304
305			`mov tl0, #000h ; load counter 0`
306			`mov th0, #0fch ;`
307			`setb tcon.6 ;start counter 1`
308			`mov a, #05h ;`
309			`acall wait ;`
310			`nop;`
311			`nop;`
312			`nop;`
313			`nop;`
314			`clr tcon.6 ;stop counter 1`
315			`mov r2, #0c0h ;`
316			`mov r3, #003h ;`
317			`mov r4, #000h ;`
318			`mov r5, #001h ;`
319			`mov r0, 01h ;`
320			`acall test0 ;`
321
322			`mov p0, #001h ; test counter 0 done!`
323			`mov r1, #000h ;`
324
325			`;`
326			`; timer 1 test`
327			`;`
328			`; mode 0`
329			`;`
330			`mov tmod, #040h ;t/c 0 and t/c 1 in counter mode 0`
331			`mov th1, #000h ;load counter 1`
332			`mov tl1, #000h ;`
333			`mov tcon, #040h ;start counter 1;`
334			`cpl p3.6;`
335			`cpl p3.6;`
336			`cpl p3.6;`
337			`cpl p3.6;`
338			`cpl p3.6;`
339			`cpl p3.6;`
340			`cpl p3.6;`
341			`cpl p3.6;`
342			`clr tcon.6 ;stop counter 1`
343			`mov r2, #018h ;`
344			`mov r3, #000h ;`
345			`mov r4, #004h ;`
346			`mov r5, #000h ;`
347			`acall test1 ;`
348
349			`mov tl1, #01ch ; load counter 1`
350			`setb tcon.6 ;start counter 1`
351			`cpl p3.6;`
352			`cpl p3.6;`
353			`cpl p3.6;`
354			`cpl p3.6;`
355			`cpl p3.6;`
356			`cpl p3.6;`
357			`cpl p3.6;`
358			`cpl p3.6;`
359			`cpl p3.6;`
360			`cpl p3.6;`
361			`clr tcon.6 ;stop counter 1`
362			`mov r2, #028h ;`
363			`mov r3, #001h ;`
364			`mov r4, #001h ;`
365			`mov r5, #000h ;`
366			`acall test1 ;`
367
368			`mov tl1, #01ch ;`
369			`mov th1, #0ffh ;`
370			`setb tcon.6 ;start counter 1`
371			`cpl p3.6;`
372			`cpl p3.6;`
373			`cpl p3.6;`
374			`cpl p3.6;`
375			`cpl p3.6;`
376			`cpl p3.6;`
377			`cpl p3.6;`
378			`cpl p3.6;`
379			`cpl p3.6;`
380			`cpl p3.6;`
381			`cpl p3.6;`
382			`cpl p3.6;`
383			`clr tcon.6 ;stop counter 1`
384			`mov r2, #038h ;`
385			`mov r3, #000h ;`
386			`mov r4, #002h ;`
387			`mov r5, #001h ;`
388			`acall test1 ;`
389			`;`
390			`; mode 1`
391			`;`
392			`mov tmod, #050h ; t/c 1 in counter 1`
393			`mov th1, #000h ;load counter 1`
394			`mov tl1, #000h ;`
395			`setb tcon.6 ;start counter 1`
396			`cpl p3.6;`
397			`cpl p3.6;`
398			`cpl p3.6;`
399			`cpl p3.6;`
400			`cpl p3.6;`
401			`cpl p3.6;`
402			`cpl p3.6;`
403			`cpl p3.6;`
404			`clr tcon.6 ;stop counter 1`
405			`mov r2, #048h ;`
406			`mov r3, #000h ;`
407			`mov r4, #004h ;`
408			`mov r5, #001h ;`
409			`acall test1 ;`
410
411			`mov tl1, #0fch ; load counter 1`
412			`setb tcon.6 ; start counter 1`
413			`cpl p3.6;`
414			`cpl p3.6;`
415			`cpl p3.6;`
416			`cpl p3.6;`
417			`cpl p3.6;`
418			`cpl p3.6;`
419			`cpl p3.6;`
420			`cpl p3.6;`
421			`cpl p3.6;`
422			`cpl p3.6;`
423			`clr tcon.6 ;stop counter 1`
424			`mov r2, #058h ;`
425			`mov r3, #001h ;`
426			`mov r4, #001h ;`
427			`mov r5, #001h ;`
428			`acall test1 ;`
429
430			`mov tl1, #0fch ;`
431			`mov th1, #0ffh ;`
432			`setb tcon.6 ;start counter 1`
433			`cpl p3.6;`
434			`cpl p3.6;`
435			`cpl p3.6;`
436			`cpl p3.6;`
437			`cpl p3.6;`
438			`cpl p3.6;`
439			`cpl p3.6;`
440			`cpl p3.6;`
441			`cpl p3.6;`
442			`cpl p3.6;`
443			`cpl p3.6;`
444			`cpl p3.6;`
445			`clr tcon.6 ;stop counter 1`
446			`mov r2, #068h ;`
447			`mov r3, #000h ;`
448			`mov r4, #002h ;`
449			`mov r5, #002h ;`
450			`acall test1 ;`
451			`;`
452			`; mode 2`
453			`;`
454			`mov tmod, #060h ; t/c 1 in mode 2`
455			`mov th1, #000h ;load counter 1`
456			`mov tl1, #005h ;`
457			`setb tcon.6 ;start counter 1`
458			`cpl p3.6;`
459			`cpl p3.6;`
460			`cpl p3.6;`
461			`cpl p3.6;`
462			`cpl p3.6;`
463			`cpl p3.6;`
464			`cpl p3.6;`
465			`cpl p3.6;`
466			`clr tcon.6 ;stop counter 1`
467			`mov r2, #078h ;`
468			`mov r3, #000h ;`
469			`mov r4, #009h ;`
470			`mov r5, #002h ;`
471			`acall test1 ;`
472
473			`mov tl1, #0fch ; load counter 1`
474			`mov th1, #050h ;`
475			`setb tcon.6 ;start counter 1`
476			`cpl p3.6;`
477			`cpl p3.6;`
478			`cpl p3.6;`
479			`cpl p3.6;`
480			`cpl p3.6;`
481			`cpl p3.6;`
482			`cpl p3.6;`
483			`cpl p3.6;`
484			`cpl p3.6;`
485			`cpl p3.6;`
486			`clr tcon.6 ;stop counter 1`
487			`mov r2, #088h ;`
488			`mov r3, #050h ;`
489			`mov r4, #051h ;`
490			`mov r5, #003h ;`
491			`acall test1 ;`
492			`;`
493			`; mode 3`
494			`;`
495			`mov tmod, #070h ; t/c 1 in mode 3`
496			`mov th1, #000h ;load counter 1`
497			`mov tl1, #000h ;`
498			`setb tcon.6 ;start counter 1`
499			`cpl p3.6;`
500			`cpl p3.6;`
501			`cpl p3.6;`
502			`cpl p3.6;`
503			`cpl p3.6;`
504			`cpl p3.6;`
505			`cpl p3.6;`
506			`cpl p3.6;`
507			`clr tcon.6 ;stop counter 1`
508			`mov r2, #098h ;`
509			`mov r3, #000h ;`
510			`mov r4, #000h ;`
511			`mov r5, #003h ;`
512			`acall test1 ;`
513
514			`mov tl1, #0fch ; load counter 1`
515			`mov th1, #0ffh ;`
516			`setb tcon.6 ;start counter 1`
517			`cpl p3.6;`
518			`cpl p3.6;`
519			`cpl p3.6;`
520			`cpl p3.6;`
521			`cpl p3.6;`
522			`cpl p3.6;`
523			`cpl p3.6;`
524			`cpl p3.6;`
525			`cpl p3.6;`
526
527
528			`cpl p3.6;`
529			`cpl p3.6;`
530			`cpl p3.6;`
531			`clr tcon.6 ;stop counter 1`
532			`mov r2, #0a8h ;`
533			`mov r3, #0ffh ;`
534			`mov r4, #0fch ;`
535			`mov r5, #003h ;`
536			`acall test1 ;`
537
538			`mov p0, #002h ; test counter 1 done!`
539
540
541			`end`