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[/] [8051/] [tags/] [rel_1/] [asm/] [hex/] [r_bank.hex] - Blame information for rev 147

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00_60] = 8'h75;
    buff [16'h00_61] = 8'h80;
    buff [16'h00_62] = 8'h04;
end
 
always @(posedge clk)
begin
  data1 <= #1 buff [addr];
  data2 <= #1 buff [addr+1];
  data3 <= #1 buff [addr+2];
end
 
endmodule
 

Line No.	Rev	Author	Line
1	2	simont	`00_60] = 8'h75;`
2			`buff [16'h00_61] = 8'h80;`
3			`buff [16'h00_62] = 8'h04;`
4			`end`
5
6			`always @(posedge clk)`
7			`begin`
8			`data1 <= #1 buff [addr];`
9			`data2 <= #1 buff [addr+1];`
10			`data3 <= #1 buff [addr+2];`
11			`end`
12
13			`endmodule`
14

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[/] [8051/] [tags/] [rel_1/] [asm/] [hex/] [r_bank.hex] - Blame information for rev 147