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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_acc.v] - Blame information for rev 82

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores acccumulator                                     ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   accumulaor register for 8051 core                          ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.7  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_acc (clk, rst, bit_in, data_in, data2_in, wr, wr_bit, wr_addr, rd_addr,
                data_out, bit_out, p, wr_sfr);
// clk          (in)  clock
// rst          (in)  reset
// bit_in       (in)  bit input - used in case of writing bits to acc (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
// data_in      (in)  data input - used to write to acc (from alu destiantion 1) [oc8051_alu.des1]
// data2_in     (in)  data 2 input - write to acc, from alu detination 2 - instuctions mul and div [oc8051_alu.des2]
// wr           (in)  write - actine high [oc8051_decoder.wr -r]
// wr_bit       (in)  write bit addresable - actine high [oc8051_decoder.bit_addr -r]
// wr_addr      (in)  write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]
// data_out     (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]
// p            (out) parity [oc8051_psw.p]
// mx_ext       (in)  mx extension
// wr_sfr
//
 
 
input clk, rst, wr, wr_bit, bit_in;
input [2:0] rd_addr, wr_sfr;
input [7:0] wr_addr, data_in, data2_in;
 
output p, bit_out;
output [7:0] data_out;
 
reg [7:0] data_out;
reg bit_out;
 
//
//calculates parity
assign p = ^data_out;
 
//
//writing to acc
//must check if write high and correct address
always @(posedge clk or posedge rst)
begin
  if (rst)
    data_out <= #1 `OC8051_RST_ACC;
  else if ((wr_sfr==`OC8051_WRS_ACC2) || (wr_sfr==`OC8051_WRS_BA))
    data_out <= #1 data2_in;
  else if ((wr_sfr==`OC8051_WRS_ACC1))
    data_out <= #1 data_in;
  else if (wr) begin
    if (!wr_bit) begin
      if (wr_addr==`OC8051_SFR_ACC)
        data_out <= #1 data_in;
    end else begin
      if (wr_addr[7:3]==`OC8051_SFR_B_ACC)
        data_out[wr_addr[2:0]] <= #1 bit_in;
    end
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
      bit_out <= #1 bit_in;
  end else if (((wr_addr==`OC8051_SFR_ACC) & wr & !wr_bit) || (wr_sfr==`OC8051_WRS_ACC1)) begin
      bit_out <= #1 data_in[rd_addr];
  end else if ((wr_sfr==`OC8051_WRS_ACC2) || (wr_sfr==`OC8051_WRS_BA)) begin
      bit_out <= #1 data2_in[rd_addr];
  end else bit_out <= #1 data_out[rd_addr];
end
 
endmodule
 

Line No.	Rev	Author	Line
1	76	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores acccumulator ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// accumulaor register for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	82	simont	`// Revision 1.8 2002/11/05 17:23:54 simont`
48			`// add module oc8051_sfr, 256 bytes internal ram`
49			`//`
50	76	simont	`// Revision 1.7 2002/09/30 17:33:59 simont`
51			`// prepared header`
52			`//`
53			`//`
54
55			`// synopsys translate_off`
56			`include "oc8051_timescale.v"
57			`// synopsys translate_on`
58
59			`include "oc8051_defines.v"
60
61
62	82	simont	`module oc8051_acc (clk, rst, bit_in, data_in, data2_in, wr, wr_bit, wr_addr, rd_addr,`
63			`data_out, bit_out, p, wr_sfr);`
64	76	simont	`// clk (in) clock`
65			`// rst (in) reset`
66			`// bit_in (in) bit input - used in case of writing bits to acc (bit adddressable memory space - alu carry) [oc8051_alu.desCy]`
67			`// data_in (in) data input - used to write to acc (from alu destiantion 1) [oc8051_alu.des1]`
68			`// data2_in (in) data 2 input - write to acc, from alu detination 2 - instuctions mul and div [oc8051_alu.des2]`
69			`// wr (in) write - actine high [oc8051_decoder.wr -r]`
70			`// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]`
71			`// wr_addr (in) write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]`
72			`// data_out (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]`
73			`// p (out) parity [oc8051_psw.p]`
74	82	simont	`// mx_ext (in) mx extension`
75			`// wr_sfr`
76	76	simont	`//`
77
78
79	82	simont	`input clk, rst, wr, wr_bit, bit_in;`
80			`input [2:0] rd_addr, wr_sfr;`
81			`input [7:0] wr_addr, data_in, data2_in;`
82	76	simont
83			`output p, bit_out;`
84			`output [7:0] data_out;`
85
86			`reg [7:0] data_out;`
87			`reg bit_out;`
88
89			`//`
90			`//calculates parity`
91			`assign p = ^data_out;`
92
93			`//`
94			`//writing to acc`
95			`//must check if write high and correct address`
96			`always @(posedge clk or posedge rst)`
97			`begin`
98			`if (rst)`
99			data_out <= #1 `OC8051_RST_ACC;
100	82	simont	else if ((wr_sfr==`OC8051_WRS_ACC2) \|\| (wr_sfr==`OC8051_WRS_BA))
101	76	simont	`data_out <= #1 data2_in;`
102	82	simont	else if ((wr_sfr==`OC8051_WRS_ACC1))
103			`data_out <= #1 data_in;`
104	76	simont	`else if (wr) begin`
105			`if (!wr_bit) begin`
106			if (wr_addr==`OC8051_SFR_ACC)
107			`data_out <= #1 data_in;`
108			`end else begin`
109			if (wr_addr[7:3]==`OC8051_SFR_B_ACC)
110			`data_out[wr_addr[2:0]] <= #1 bit_in;`
111			`end`
112			`end`
113			`end`
114
115			`always @(posedge clk or posedge rst)`
116			`begin`
117			`if (rst) bit_out <= #1 1'b0;`
118			`else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin`
119			`bit_out <= #1 bit_in;`
120	82	simont	end else if (((wr_addr==`OC8051_SFR_ACC) & wr & !wr_bit) \|\| (wr_sfr==`OC8051_WRS_ACC1)) begin
121	76	simont	`bit_out <= #1 data_in[rd_addr];`
122	82	simont	end else if ((wr_sfr==`OC8051_WRS_ACC2) \|\| (wr_sfr==`OC8051_WRS_BA)) begin
123			`bit_out <= #1 data2_in[rd_addr];`
124	76	simont	`end else bit_out <= #1 data_out[rd_addr];`
125			`end`
126
127			`endmodule`
128

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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_acc.v] - Blame information for rev 82