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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Blame information for rev 81

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 memory interface                                       ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   comunication betwen cpu and memory                         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_memory_interface (clk, rst,
//decoder
  wr_i, wr_bit_i, rd_sel, wr_sel,
  pc_wr_sel, pc_wr, pc, rd,
  mem_wait, mem_act, istb,
//internal ram
  wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,
 
  bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,
 
//program rom
  iadr_o, ea, ea_int,
  op1_out, op2_out, op3_out,
//internal
  op1_i, op2_i, op3_i,
//external
  iack_i, istb_o, idat_i,
 
//external data ram
  dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,
//interrupt interface
  intr, int_v, int_ack,
 
//alu
  des1, des2,
 
//sfr's
  dptr, ri, rn_mem, sp,  sp_w, rn, acc, reti);
 
input bit_in, sfr_bit, dack_i;
input [2:0] mem_act;
input [7:0] in_ram, sfr, acc, sp_w;
input [31:0] idat_i;
 
output bit_out, mem_wait, reti;
output [7:0] iram_out, wr_dat;
 
reg bit_out, reti;
reg [7:0] iram_out, sp_r;
reg [2:0] rd_addr_r;
input clk, rst, wr_i, wr_bit_i;
output wr_o, wr_bit_o;
 
//????
reg dack_ir;
reg [7:0] ddat_ir;
reg [23:0] idat_ir;
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
input iack_i;
input [7:0] des1, des2;
output [15:0] iadr_o;
 
wire ea_rom_sel;
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
input [7:0] ri, rn_mem, ddat_i;
input [15:0] dptr;
 
output dstb_o, dwe_o;
output [7:0] ddat_o;
output [15:0] dadr_o;
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
input [2:0] rd_sel, wr_sel;
input [4:0] rn;
input [7:0] sp;
 
output rd_ind, wr_ind;
output [7:0] wr_addr, rd_addr;
reg rd_ind, wr_ind;
reg [7:0] wr_addr, rd_addr;
 
reg [4:0] rn_r;
reg [7:0] ri_r, imm_r, imm2_r, op1_r;
wire [7:0] imm, imm2;
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
input intr, rd, ea, ea_int, istb;
input [7:0] op1_i, op2_i, op3_i, int_v;
output int_ack, istb_o;
output [7:0] op1_out, op3_out, op2_out;
 
reg int_ack_t, int_ack, int_ack_buff;
reg [7:0] int_vec_buff;
reg [7:0] op1_out, op2_buff, op3_buff;
reg [7:0] op1_o, op2_o, op3_o;
reg [7:0] op1_xt, op2_xt, op3_xt;
 
wire [7:0] op1, op2, op3, op2_direct;
//wire op_sel;
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
input [2:0] pc_wr_sel;
 
input pc_wr;
output [15:0] pc;
 
 
reg [15:0] pc;
 
//
//pc            program counter register, save current value
reg [15:0] pc_buf;
wire [15:0] alu;
 
//
// wr_lo        write low: used in reti instruction, write only low byte of pc
// ini_buff     interrupt buffer: used to prevent interrupting in the middle of executin instructions
reg int_buff, int_buff1;
 
 
//
//
////////////////////////////
reg istb_t, imem_wait, dstb_o, dwe_o;
//reg [3:0] mem_act_r;
reg [7:0] ddat_o;
reg [15:0] iadr_t, dadr_ot;
reg dmem_wait;
wire pc_wait;
wire [1:0] bank;
//wire pis_l;
wire [15:0] iadr_ot;
wire [7:0] isr_call;
 
assign bank = rn[4:3];
assign imm = op2_out;
assign imm2 = op3_out;
assign alu = {des2,des1};
assign ea_rom_sel = ea && ea_int;
assign wr_o = wr_i;
assign wr_bit_o = wr_bit_i;
 
assign mem_wait = dmem_wait || imem_wait;
//assign istb_o = (istb || istb_t || (!iack_i)) && !dstb_o && !ea_rom_sel;
assign istb_o = (istb || istb_t) && !dstb_o && !ea_rom_sel;
 
assign pc_wait = rd && (ea_rom_sel || (!istb_t && !(istb_o && !iack_i)));
 
assign wr_dat = des1;
 
 
/////////////////////////////
//
//  ram_select
//
/////////////////////////////
always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rn_mem or rd_ind)
begin
  if (rd_addr_r[2] && !rd_ind) begin
    iram_out = sfr;
    bit_out = sfr_bit;
  end else if (~|rd_addr_r[2:0]) begin
    iram_out = rn_mem;
    bit_out = bit_in;
  end else begin
    iram_out = in_ram;
    bit_out = bit_in;
  end
end
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
always @(rd_sel or sp or ri or rn or imm or op1_out or dadr_o[15:0] or bank)
begin
     case (rd_sel)
      `OC8051_RRS_RN : rd_addr = {3'h0, rn};
      `OC8051_RRS_I : rd_addr = ri;
      `OC8051_RRS_D : rd_addr = imm;
      `OC8051_RRS_SP : rd_addr = sp;
 
      `OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
      `OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
      default : rd_addr = 2'bxx;
    endcase
 
end
 
 
//
//
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
begin
    case (wr_sel)
      `OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
      `OC8051_RWS_I : wr_addr = ri_r;
      `OC8051_RWS_D : wr_addr = imm_r;
      `OC8051_RWS_SP : wr_addr = sp_w;
      `OC8051_RWS_D3 : wr_addr = imm2_r;
      default : wr_addr = 2'bxx;
    endcase
end
 
always @(posedge clk or posedge rst)
  if (rst)
    rd_ind <= #1 1'b0;
  else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
    rd_ind <= #1 1'b1;
  else
    rd_ind <= #1 1'b0;
 
always @(wr_sel)
  if ((wr_sel==`OC8051_RWS_I) || (wr_sel==`OC8051_RWS_SP))
    wr_ind = 1'b1;
  else
    wr_ind = 1'b0;
 
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
//
// output address is alu destination
// (instructions MOVC)
 
assign iadr_ot = istb_t ? iadr_t : pc;
assign iadr_o = iadr_ot;
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    iadr_t <= #1 23'h0;
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 24'h0;
  end else if (iack_i) begin
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 idat_i [31:8];
  end else if (ea_rom_sel && imem_wait) begin
    imem_wait <= #1 1'b0;
  end else if (ea_rom_sel && !imem_wait && istb_t) begin
    istb_t <= #1 1'b0;
  end else if (mem_act==`OC8051_MAS_CODE) begin
    iadr_t <= #1 {des2, des1};
    istb_t <= #1 1'b1;
    imem_wait <= #1 1'b1;
  end
end
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
 
assign dadr_o = dadr_ot;
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    dwe_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
    dstb_o <= #1 1'b0;
    ddat_o <= #1 8'h00;
    dadr_ot <= #1 23'h0;
  end else if (dack_i) begin
    dwe_o <= #1 1'b0;
    dstb_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
  end else begin
    case (mem_act)
      `OC8051_MAS_DPTR_R: begin  // read from external rom: acc=(dptr)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_DPTR_W: begin  // write to external rom: (dptr)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_R:   begin  // read from external rom: acc=(Ri)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_W: begin    // write to external rom: (Ri)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
    endcase
  end
end
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
 
assign op1 = ea_rom_sel ? op1_i: op1_xt;
assign op2 = ea_rom_sel ? op2_i: op2_xt;
assign op3 = ea_rom_sel ? op3_i: op3_xt;
 
 
always @(dack_ir or ddat_ir or op1_o or iram_out)
  if (dack_ir)
    op1_out = ddat_ir;
  else
    op1_out = op1_o;
 
assign op3_out = (rd) ? op3_o : op3_buff;
assign op2_out = (rd) ? op2_o : op2_buff;
 
always @(idat_i or iack_i or idat_ir or rd)
begin
  if (iack_i) begin
    op1_xt = idat_i[31:24];
    op2_xt = idat_i[23:16];
    op3_xt = idat_i[15:8];
  end else if (!rd) begin
    op1_xt = idat_ir[23:16];
    op2_xt = idat_ir[15:8];
    op3_xt = idat_ir[7:0];
  end else begin
    op1_xt = 8'h00;
    op2_xt = 8'h00;
    op3_xt = 8'h00;
  end
end
 
 
//
// in case of interrupts
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)
begin
  if (int_ack_t && (iack_i || ea_rom_sel)) begin
    op1_o = `OC8051_LCALL;
    op2_o = 8'h00;
    op3_o = int_vec_buff;
  end else begin
    op1_o = op1;
    op2_o = op2;
    op3_o = op3;
  end
end
 
//
//in case of reti
always @(posedge clk or posedge rst)
  if (rst) reti <= #1 1'b0;
  else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
  else reti <= #1 1'b0;
 
//
// remember inputs
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    op2_buff <= #1 8'h0;
    op3_buff <= #1 8'h0;
  end else if (rd) begin
    op2_buff <= #1 op2_o;
    op3_buff <= #1 op3_o;
  end
end
 
//
// remember interrupt
// we don't want to interrupt instruction in the middle of execution
always @(posedge clk or posedge rst)
 if (rst) begin
   int_ack_t <= #1 1'b0;
   int_vec_buff <= #1 8'h00;
 end else if (intr) begin
   int_ack_t <= #1 1'b1;
   int_vec_buff <= #1 int_v;
 end else if (rd && (ea_rom_sel || iack_i)) int_ack_t <= #1 1'b0;
 
always @(posedge clk or posedge rst)
  if (rst) int_ack_buff <= #1 1'b0;
  else int_ack_buff <= #1 int_ack_t;
 
always @(posedge clk or posedge rst)
  if (rst) int_ack <= #1 1'b0;
  else begin
    if ((int_ack_buff) & !(int_ack_t))
      int_ack <= #1 1'b1;
    else int_ack <= #1 1'b0;
  end
 
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
 
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or alu[7:0] or ea_rom_sel or iack_i)
begin
    if (int_buff || int_buff1) begin
//
//in case of interrupt hold valut, to be written to stack
      pc= pc_buf;
//    end else if (pis_l) begin
//      pc = {pc_buf[22:8], alu[7:0]};
    end else if (pc_wait) begin
        casex (op1_out)
          `OC8051_ACALL : pc= pc_buf + 23'h2;
          `OC8051_AJMP : pc= pc_buf + 23'h2;
 
        //op_code [7:3]
          `OC8051_CJNE_R : pc= pc_buf + 23'h3;
          `OC8051_DJNZ_R : pc= pc_buf + 23'h2;
          `OC8051_MOV_DR : pc= pc_buf + 23'h2;
          `OC8051_MOV_CR : pc= pc_buf + 23'h2;
          `OC8051_MOV_RD : pc= pc_buf + 23'h2;
 
        //op_code [7:1]
          `OC8051_CJNE_I : pc= pc_buf + 23'h3;
          `OC8051_MOV_ID : pc= pc_buf + 23'h2;
          `OC8051_MOV_DI : pc= pc_buf + 23'h2;
          `OC8051_MOV_CI : pc= pc_buf + 23'h2;
 
        //op_code [7:0]
          `OC8051_ADD_D : pc= pc_buf + 23'h2;
          `OC8051_ADD_C : pc= pc_buf + 23'h2;
          `OC8051_ADDC_D : pc= pc_buf + 23'h2;
          `OC8051_ADDC_C : pc= pc_buf + 23'h2;
          `OC8051_ANL_D : pc= pc_buf + 23'h2;
          `OC8051_ANL_C : pc= pc_buf + 23'h2;
          `OC8051_ANL_DD : pc= pc_buf + 23'h2;
          `OC8051_ANL_DC : pc= pc_buf + 23'h3;
          `OC8051_ANL_B : pc= pc_buf + 23'h2;
          `OC8051_ANL_NB : pc= pc_buf + 23'h2;
          `OC8051_CJNE_D : pc= pc_buf + 23'h3;
          `OC8051_CJNE_C : pc= pc_buf + 23'h3;
          `OC8051_CLR_B : pc= pc_buf + 23'h2;
          `OC8051_CPL_B : pc= pc_buf + 23'h2;
          `OC8051_DEC_D : pc= pc_buf + 23'h2;
          `OC8051_DJNZ_D : pc= pc_buf + 23'h3;
          `OC8051_INC_D : pc= pc_buf + 23'h2;
          `OC8051_JB : pc= pc_buf + 23'h3;
          `OC8051_JBC : pc= pc_buf + 23'h3;
          `OC8051_JC : pc= pc_buf + 23'h2;
          `OC8051_JNB : pc= pc_buf + 23'h3;
          `OC8051_JNC : pc= pc_buf + 23'h2;
          `OC8051_JNZ : pc= pc_buf + 23'h2;
          `OC8051_JZ : pc= pc_buf + 23'h2;
          `OC8051_LCALL :pc= pc_buf + 23'h3;
          `OC8051_LJMP : pc= pc_buf + 23'h3;
          `OC8051_MOV_D : pc= pc_buf + 23'h2;
          `OC8051_MOV_C : pc= pc_buf + 23'h2;
          `OC8051_MOV_DA : pc= pc_buf + 23'h2;
          `OC8051_MOV_DD : pc= pc_buf + 23'h3;
          `OC8051_MOV_CD : pc= pc_buf + 23'h3;
          `OC8051_MOV_BC : pc= pc_buf + 23'h2;
          `OC8051_MOV_CB : pc= pc_buf + 23'h2;
          `OC8051_MOV_DP : pc= pc_buf + 23'h3;
          `OC8051_ORL_D : pc= pc_buf + 23'h2;
          `OC8051_ORL_C : pc= pc_buf + 23'h2;
          `OC8051_ORL_AD : pc= pc_buf + 23'h2;
          `OC8051_ORL_CD : pc= pc_buf + 23'h3;
          `OC8051_ORL_B : pc= pc_buf + 23'h2;
          `OC8051_ORL_NB : pc= pc_buf + 23'h2;
          `OC8051_POP : pc= pc_buf + 23'h2;
          `OC8051_PUSH : pc= pc_buf + 23'h2;
          `OC8051_SETB_B : pc= pc_buf + 23'h2;
          `OC8051_SJMP : pc= pc_buf + 23'h2;
          `OC8051_SUBB_D : pc= pc_buf + 23'h2;
          `OC8051_SUBB_C : pc= pc_buf + 23'h2;
          `OC8051_XCH_D : pc= pc_buf + 23'h2;
          `OC8051_XRL_D : pc= pc_buf + 23'h2;
          `OC8051_XRL_C : pc= pc_buf + 23'h2;
          `OC8051_XRL_AD : pc= pc_buf + 23'h2;
          `OC8051_XRL_CD : pc= pc_buf + 23'h3;
          default: pc= pc_buf + 23'h1;
        endcase
//
//in case of instructions that use more than one clock hold current pc
    end else begin
      pc= pc_buf;
   end
end
 
 
//
//interrupt buffer
always @(posedge clk or posedge rst)
  if (rst) begin
    int_buff1 <= #1 1'b0;
  end else begin
    int_buff1 <= #1 int_buff;
  end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    int_buff <= #1 1'b0;
  end else if (intr) begin
    int_buff <= #1 1'b1;
  end else if (pc_wait)
    int_buff <= #1 1'b0;
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    pc_buf <= #1 `OC8051_RST_PC;
  end else begin
    if (pc_wr) begin
//
//case of writing new value to pc (jupms)
      case (pc_wr_sel)
        `OC8051_PIS_ALU: pc_buf        <= #1 alu;
        `OC8051_PIS_AL:  pc_buf[7:0]   <= #1 alu[7:0];
        `OC8051_PIS_AH:  pc_buf[15:8]  <= #1 alu[7:0];
        `OC8051_PIS_I11: pc_buf[10:0]  <= #1 {op1_out[7:5], op2_out};
        `OC8051_PIS_I16: pc_buf        <= #1 {op2_out, op3_out};
      endcase
    end else
//
//or just remember current
      pc_buf <= #1 pc;
  end
end
 
 
always @(posedge clk or posedge rst)
  if (rst)
    ddat_ir <= #1 8'h00;
  else if (dack_i)
    ddat_ir <= #1 ddat_i;
 
////////////////////////
always @(posedge clk or posedge rst)
  if (rst) begin
    rn_r <= #1 5'd0;
    ri_r <= #1 8'h00;
    imm_r <= #1 8'h00;
    imm2_r <= #1 8'h00;
    rd_addr_r <= #1 3'h0;
    op1_r <= #1 8'h0;
    dack_ir <= #1 1'b0;
    sp_r <= #1 1'b0;
  end else begin
    rn_r <= #1 rn;
    ri_r <= #1 ri;
    imm_r <= #1 imm;
    imm2_r <= #1 imm2;
    rd_addr_r <= #1 rd_addr[7:5];
    op1_r <= #1 op1_out;
    dack_ir <= #1 dack_i;
    sp_r <= #1 sp;
  end
 
 
endmodule

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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Blame information for rev 81

Line No.	Rev	Author	Line
1	81	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 memory interface ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// comunication betwen cpu and memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`// synopsys translate_off`
50			`include "oc8051_timescale.v"
51			`// synopsys translate_on`
52
53			`include "oc8051_defines.v"
54
55
56			`module oc8051_memory_interface (clk, rst,`
57			`//decoder`
58			`wr_i, wr_bit_i, rd_sel, wr_sel,`
59			`pc_wr_sel, pc_wr, pc, rd,`
60			`mem_wait, mem_act, istb,`
61			`//internal ram`
62			`wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,`
63
64			`bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,`
65
66			`//program rom`
67			`iadr_o, ea, ea_int,`
68			`op1_out, op2_out, op3_out,`
69			`//internal`
70			`op1_i, op2_i, op3_i,`
71			`//external`
72			`iack_i, istb_o, idat_i,`
73
74			`//external data ram`
75			`dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,`
76			`//interrupt interface`
77			`intr, int_v, int_ack,`
78
79			`//alu`
80			`des1, des2,`
81
82			`//sfr's`
83			`dptr, ri, rn_mem, sp, sp_w, rn, acc, reti);`
84
85			`input bit_in, sfr_bit, dack_i;`
86			`input [2:0] mem_act;`
87			`input [7:0] in_ram, sfr, acc, sp_w;`
88			`input [31:0] idat_i;`
89
90			`output bit_out, mem_wait, reti;`
91			`output [7:0] iram_out, wr_dat;`
92
93			`reg bit_out, reti;`
94			`reg [7:0] iram_out, sp_r;`
95			`reg [2:0] rd_addr_r;`
96			`input clk, rst, wr_i, wr_bit_i;`
97			`output wr_o, wr_bit_o;`
98
99			`//????`
100			`reg dack_ir;`
101			`reg [7:0] ddat_ir;`
102			`reg [23:0] idat_ir;`
103
104			`/////////////////////////////`
105			`//`
106			`// rom_addr_sel`
107			`//`
108			`/////////////////////////////`
109			`input iack_i;`
110			`input [7:0] des1, des2;`
111			`output [15:0] iadr_o;`
112
113			`wire ea_rom_sel;`
114
115			`/////////////////////////////`
116			`//`
117			`// ext_addr_sel`
118			`//`
119			`/////////////////////////////`
120			`input [7:0] ri, rn_mem, ddat_i;`
121			`input [15:0] dptr;`
122
123			`output dstb_o, dwe_o;`
124			`output [7:0] ddat_o;`
125			`output [15:0] dadr_o;`
126
127			`/////////////////////////////`
128			`//`
129			`// ram_adr_sel`
130			`//`
131			`/////////////////////////////`
132
133			`input [2:0] rd_sel, wr_sel;`
134			`input [4:0] rn;`
135			`input [7:0] sp;`
136
137			`output rd_ind, wr_ind;`
138			`output [7:0] wr_addr, rd_addr;`
139			`reg rd_ind, wr_ind;`
140			`reg [7:0] wr_addr, rd_addr;`
141
142			`reg [4:0] rn_r;`
143			`reg [7:0] ri_r, imm_r, imm2_r, op1_r;`
144			`wire [7:0] imm, imm2;`
145
146			`/////////////////////////////`
147			`//`
148			`// op_select`
149			`//`
150			`/////////////////////////////`
151
152			`input intr, rd, ea, ea_int, istb;`
153			`input [7:0] op1_i, op2_i, op3_i, int_v;`
154			`output int_ack, istb_o;`
155			`output [7:0] op1_out, op3_out, op2_out;`
156
157			`reg int_ack_t, int_ack, int_ack_buff;`
158			`reg [7:0] int_vec_buff;`
159			`reg [7:0] op1_out, op2_buff, op3_buff;`
160			`reg [7:0] op1_o, op2_o, op3_o;`
161			`reg [7:0] op1_xt, op2_xt, op3_xt;`
162
163			`wire [7:0] op1, op2, op3, op2_direct;`
164			`//wire op_sel;`
165
166			`/////////////////////////////`
167			`//`
168			`// pc`
169			`//`
170			`/////////////////////////////`
171			`input [2:0] pc_wr_sel;`
172
173			`input pc_wr;`
174			`output [15:0] pc;`
175
176
177			`reg [15:0] pc;`
178
179			`//`
180			`//pc program counter register, save current value`
181			`reg [15:0] pc_buf;`
182			`wire [15:0] alu;`
183
184			`//`
185			`// wr_lo write low: used in reti instruction, write only low byte of pc`
186			`// ini_buff interrupt buffer: used to prevent interrupting in the middle of executin instructions`
187			`reg int_buff, int_buff1;`
188
189
190			`//`
191			`//`
192			`////////////////////////////`
193			`reg istb_t, imem_wait, dstb_o, dwe_o;`
194			`//reg [3:0] mem_act_r;`
195			`reg [7:0] ddat_o;`
196			`reg [15:0] iadr_t, dadr_ot;`
197			`reg dmem_wait;`
198			`wire pc_wait;`
199			`wire [1:0] bank;`
200			`//wire pis_l;`
201			`wire [15:0] iadr_ot;`
202			`wire [7:0] isr_call;`
203
204			`assign bank = rn[4:3];`
205			`assign imm = op2_out;`
206			`assign imm2 = op3_out;`
207			`assign alu = {des2,des1};`
208			`assign ea_rom_sel = ea && ea_int;`
209			`assign wr_o = wr_i;`
210			`assign wr_bit_o = wr_bit_i;`
211
212			`assign mem_wait = dmem_wait \|\| imem_wait;`
213			`//assign istb_o = (istb \|\| istb_t \|\| (!iack_i)) && !dstb_o && !ea_rom_sel;`
214			`assign istb_o = (istb \|\| istb_t) && !dstb_o && !ea_rom_sel;`
215
216			`assign pc_wait = rd && (ea_rom_sel \|\| (!istb_t && !(istb_o && !iack_i)));`
217
218			`assign wr_dat = des1;`
219
220
221			`/////////////////////////////`
222			`//`
223			`// ram_select`
224			`//`
225			`/////////////////////////////`
226			`always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rn_mem or rd_ind)`
227			`begin`
228			`if (rd_addr_r[2] && !rd_ind) begin`
229			`iram_out = sfr;`
230			`bit_out = sfr_bit;`
231			`end else if (~\|rd_addr_r[2:0]) begin`
232			`iram_out = rn_mem;`
233			`bit_out = bit_in;`
234			`end else begin`
235			`iram_out = in_ram;`
236			`bit_out = bit_in;`
237			`end`
238			`end`
239
240			`/////////////////////////////`
241			`//`
242			`// ram_adr_sel`
243			`//`
244			`/////////////////////////////`
245
246			`always @(rd_sel or sp or ri or rn or imm or op1_out or dadr_o[15:0] or bank)`
247			`begin`
248			`case (rd_sel)`
249			`OC8051_RRS_RN : rd_addr = {3'h0, rn};
250			`OC8051_RRS_I : rd_addr = ri;
251			`OC8051_RRS_D : rd_addr = imm;
252			`OC8051_RRS_SP : rd_addr = sp;
253
254			`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
255			`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
256			`default : rd_addr = 2'bxx;`
257			`endcase`
258
259			`end`
260
261
262			`//`
263			`//`
264			`always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])`
265			`begin`
266			`case (wr_sel)`
267			`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
268			`OC8051_RWS_I : wr_addr = ri_r;
269			`OC8051_RWS_D : wr_addr = imm_r;
270			`OC8051_RWS_SP : wr_addr = sp_w;
271			`OC8051_RWS_D3 : wr_addr = imm2_r;
272			`default : wr_addr = 2'bxx;`
273			`endcase`
274			`end`
275
276			`always @(posedge clk or posedge rst)`
277			`if (rst)`
278			`rd_ind <= #1 1'b0;`
279			else if ((rd_sel==`OC8051_RRS_I) \|\| (rd_sel==`OC8051_RRS_SP))
280			`rd_ind <= #1 1'b1;`
281			`else`
282			`rd_ind <= #1 1'b0;`
283
284			`always @(wr_sel)`
285			if ((wr_sel==`OC8051_RWS_I) \|\| (wr_sel==`OC8051_RWS_SP))
286			`wr_ind = 1'b1;`
287			`else`
288			`wr_ind = 1'b0;`
289
290
291			`/////////////////////////////`
292			`//`
293			`// rom_addr_sel`
294			`//`
295			`/////////////////////////////`
296			`//`
297			`// output address is alu destination`
298			`// (instructions MOVC)`
299
300			`assign iadr_ot = istb_t ? iadr_t : pc;`
301			`assign iadr_o = iadr_ot;`
302
303
304			`always @(posedge clk or posedge rst)`
305			`begin`
306			`if (rst) begin`
307			`iadr_t <= #1 23'h0;`
308			`istb_t <= #1 1'b0;`
309			`imem_wait <= #1 1'b0;`
310			`idat_ir <= #1 24'h0;`
311			`end else if (iack_i) begin`
312			`istb_t <= #1 1'b0;`
313			`imem_wait <= #1 1'b0;`
314			`idat_ir <= #1 idat_i [31:8];`
315			`end else if (ea_rom_sel && imem_wait) begin`
316			`imem_wait <= #1 1'b0;`
317			`end else if (ea_rom_sel && !imem_wait && istb_t) begin`
318			`istb_t <= #1 1'b0;`
319			end else if (mem_act==`OC8051_MAS_CODE) begin
320			`iadr_t <= #1 {des2, des1};`
321			`istb_t <= #1 1'b1;`
322			`imem_wait <= #1 1'b1;`
323			`end`
324			`end`
325
326			`/////////////////////////////`
327			`//`
328			`// ext_addr_sel`
329			`//`
330			`/////////////////////////////`
331
332			`assign dadr_o = dadr_ot;`
333
334			`always @(posedge clk or posedge rst)`
335			`begin`
336			`if (rst) begin`
337			`dwe_o <= #1 1'b0;`
338			`dmem_wait <= #1 1'b0;`
339			`dstb_o <= #1 1'b0;`
340			`ddat_o <= #1 8'h00;`
341			`dadr_ot <= #1 23'h0;`
342			`end else if (dack_i) begin`
343			`dwe_o <= #1 1'b0;`
344			`dstb_o <= #1 1'b0;`
345			`dmem_wait <= #1 1'b0;`
346			`end else begin`
347			`case (mem_act)`
348			`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr)
349			`dwe_o <= #1 1'b0;`
350			`dstb_o <= #1 1'b1;`
351			`ddat_o <= #1 8'h00;`
352			`dadr_ot <= #1 {7'h0, dptr};`
353			`dmem_wait <= #1 1'b1;`
354			`end`
355			`OC8051_MAS_DPTR_W: begin // write to external rom: (dptr)=acc
356			`dwe_o <= #1 1'b1;`
357			`dstb_o <= #1 1'b1;`
358			`ddat_o <= #1 acc;`
359			`dadr_ot <= #1 {7'h0, dptr};`
360			`dmem_wait <= #1 1'b1;`
361			`end`
362			`OC8051_MAS_RI_R: begin // read from external rom: acc=(Ri)
363			`dwe_o <= #1 1'b0;`
364			`dstb_o <= #1 1'b1;`
365			`ddat_o <= #1 8'h00;`
366			`dadr_ot <= #1 {15'h0, ri};`
367			`dmem_wait <= #1 1'b1;`
368			`end`
369			`OC8051_MAS_RI_W: begin // write to external rom: (Ri)=acc
370			`dwe_o <= #1 1'b1;`
371			`dstb_o <= #1 1'b1;`
372			`ddat_o <= #1 acc;`
373			`dadr_ot <= #1 {15'h0, ri};`
374			`dmem_wait <= #1 1'b1;`
375			`end`
376			`endcase`
377			`end`
378			`end`
379
380			`/////////////////////////////`
381			`//`
382			`// op_select`
383			`//`
384			`/////////////////////////////`
385
386
387			`assign op1 = ea_rom_sel ? op1_i: op1_xt;`
388			`assign op2 = ea_rom_sel ? op2_i: op2_xt;`
389			`assign op3 = ea_rom_sel ? op3_i: op3_xt;`
390
391
392			`always @(dack_ir or ddat_ir or op1_o or iram_out)`
393			`if (dack_ir)`
394			`op1_out = ddat_ir;`
395			`else`
396			`op1_out = op1_o;`
397
398			`assign op3_out = (rd) ? op3_o : op3_buff;`
399			`assign op2_out = (rd) ? op2_o : op2_buff;`
400
401			`always @(idat_i or iack_i or idat_ir or rd)`
402			`begin`
403			`if (iack_i) begin`
404			`op1_xt = idat_i[31:24];`
405			`op2_xt = idat_i[23:16];`
406			`op3_xt = idat_i[15:8];`
407			`end else if (!rd) begin`
408			`op1_xt = idat_ir[23:16];`
409			`op2_xt = idat_ir[15:8];`
410			`op3_xt = idat_ir[7:0];`
411			`end else begin`
412			`op1_xt = 8'h00;`
413			`op2_xt = 8'h00;`
414			`op3_xt = 8'h00;`
415			`end`
416			`end`
417
418
419			`//`
420			`// in case of interrupts`
421			`always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)`
422			`begin`
423			`if (int_ack_t && (iack_i \|\| ea_rom_sel)) begin`
424			op1_o = `OC8051_LCALL;
425			`op2_o = 8'h00;`
426			`op3_o = int_vec_buff;`
427			`end else begin`
428			`op1_o = op1;`
429			`op2_o = op2;`
430			`op3_o = op3;`
431			`end`
432			`end`
433
434			`//`
435			`//in case of reti`
436			`always @(posedge clk or posedge rst)`
437			`if (rst) reti <= #1 1'b0;`
438			else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
439			`else reti <= #1 1'b0;`
440
441			`//`
442			`// remember inputs`
443			`always @(posedge clk or posedge rst)`
444			`begin`
445			`if (rst) begin`
446			`op2_buff <= #1 8'h0;`
447			`op3_buff <= #1 8'h0;`
448			`end else if (rd) begin`
449			`op2_buff <= #1 op2_o;`
450			`op3_buff <= #1 op3_o;`
451			`end`
452			`end`
453
454			`//`
455			`// remember interrupt`
456			`// we don't want to interrupt instruction in the middle of execution`
457			`always @(posedge clk or posedge rst)`
458			`if (rst) begin`
459			`int_ack_t <= #1 1'b0;`
460			`int_vec_buff <= #1 8'h00;`
461			`end else if (intr) begin`
462			`int_ack_t <= #1 1'b1;`
463			`int_vec_buff <= #1 int_v;`
464			`end else if (rd && (ea_rom_sel \|\| iack_i)) int_ack_t <= #1 1'b0;`
465
466			`always @(posedge clk or posedge rst)`
467			`if (rst) int_ack_buff <= #1 1'b0;`
468			`else int_ack_buff <= #1 int_ack_t;`
469
470			`always @(posedge clk or posedge rst)`
471			`if (rst) int_ack <= #1 1'b0;`
472			`else begin`
473			`if ((int_ack_buff) & !(int_ack_t))`
474			`int_ack <= #1 1'b1;`
475			`else int_ack <= #1 1'b0;`
476			`end`
477
478
479			`/////////////////////////////`
480			`//`
481			`// pc`
482			`//`
483			`/////////////////////////////`
484
485			`always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or alu[7:0] or ea_rom_sel or iack_i)`
486			`begin`
487			`if (int_buff \|\| int_buff1) begin`
488			`//`
489			`//in case of interrupt hold valut, to be written to stack`
490			`pc= pc_buf;`
491			`// end else if (pis_l) begin`
492			`// pc = {pc_buf[22:8], alu[7:0]};`
493			`end else if (pc_wait) begin`
494			`casex (op1_out)`
495			`OC8051_ACALL : pc= pc_buf + 23'h2;
496			`OC8051_AJMP : pc= pc_buf + 23'h2;
497
498			`//op_code [7:3]`
499			`OC8051_CJNE_R : pc= pc_buf + 23'h3;
500			`OC8051_DJNZ_R : pc= pc_buf + 23'h2;
501			`OC8051_MOV_DR : pc= pc_buf + 23'h2;
502			`OC8051_MOV_CR : pc= pc_buf + 23'h2;
503			`OC8051_MOV_RD : pc= pc_buf + 23'h2;
504
505			`//op_code [7:1]`
506			`OC8051_CJNE_I : pc= pc_buf + 23'h3;
507			`OC8051_MOV_ID : pc= pc_buf + 23'h2;
508			`OC8051_MOV_DI : pc= pc_buf + 23'h2;
509			`OC8051_MOV_CI : pc= pc_buf + 23'h2;
510
511			`//op_code [7:0]`
512			`OC8051_ADD_D : pc= pc_buf + 23'h2;
513			`OC8051_ADD_C : pc= pc_buf + 23'h2;
514			`OC8051_ADDC_D : pc= pc_buf + 23'h2;
515			`OC8051_ADDC_C : pc= pc_buf + 23'h2;
516			`OC8051_ANL_D : pc= pc_buf + 23'h2;
517			`OC8051_ANL_C : pc= pc_buf + 23'h2;
518			`OC8051_ANL_DD : pc= pc_buf + 23'h2;
519			`OC8051_ANL_DC : pc= pc_buf + 23'h3;
520			`OC8051_ANL_B : pc= pc_buf + 23'h2;
521			`OC8051_ANL_NB : pc= pc_buf + 23'h2;
522			`OC8051_CJNE_D : pc= pc_buf + 23'h3;
523			`OC8051_CJNE_C : pc= pc_buf + 23'h3;
524			`OC8051_CLR_B : pc= pc_buf + 23'h2;
525			`OC8051_CPL_B : pc= pc_buf + 23'h2;
526			`OC8051_DEC_D : pc= pc_buf + 23'h2;
527			`OC8051_DJNZ_D : pc= pc_buf + 23'h3;
528			`OC8051_INC_D : pc= pc_buf + 23'h2;
529			`OC8051_JB : pc= pc_buf + 23'h3;
530			`OC8051_JBC : pc= pc_buf + 23'h3;
531			`OC8051_JC : pc= pc_buf + 23'h2;
532			`OC8051_JNB : pc= pc_buf + 23'h3;
533			`OC8051_JNC : pc= pc_buf + 23'h2;
534			`OC8051_JNZ : pc= pc_buf + 23'h2;
535			`OC8051_JZ : pc= pc_buf + 23'h2;
536			`OC8051_LCALL :pc= pc_buf + 23'h3;
537			`OC8051_LJMP : pc= pc_buf + 23'h3;
538			`OC8051_MOV_D : pc= pc_buf + 23'h2;
539			`OC8051_MOV_C : pc= pc_buf + 23'h2;
540			`OC8051_MOV_DA : pc= pc_buf + 23'h2;
541			`OC8051_MOV_DD : pc= pc_buf + 23'h3;
542			`OC8051_MOV_CD : pc= pc_buf + 23'h3;
543			`OC8051_MOV_BC : pc= pc_buf + 23'h2;
544			`OC8051_MOV_CB : pc= pc_buf + 23'h2;
545			`OC8051_MOV_DP : pc= pc_buf + 23'h3;
546			`OC8051_ORL_D : pc= pc_buf + 23'h2;
547			`OC8051_ORL_C : pc= pc_buf + 23'h2;
548			`OC8051_ORL_AD : pc= pc_buf + 23'h2;
549			`OC8051_ORL_CD : pc= pc_buf + 23'h3;
550			`OC8051_ORL_B : pc= pc_buf + 23'h2;
551			`OC8051_ORL_NB : pc= pc_buf + 23'h2;
552			`OC8051_POP : pc= pc_buf + 23'h2;
553			`OC8051_PUSH : pc= pc_buf + 23'h2;
554			`OC8051_SETB_B : pc= pc_buf + 23'h2;
555			`OC8051_SJMP : pc= pc_buf + 23'h2;
556			`OC8051_SUBB_D : pc= pc_buf + 23'h2;
557			`OC8051_SUBB_C : pc= pc_buf + 23'h2;
558			`OC8051_XCH_D : pc= pc_buf + 23'h2;
559			`OC8051_XRL_D : pc= pc_buf + 23'h2;
560			`OC8051_XRL_C : pc= pc_buf + 23'h2;
561			`OC8051_XRL_AD : pc= pc_buf + 23'h2;
562			`OC8051_XRL_CD : pc= pc_buf + 23'h3;
563			`default: pc= pc_buf + 23'h1;`
564			`endcase`
565			`//`
566			`//in case of instructions that use more than one clock hold current pc`
567			`end else begin`
568			`pc= pc_buf;`
569			`end`
570			`end`
571
572
573			`//`
574			`//interrupt buffer`
575			`always @(posedge clk or posedge rst)`
576			`if (rst) begin`
577			`int_buff1 <= #1 1'b0;`
578			`end else begin`
579			`int_buff1 <= #1 int_buff;`
580			`end`
581
582			`always @(posedge clk or posedge rst)`
583			`if (rst) begin`
584			`int_buff <= #1 1'b0;`
585			`end else if (intr) begin`
586			`int_buff <= #1 1'b1;`
587			`end else if (pc_wait)`
588			`int_buff <= #1 1'b0;`
589
590
591			`always @(posedge clk or posedge rst)`
592			`begin`
593			`if (rst) begin`
594			pc_buf <= #1 `OC8051_RST_PC;
595			`end else begin`
596			`if (pc_wr) begin`
597			`//`
598			`//case of writing new value to pc (jupms)`
599			`case (pc_wr_sel)`
600			`OC8051_PIS_ALU: pc_buf <= #1 alu;
601			`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
602			`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
603			`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
604			`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
605			`endcase`
606			`end else`
607			`//`
608			`//or just remember current`
609			`pc_buf <= #1 pc;`
610			`end`
611			`end`
612
613
614			`always @(posedge clk or posedge rst)`
615			`if (rst)`
616			`ddat_ir <= #1 8'h00;`
617			`else if (dack_i)`
618			`ddat_ir <= #1 ddat_i;`
619
620			`////////////////////////`
621			`always @(posedge clk or posedge rst)`
622			`if (rst) begin`
623			`rn_r <= #1 5'd0;`
624			`ri_r <= #1 8'h00;`
625			`imm_r <= #1 8'h00;`
626			`imm2_r <= #1 8'h00;`
627			`rd_addr_r <= #1 3'h0;`
628			`op1_r <= #1 8'h0;`
629			`dack_ir <= #1 1'b0;`
630			`sp_r <= #1 1'b0;`
631			`end else begin`
632			`rn_r <= #1 rn;`
633			`ri_r <= #1 ri;`
634			`imm_r <= #1 imm;`
635			`imm2_r <= #1 imm2;`
636			`rd_addr_r <= #1 rd_addr[7:5];`
637			`op1_r <= #1 op1_out;`
638			`dack_ir <= #1 dack_i;`
639			`sp_r <= #1 sp;`
640			`end`
641
642
643			`endmodule`