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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_ports.v] - Blame information for rev 186

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 port output                                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   8051 special function registers: port 0:3 - output         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.7  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.6  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_ports (clk,
                    rst,
                    bit_in,
                    data_in,
                    wr,
                    wr_bit,
                    wr_addr,
 
        `ifdef OC8051_PORT0
                    p0_out,
                    p0_in,
                    p0_data,
        `endif
 
        `ifdef OC8051_PORT1
                    p1_out,
                    p1_in,
                    p1_data,
 
        `endif
 
        `ifdef OC8051_PORT2
                    p2_out,
                    p2_in,
                    p2_data,
        `endif
 
        `ifdef OC8051_PORT3
                    p3_out,
                    p3_in,
                    p3_data,
        `endif
 
                    rmw);
 
input        clk,       //clock
             rst,       //reset
             wr,        //write [oc8051_decoder.wr -r]
             wr_bit,    //write bit addresable [oc8051_decoder.bit_addr -r]
             bit_in,    //bit input [oc8051_alu.desCy]
             rmw;       //read modify write feature [oc8051_decoder.rmw]
input [7:0]  wr_addr,    //write address [oc8051_ram_wr_sel.out]
             data_in;   //data input (from alu destiantion 1) [oc8051_alu.des1]
 
`ifdef OC8051_PORT0
  input  [7:0] p0_in;
  output [7:0] p0_out,
               p0_data;
  reg    [7:0] p0_out;
 
  assign p0_data = rmw ? p0_out : p0_in;
`endif
 
 
`ifdef OC8051_PORT1
  input  [7:0] p1_in;
  output [7:0] p1_out,
               p1_data;
  reg    [7:0] p1_out;
 
  assign p1_data = rmw ? p1_out : p1_in;
`endif
 
 
`ifdef OC8051_PORT2
  input  [7:0] p2_in;
  output [7:0] p2_out,
               p2_data;
  reg    [7:0] p2_out;
 
  assign p2_data = rmw ? p2_out : p2_in;
`endif
 
 
`ifdef OC8051_PORT3
  input  [7:0] p3_in;
  output [7:0] p3_out,
               p3_data;
  reg    [7:0] p3_out;
 
  assign p3_data = rmw ? p3_out : p3_in;
`endif
 
//
// case of writing to port
always @(posedge clk or posedge rst)
begin
  if (rst) begin
`ifdef OC8051_PORT0
    p0_out <= #1 `OC8051_RST_P0;
`endif
 
`ifdef OC8051_PORT1
    p1_out <= #1 `OC8051_RST_P1;
`endif
 
`ifdef OC8051_PORT2
    p2_out <= #1 `OC8051_RST_P2;
`endif
 
`ifdef OC8051_PORT3
    p3_out <= #1 `OC8051_RST_P3;
`endif
  end else if (wr) begin
    if (!wr_bit) begin
      case (wr_addr)
//
// bytaddresable
`ifdef OC8051_PORT0
        `OC8051_SFR_P0: p0_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT1
        `OC8051_SFR_P1: p1_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT2
        `OC8051_SFR_P2: p2_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT3
        `OC8051_SFR_P3: p3_out <= #1 data_in;
`endif
      endcase
    end else begin
      case (wr_addr[7:3])
 
//
// bit addressable
`ifdef OC8051_PORT0
        `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT1
        `OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT2
        `OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT3
        `OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
`endif
      endcase
    end
  end
end
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 port output ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 special function registers: port 0:3 - output ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	120	simont	`// Revision 1.8 2003/04/07 14:58:02 simont`
48			`// change sfr's interface.`
49			`//`
50	116	simont	`// Revision 1.7 2003/01/13 14:14:41 simont`
51			`// replace some modules`
52			`//`
53	82	simont	`// Revision 1.6 2002/09/30 17:33:59 simont`
54			`// prepared header`
55			`//`
56			`//`
57
58
59			`// synopsys translate_off`
60			`include "oc8051_timescale.v"
61			`// synopsys translate_on`
62
63			`include "oc8051_defines.v"
64
65
66	120	simont	`module oc8051_ports (clk,`
67			`rst,`
68			`bit_in,`
69			`data_in,`
70			`wr,`
71			`wr_bit,`
72			`wr_addr,`
73	82	simont
74	120	simont	`ifdef OC8051_PORT0
75			`p0_out,`
76			`p0_in,`
77			`p0_data,`
78			`endif
79	82	simont
80	120	simont	`ifdef OC8051_PORT1
81			`p1_out,`
82			`p1_in,`
83			`p1_data,`
84	82	simont
85	120	simont	`endif
86	82	simont
87	120	simont	`ifdef OC8051_PORT2
88			`p2_out,`
89			`p2_in,`
90			`p2_data,`
91			`endif
92	82	simont
93	120	simont	`ifdef OC8051_PORT3
94			`p3_out,`
95			`p3_in,`
96			`p3_data,`
97			`endif
98	116	simont
99	120	simont	`rmw);`
100
101			`input clk, //clock`
102			`rst, //reset`
103			`wr, //write [oc8051_decoder.wr -r]`
104			`wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]`
105			`bit_in, //bit input [oc8051_alu.desCy]`
106			`rmw; //read modify write feature [oc8051_decoder.rmw]`
107			`input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]`
108			`data_in; //data input (from alu destiantion 1) [oc8051_alu.des1]`
109
110			`ifdef OC8051_PORT0
111			`input [7:0] p0_in;`
112			`output [7:0] p0_out,`
113			`p0_data;`
114			`reg [7:0] p0_out;`
115
116			`assign p0_data = rmw ? p0_out : p0_in;`
117			`endif
118
119
120			`ifdef OC8051_PORT1
121			`input [7:0] p1_in;`
122			`output [7:0] p1_out,`
123			`p1_data;`
124			`reg [7:0] p1_out;`
125
126			`assign p1_data = rmw ? p1_out : p1_in;`
127			`endif
128
129
130			`ifdef OC8051_PORT2
131			`input [7:0] p2_in;`
132			`output [7:0] p2_out,`
133			`p2_data;`
134			`reg [7:0] p2_out;`
135
136			`assign p2_data = rmw ? p2_out : p2_in;`
137			`endif
138
139
140			`ifdef OC8051_PORT3
141			`input [7:0] p3_in;`
142			`output [7:0] p3_out,`
143			`p3_data;`
144			`reg [7:0] p3_out;`
145
146			`assign p3_data = rmw ? p3_out : p3_in;`
147			`endif
148
149	82	simont	`//`
150			`// case of writing to port`
151			`always @(posedge clk or posedge rst)`
152			`begin`
153			`if (rst) begin`
154	120	simont	`ifdef OC8051_PORT0
155	82	simont	p0_out <= #1 `OC8051_RST_P0;
156	120	simont	`endif
157
158			`ifdef OC8051_PORT1
159	82	simont	p1_out <= #1 `OC8051_RST_P1;
160	120	simont	`endif
161
162			`ifdef OC8051_PORT2
163	82	simont	p2_out <= #1 `OC8051_RST_P2;
164	120	simont	`endif
165
166			`ifdef OC8051_PORT3
167	82	simont	p3_out <= #1 `OC8051_RST_P3;
168	120	simont	`endif
169	82	simont	`end else if (wr) begin`
170			`if (!wr_bit) begin`
171			`case (wr_addr)`
172			`//`
173			`// bytaddresable`
174	120	simont	`ifdef OC8051_PORT0
175	82	simont	`OC8051_SFR_P0: p0_out <= #1 data_in;
176	120	simont	`endif
177
178			`ifdef OC8051_PORT1
179	82	simont	`OC8051_SFR_P1: p1_out <= #1 data_in;
180	120	simont	`endif
181
182			`ifdef OC8051_PORT2
183	82	simont	`OC8051_SFR_P2: p2_out <= #1 data_in;
184	120	simont	`endif
185
186			`ifdef OC8051_PORT3
187	82	simont	`OC8051_SFR_P3: p3_out <= #1 data_in;
188	120	simont	`endif
189	82	simont	`endcase`
190			`end else begin`
191			`case (wr_addr[7:3])`
192
193			`//`
194			`// bit addressable`
195	120	simont	`ifdef OC8051_PORT0
196	82	simont	`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
197	120	simont	`endif
198
199			`ifdef OC8051_PORT1
200	82	simont	`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
201	120	simont	`endif
202
203			`ifdef OC8051_PORT2
204	82	simont	`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
205	120	simont	`endif
206
207			`ifdef OC8051_PORT3
208	82	simont	`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
209	120	simont	`endif
210	82	simont	`endcase`
211			`end`
212			`end`
213			`end`
214
215
216			`endmodule`
217

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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_ports.v] - Blame information for rev 186