URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_sfr.v] - Blame information for rev 186

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores sfr top level module                             ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   special function registers for oc8051                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.12  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.11  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.10  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.9  2003/04/09 16:24:03  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.8  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/07 13:29:16  simont
// change uart to meet timing.
//
// Revision 1.5  2003/04/04 10:35:07  simont
// signal prsc_ow added.
//
// Revision 1.4  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.3  2003/01/21 13:51:30  simont
// add include oc8051_defines.v
//
// Revision 1.2  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.1  2002/11/05 17:22:27  simont
// initial import
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_sfr (rst, clk,
       adr0, adr1, dat0,
       dat1, dat2, bit_in,
       des_acc,
       we, wr_bit,
       bit_out,
       wr_sfr, acc,
       ram_wr_sel, ram_rd_sel,
       sp, sp_w,
       bank_sel,
       desAc, desOv,
       srcAc, cy,
       psw_set, rmw,
       comp_sel,
       comp_wait,
 
`ifdef OC8051_PORTS
 
  `ifdef OC8051_PORT0
       p0_out,
       p0_in,
  `endif
 
  `ifdef OC8051_PORT1
       p1_out,
       p1_in,
  `endif
 
  `ifdef OC8051_PORT2
       p2_out,
       p2_in,
  `endif
 
  `ifdef OC8051_PORT3
       p3_out,
       p3_in,
  `endif
 
`endif
 
 
  `ifdef OC8051_UART
       rxd, txd,
  `endif
 
       int_ack, intr,
       int0, int1,
       int_src,
       reti,
 
  `ifdef OC8051_TC01
       t0, t1,
  `endif
 
  `ifdef OC8051_TC2
       t2, t2ex,
  `endif
 
       dptr_hi, dptr_lo,
       wait_data);
 
 
input       rst,        // reset - pin
            clk,        // clock - pin
            we,         // write enable
            bit_in,
            desAc,
            desOv,
            rmw;
input       int_ack,
            int0,
            int1,
            reti,
            wr_bit;
input [1:0] psw_set,
            wr_sfr,
            comp_sel;
input [2:0] ram_rd_sel,
            ram_wr_sel;
input [7:0] adr0,        //address 0 input
            adr1,       //address 1 input
            des_acc,
            dat1,       //data 1 input (des1)
            dat2;       //data 2 input (des2)
 
output       bit_out,
             intr,
             srcAc,
             cy,
             wait_data,
             comp_wait;
output [1:0] bank_sel;
output [7:0] dat0,       //data output
             int_src,
             dptr_hi,
             dptr_lo,
             acc;
output [7:0] sp,
             sp_w;
 
// ports
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0] p0_in;
output [7:0] p0_out;
wire   [7:0] p0_data;
`endif
 
`ifdef OC8051_PORT1
input  [7:0] p1_in;
output [7:0] p1_out;
wire   [7:0] p1_data;
`endif
 
`ifdef OC8051_PORT2
input  [7:0] p2_in;
output [7:0] p2_out;
wire   [7:0] p2_data;
`endif
 
`ifdef OC8051_PORT3
input  [7:0] p3_in;
output [7:0] p3_out;
wire   [7:0] p3_data;
`endif
 
`endif
 
 
// serial interface
`ifdef OC8051_UART
input        rxd;
output       txd;
`endif
 
// timer/counter 0,1
`ifdef OC8051_TC01
input        t0, t1;
`endif
 
// timer/counter 2
`ifdef OC8051_TC2
input        t2, t2ex;
`endif
 
reg        bit_out,
           wait_data;
reg [7:0]  dat0,
           adr0_r;
 
reg        wr_bit_r;
reg [2:0]  ram_wr_sel_r;
 
 
wire       p,
           uart_int,
           tf0,
           tf1,
           tr0,
           tr1,
           rclk,
           tclk,
           brate2,
           tc2_int;
 
 
wire [7:0] b_reg,
           psw,
 
`ifdef OC8051_TC2
  // t/c 2
           t2con,
           tl2,
           th2,
           rcap2l,
           rcap2h,
`endif
 
`ifdef OC8051_TC01
  // t/c 0,1
           tmod,
           tl0,
           th0,
           tl1,
           th1,
`endif
 
  // serial interface
`ifdef OC8051_UART
           scon,
           pcon,
           sbuf,
`endif
 
  //interrupt control
           ie,
           tcon,
           ip;
 
 
reg        pres_ow;
reg [3:0]  prescaler;
 
 
assign cy = psw[7];
assign srcAc = psw [6];
 
 
 
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk),
                       .rst(rst),
                       .bit_in(bit_in),
                       .data_in(des_acc),
                       .data2_in(dat2),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .wr_sfr(wr_sfr),
                       .wr_addr(adr1),
                       .data_out(acc),
                       .p(p));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk),
                                     .rst(rst),
                                     .bit_in(bit_in),
                                     .data_in(des_acc),
                                     .wr(we),
                                     .wr_bit(wr_bit_r),
                                     .wr_addr(adr1),
                                     .data_out(b_reg));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk),
                     .rst(rst),
                     .ram_rd_sel(ram_rd_sel),
                     .ram_wr_sel(ram_wr_sel),
                     .wr_addr(adr1),
                     .wr(we),
                     .wr_bit(wr_bit_r),
                     .data_in(dat1),
                     .sp_out(sp),
                     .sp_w(sp_w));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk),
                         .rst(rst),
                         .addr(adr1),
                         .data_in(des_acc),
                         .data2_in(dat2),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .data_hi(dptr_hi),
                         .data_lo(dptr_lo),
                         .wr_sfr(wr_sfr));
 
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk),
                        .rst(rst),
                        .wr_addr(adr1),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .data_out(psw),
                        .p(p),
                        .cy_in(bit_in),
                        .ac_in(desAc),
                        .ov_in(desOv),
                        .set(psw_set),
                        .bank_sel(bank_sel));
 
//
// ports
// P0, P1, P2, P3
`ifdef OC8051_PORTS
  oc8051_ports oc8051_ports1(.clk(clk),
                           .rst(rst),
                           .bit_in(bit_in),
                           .data_in(dat1),
                           .wr(we),
                           .wr_bit(wr_bit_r),
                           .wr_addr(adr1),
 
                `ifdef OC8051_PORT0
                           .p0_out(p0_out),
                           .p0_in(p0_in),
                           .p0_data(p0_data),
                `endif
 
                `ifdef OC8051_PORT1
                           .p1_out(p1_out),
                           .p1_in(p1_in),
                           .p1_data(p1_data),
                `endif
 
                `ifdef OC8051_PORT2
                           .p2_out(p2_out),
                           .p2_in(p2_in),
                           .p2_data(p2_data),
                `endif
 
                `ifdef OC8051_PORT3
                           .p3_out(p3_out),
                           .p3_in(p3_in),
                           .p3_data(p3_data),
                `endif
 
                           .rmw(rmw));
`endif
 
//
// serial interface
// SCON, SBUF
`ifdef OC8051_UART
  oc8051_uart oc8051_uatr1 (.clk(clk),
                            .rst(rst),
                            .bit_in(bit_in),
                            .data_in(dat1),
                            .wr(we),
                            .wr_bit(wr_bit_r),
                            .wr_addr(adr1),
                            .rxd(rxd),
                            .txd(txd),
                // interrupt
                            .intr(uart_int),
                // baud rate sources
                            .brate2(brate2),
                            .t1_ow(tf1),
                            .pres_ow(pres_ow),
                            .rclk(rclk),
                            .tclk(tclk),
                //registers
                            .scon(scon),
                            .pcon(pcon),
                            .sbuf(sbuf));
`else
  assign uart_int = 1'b0;
`endif
 
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk),
                        .rst(rst),
                        .wr_addr(adr1),
                        .bit_in(bit_in),
                        .ack(int_ack),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .tf0(tf0),
                        .tf1(tf1),
                        .t2_int(tc2_int),
                        .tr0(tr0),
                        .tr1(tr1),
                        .ie0(int0),
                        .ie1(int1),
                        .uart_int(uart_int),
                        .reti(reti),
                        .intr(intr),
                        .int_vec(int_src),
                        .ie(ie),
                        .tcon(tcon),
                        .ip(ip));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
`ifdef OC8051_TC01
  oc8051_tc oc8051_tc1(.clk(clk),
                       .rst(rst),
                       .wr_addr(adr1),
                       .data_in(dat1),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .ie0(int0),
                       .ie1(int1),
                       .tr0(tr0),
                       .tr1(tr1),
                       .t0(t0),
                       .t1(t1),
                       .tf0(tf0),
                       .tf1(tf1),
                       .pres_ow(pres_ow),
                       .tmod(tmod),
                       .tl0(tl0),
                       .th0(th0),
                       .tl1(tl1),
                       .th1(th1));
`else
  assign tf0 = 1'b0;
  assign tf1 = 1'b0;
`endif
 
//
// timer/counter 2
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
`ifdef OC8051_TC2
  oc8051_tc2 oc8051_tc21(.clk(clk),
                         .rst(rst),
                         .wr_addr(adr1),
                         .data_in(dat1),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .bit_in(bit_in),
                         .t2(t2),
                         .t2ex(t2ex),
                         .rclk(rclk),
                         .tclk(tclk),
                         .brate2(brate2),
                         .tc2_int(tc2_int),
                         .pres_ow(pres_ow),
                         .t2con(t2con),
                         .tl2(tl2),
                         .th2(th2),
                         .rcap2l(rcap2l),
                         .rcap2h(rcap2h));
`else
  assign tc2_int = 1'b0;
  assign rclk    = 1'b0;
  assign tclk    = 1'b0;
  assign brate2  = 1'b0;
`endif
 
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    adr0_r <= #1 8'h00;
    ram_wr_sel_r <= #1 3'b000;
    wr_bit_r <= #1 1'b0;
//    wait_data <= #1 1'b0;
  end else begin
    adr0_r <= #1 adr0;
    ram_wr_sel_r <= #1 ram_wr_sel;
    wr_bit_r <= #1 wr_bit;
  end
 
assign comp_wait = !(
                    ((comp_sel==`OC8051_CSS_AZ) &
                       ((wr_sfr==`OC8051_WRS_ACC1) |
                        (wr_sfr==`OC8051_WRS_ACC2) |
                        ((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_CY) &
                       ((|psw_set) |
                        ((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_BIT) &
                       ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
                       ((adr1==adr0) & adr1[7] & we & !wr_bit_r)));
 
 
 
//
//set output in case of address (byte)
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    dat0 <= #1 8'h00;
    wait_data <= #1 1'b0;
  end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin                          //write and read same address
    dat0 <= #1 des_acc;
    wait_data <= #1 1'b0;
  end else if (
      (
        ((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) |        //write to acc
//        ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) |  //write to dpl
        (adr1[7] & (adr1==adr0) & we & !wr_bit_r) |                     //write and read same address
        (adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) &  we & wr_bit_r) //write bit addressable to read address
      ) & !wait_data) begin
    wait_data <= #1 1'b1;
 
  end else if ((
      ((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
      ((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) |  //write to acc
      ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI))        //write to dph
      ) & !wait_data) begin
    wait_data <= #1 1'b1;
 
  end else begin
    case (adr0)
      `OC8051_SFR_ACC:          dat0 <= #1 acc;
      `OC8051_SFR_PSW:          dat0 <= #1 psw;
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_P0:           dat0 <= #1 p0_data;
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_P1:           dat0 <= #1 p1_data;
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_P2:           dat0 <= #1 p2_data;
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_P3:           dat0 <= #1 p3_data;
  `endif
`endif
 
      `OC8051_SFR_SP:           dat0 <= #1 sp;
      `OC8051_SFR_B:            dat0 <= #1 b_reg;
      `OC8051_SFR_DPTR_HI:      dat0 <= #1 dptr_hi;
      `OC8051_SFR_DPTR_LO:      dat0 <= #1 dptr_lo;
 
`ifdef OC8051_UART
      `OC8051_SFR_SCON:         dat0 <= #1 scon;
      `OC8051_SFR_SBUF:         dat0 <= #1 sbuf;
      `OC8051_SFR_PCON:         dat0 <= #1 pcon;
`endif
 
`ifdef OC8051_TC01
      `OC8051_SFR_TH0:          dat0 <= #1 th0;
      `OC8051_SFR_TH1:          dat0 <= #1 th1;
      `OC8051_SFR_TL0:          dat0 <= #1 tl0;
      `OC8051_SFR_TL1:          dat0 <= #1 tl1;
      `OC8051_SFR_TMOD:         dat0 <= #1 tmod;
`endif
 
      `OC8051_SFR_IP:           dat0 <= #1 ip;
      `OC8051_SFR_IE:           dat0 <= #1 ie;
      `OC8051_SFR_TCON:         dat0 <= #1 tcon;
 
`ifdef OC8051_TC2
      `OC8051_SFR_RCAP2H:       dat0 <= #1 rcap2h;
      `OC8051_SFR_RCAP2L:       dat0 <= #1 rcap2l;
      `OC8051_SFR_TH2:          dat0 <= #1 th2;
      `OC8051_SFR_TL2:          dat0 <= #1 tl2;
      `OC8051_SFR_T2CON:        dat0 <= #1 t2con;
`endif
 
      default:                  dat0 <= #1 8'h00;
    endcase
    wait_data <= #1 1'b0;
  end
end
 
 
//
//set output in case of address (bit)
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    bit_out <= #1 1'h0;
  else if (
          ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
          ((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC))         //write to acc
          )
 
    bit_out <= #1 dat1[adr0[2:0]];
  else if ((adr1==adr0) & we & wr_bit_r)
    bit_out <= #1 bit_in;
  else
    case (adr0[7:3])
      `OC8051_SFR_B_ACC:   bit_out <= #1 acc[adr0[2:0]];
      `OC8051_SFR_B_PSW:   bit_out <= #1 psw[adr0[2:0]];
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_B_P0:    bit_out <= #1 p0_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_B_P1:    bit_out <= #1 p1_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_B_P2:    bit_out <= #1 p2_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_B_P3:    bit_out <= #1 p3_data[adr0[2:0]];
  `endif
`endif
 
      `OC8051_SFR_B_B:     bit_out <= #1 b_reg[adr0[2:0]];
      `OC8051_SFR_B_IP:    bit_out <= #1 ip[adr0[2:0]];
      `OC8051_SFR_B_IE:    bit_out <= #1 ie[adr0[2:0]];
      `OC8051_SFR_B_TCON:  bit_out <= #1 tcon[adr0[2:0]];
 
`ifdef OC8051_UART
      `OC8051_SFR_B_SCON:  bit_out <= #1 scon[adr0[2:0]];
`endif
 
`ifdef OC8051_TC2
      `OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
`endif
 
      default:             bit_out <= #1 1'b0;
    endcase
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    prescaler <= #1 4'h0;
    pres_ow <= #1 1'b0;
  end else if (prescaler==4'b1011) begin
    prescaler <= #1 4'h0;
    pres_ow <= #1 1'b1;
  end else begin
    prescaler <= #1 prescaler + 4'h1;
    pres_ow <= #1 1'b0;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	75	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores sfr top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// special function registers for oc8051 ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	145	simont	`// Revision 1.13 2003/05/05 15:46:37 simont`
48			`// add aditional alu destination to solve critical path.`
49			`//`
50	139	simont	`// Revision 1.12 2003/04/29 11:24:31 simont`
51			`// fix bug in case execution of two data dependent instructions.`
52			`//`
53	134	simont	`// Revision 1.11 2003/04/25 17:15:51 simont`
54			`// change branch instruction execution (reduse needed clock periods).`
55			`//`
56	132	simont	`// Revision 1.10 2003/04/10 12:43:19 simont`
57			`// defines for pherypherals added`
58			`//`
59	120	simont	`// Revision 1.9 2003/04/09 16:24:03 simont`
60			`// change wr_sft to 2 bit wire.`
61			`//`
62	118	simont	`// Revision 1.8 2003/04/09 15:49:42 simont`
63			`// Register oc8051_sfr dato output, add signal wait_data.`
64			`//`
65	117	simont	`// Revision 1.7 2003/04/07 14:58:02 simont`
66			`// change sfr's interface.`
67			`//`
68	116	simont	`// Revision 1.6 2003/04/07 13:29:16 simont`
69			`// change uart to meet timing.`
70			`//`
71	115	simont	`// Revision 1.5 2003/04/04 10:35:07 simont`
72			`// signal prsc_ow added.`
73			`//`
74	113	simont	`// Revision 1.4 2003/03/28 17:45:57 simont`
75			`// change module name.`
76			`//`
77	90	simont	`// Revision 1.3 2003/01/21 13:51:30 simont`
78			`// add include oc8051_defines.v`
79			`//`
80	87	simont	`// Revision 1.2 2003/01/13 14:14:41 simont`
81			`// replace some modules`
82			`//`
83	82	simont	`// Revision 1.1 2002/11/05 17:22:27 simont`
84			`// initial import`
85	75	simont	`//`
86	82	simont	`//`
87	75	simont
88			`// synopsys translate_off`
89			`include "oc8051_timescale.v"
90			`// synopsys translate_on`
91
92	87	simont	`include "oc8051_defines.v"
93	75	simont
94	87	simont
95	120	simont	`module oc8051_sfr (rst, clk,`
96	117	simont	`adr0, adr1, dat0,`
97	120	simont	`dat1, dat2, bit_in,`
98	139	simont	`des_acc,`
99	120	simont	`we, wr_bit,`
100	117	simont	`bit_out,`
101	120	simont	`wr_sfr, acc,`
102			`ram_wr_sel, ram_rd_sel,`
103			`sp, sp_w,`
104			`bank_sel,`
105	139	simont	`desAc, desOv,`
106	120	simont	`srcAc, cy,`
107			`psw_set, rmw,`
108	132	simont	`comp_sel,`
109			`comp_wait,`
110	75	simont
111	120	simont	`ifdef OC8051_PORTS
112	75	simont
113	120	simont	`ifdef OC8051_PORT0
114			`p0_out,`
115			`p0_in,`
116			`endif
117	75	simont
118	120	simont	`ifdef OC8051_PORT1
119			`p1_out,`
120			`p1_in,`
121			`endif
122	75	simont
123	120	simont	`ifdef OC8051_PORT2
124			`p2_out,`
125			`p2_in,`
126			`endif
127	75	simont
128	120	simont	`ifdef OC8051_PORT3
129			`p3_out,`
130			`p3_in,`
131			`endif
132
133			`endif
134
135
136			`ifdef OC8051_UART
137			`rxd, txd,`
138			`endif
139
140			`int_ack, intr,`
141			`int0, int1,`
142			`int_src,`
143			`reti,`
144
145			`ifdef OC8051_TC01
146			`t0, t1,`
147			`endif
148
149			`ifdef OC8051_TC2
150			`t2, t2ex,`
151			`endif
152
153			`dptr_hi, dptr_lo,`
154			`wait_data);`
155
156
157			`input rst, // reset - pin`
158			`clk, // clock - pin`
159			`we, // write enable`
160			`bit_in,`
161			`desAc,`
162			`desOv,`
163			`rmw;`
164			`input int_ack,`
165			`int0,`
166			`int1,`
167			`reti,`
168			`wr_bit;`
169			`input [1:0] psw_set,`
170	132	simont	`wr_sfr,`
171			`comp_sel;`
172	120	simont	`input [2:0] ram_rd_sel,`
173			`ram_wr_sel;`
174			`input [7:0] adr0, //address 0 input`
175			`adr1, //address 1 input`
176	139	simont	`des_acc,`
177	120	simont	`dat1, //data 1 input (des1)`
178			`dat2; //data 2 input (des2)`
179
180			`output bit_out,`
181			`intr,`
182			`srcAc,`
183			`cy,`
184	132	simont	`wait_data,`
185			`comp_wait;`
186	82	simont	`output [1:0] bank_sel;`
187	120	simont	`output [7:0] dat0, //data output`
188			`int_src,`
189			`dptr_hi,`
190			`dptr_lo,`
191			`acc;`
192			`output [7:0] sp,`
193			`sp_w;`
194	75	simont
195	120	simont	`// ports`
196			`ifdef OC8051_PORTS
197	82	simont
198	120	simont	`ifdef OC8051_PORT0
199			`input [7:0] p0_in;`
200			`output [7:0] p0_out;`
201			`wire [7:0] p0_data;`
202			`endif
203	75	simont
204	120	simont	`ifdef OC8051_PORT1
205			`input [7:0] p1_in;`
206			`output [7:0] p1_out;`
207			`wire [7:0] p1_data;`
208			`endif
209	116	simont
210	120	simont	`ifdef OC8051_PORT2
211			`input [7:0] p2_in;`
212			`output [7:0] p2_out;`
213			`wire [7:0] p2_data;`
214			`endif
215	116	simont
216	120	simont	`ifdef OC8051_PORT3
217			`input [7:0] p3_in;`
218			`output [7:0] p3_out;`
219			`wire [7:0] p3_data;`
220			`endif
221	75	simont
222	120	simont	`endif
223
224
225	116	simont	`// serial interface`
226	120	simont	`ifdef OC8051_UART
227			`input rxd;`
228			`output txd;`
229			`endif
230	116	simont
231	120	simont	`// timer/counter 0,1`
232			`ifdef OC8051_TC01
233			`input t0, t1;`
234			`endif
235	82	simont
236	120	simont	`// timer/counter 2`
237			`ifdef OC8051_TC2
238			`input t2, t2ex;`
239			`endif
240	117	simont
241	120	simont	`reg bit_out,`
242			`wait_data;`
243			`reg [7:0] dat0,`
244			`adr0_r;`
245
246			`reg wr_bit_r;`
247			`reg [2:0] ram_wr_sel_r;`
248
249
250			`wire p,`
251			`uart_int,`
252			`tf0,`
253			`tf1,`
254			`tr0,`
255			`tr1,`
256			`rclk,`
257			`tclk,`
258			`brate2,`
259			`tc2_int;`
260
261
262			`wire [7:0] b_reg,`
263			`psw,`
264
265			`ifdef OC8051_TC2
266			`// t/c 2`
267			`t2con,`
268			`tl2,`
269			`th2,`
270			`rcap2l,`
271			`rcap2h,`
272			`endif
273
274			`ifdef OC8051_TC01
275			`// t/c 0,1`
276			`tmod,`
277			`tl0,`
278			`th0,`
279			`tl1,`
280			`th1,`
281			`endif
282
283			`// serial interface`
284			`ifdef OC8051_UART
285			`scon,`
286			`pcon,`
287			`sbuf,`
288			`endif
289
290			`//interrupt control`
291			`ie,`
292			`tcon,`
293			`ip;`
294
295
296			`reg pres_ow;`
297			`reg [3:0] prescaler;`
298
299
300	75	simont	`assign cy = psw[7];`
301			`assign srcAc = psw [6];`
302
303	82	simont
304
305	75	simont	`//`
306			`// accumulator`
307			`// ACC`
308	120	simont	`oc8051_acc oc8051_acc1(.clk(clk),`
309			`.rst(rst),`
310			`.bit_in(bit_in),`
311	139	simont	`.data_in(des_acc),`
312			`.data2_in(dat2),`
313			`.wr(we),`
314			`.wr_bit(wr_bit_r),`
315	120	simont	`.wr_sfr(wr_sfr),`
316	139	simont	`.wr_addr(adr1),`
317			`.data_out(acc),`
318	120	simont	`.p(p));`
319	75	simont
320
321			`//`
322			`// b register`
323			`// B`
324	139	simont	`oc8051_b_register oc8051_b_register (.clk(clk),`
325			`.rst(rst),`
326	120	simont	`.bit_in(bit_in),`
327	139	simont	`.data_in(des_acc),`
328	120	simont	`.wr(we),`
329			`.wr_bit(wr_bit_r),`
330			`.wr_addr(adr1),`
331			`.data_out(b_reg));`
332	75	simont
333			`//`
334			`//stack pointer`
335			`// SP`
336	120	simont	`oc8051_sp oc8051_sp1(.clk(clk),`
337			`.rst(rst),`
338			`.ram_rd_sel(ram_rd_sel),`
339			`.ram_wr_sel(ram_wr_sel),`
340			`.wr_addr(adr1),`
341			`.wr(we),`
342			`.wr_bit(wr_bit_r),`
343			`.data_in(dat1),`
344			`.sp_out(sp),`
345			`.sp_w(sp_w));`
346	75	simont
347			`//`
348			`//data pointer`
349			`// DPTR, DPH, DPL`
350	120	simont	`oc8051_dptr oc8051_dptr1(.clk(clk),`
351			`.rst(rst),`
352			`.addr(adr1),`
353	139	simont	`.data_in(des_acc),`
354	120	simont	`.data2_in(dat2),`
355			`.wr(we),`
356			`.wr_bit(wr_bit_r),`
357			`.data_hi(dptr_hi),`
358			`.data_lo(dptr_lo),`
359			`.wr_sfr(wr_sfr));`
360	75	simont
361	82	simont
362	75	simont	`//`
363			`//program status word`
364			`// PSW`
365	120	simont	`oc8051_psw oc8051_psw1 (.clk(clk),`
366			`.rst(rst),`
367			`.wr_addr(adr1),`
368			`.data_in(dat1),`
369			`.wr(we),`
370			`.wr_bit(wr_bit_r),`
371			`.data_out(psw),`
372			`.p(p),`
373			`.cy_in(bit_in),`
374			`.ac_in(desAc),`
375			`.ov_in(desOv),`
376			`.set(psw_set),`
377			`.bank_sel(bank_sel));`
378	75	simont
379			`//`
380			`// ports`
381			`// P0, P1, P2, P3`
382	120	simont	`ifdef OC8051_PORTS
383			`oc8051_ports oc8051_ports1(.clk(clk),`
384			`.rst(rst),`
385			`.bit_in(bit_in),`
386			`.data_in(dat1),`
387			`.wr(we),`
388			`.wr_bit(wr_bit_r),`
389			`.wr_addr(adr1),`
390	75	simont
391	120	simont	`ifdef OC8051_PORT0
392			`.p0_out(p0_out),`
393			`.p0_in(p0_in),`
394			`.p0_data(p0_data),`
395			`endif
396
397			`ifdef OC8051_PORT1
398			`.p1_out(p1_out),`
399			`.p1_in(p1_in),`
400			`.p1_data(p1_data),`
401			`endif
402
403			`ifdef OC8051_PORT2
404			`.p2_out(p2_out),`
405			`.p2_in(p2_in),`
406			`.p2_data(p2_data),`
407			`endif
408
409			`ifdef OC8051_PORT3
410			`.p3_out(p3_out),`
411			`.p3_in(p3_in),`
412			`.p3_data(p3_data),`
413			`endif
414
415			`.rmw(rmw));`
416			`endif
417
418	75	simont	`//`
419			`// serial interface`
420			`// SCON, SBUF`
421	120	simont	`ifdef OC8051_UART
422			`oc8051_uart oc8051_uatr1 (.clk(clk),`
423			`.rst(rst),`
424			`.bit_in(bit_in),`
425			`.data_in(dat1),`
426			`.wr(we),`
427			`.wr_bit(wr_bit_r),`
428			`.wr_addr(adr1),`
429			`.rxd(rxd),`
430			`.txd(txd),`
431			`// interrupt`
432			`.intr(uart_int),`
433			`// baud rate sources`
434			`.brate2(brate2),`
435			`.t1_ow(tf1),`
436			`.pres_ow(pres_ow),`
437			`.rclk(rclk),`
438			`.tclk(tclk),`
439			`//registers`
440			`.scon(scon),`
441			`.pcon(pcon),`
442			`.sbuf(sbuf));`
443			`else
444			`assign uart_int = 1'b0;`
445			`endif
446	75	simont
447			`//`
448			`// interrupt control`
449			`// IP, IE, TCON`
450	120	simont	`oc8051_int oc8051_int1 (.clk(clk),`
451			`.rst(rst),`
452			`.wr_addr(adr1),`
453			`.bit_in(bit_in),`
454			`.ack(int_ack),`
455			`.data_in(dat1),`
456			`.wr(we),`
457			`.wr_bit(wr_bit_r),`
458			`.tf0(tf0),`
459			`.tf1(tf1),`
460			`.t2_int(tc2_int),`
461			`.tr0(tr0),`
462			`.tr1(tr1),`
463			`.ie0(int0),`
464			`.ie1(int1),`
465			`.uart_int(uart_int),`
466			`.reti(reti),`
467			`.intr(intr),`
468			`.int_vec(int_src),`
469			`.ie(ie),`
470			`.tcon(tcon),`
471			`.ip(ip));`
472	75	simont
473	82	simont
474	75	simont	`//`
475			`// timer/counter control`
476			`// TH0, TH1, TL0, TH1, TMOD`
477	120	simont	`ifdef OC8051_TC01
478			`oc8051_tc oc8051_tc1(.clk(clk),`
479			`.rst(rst),`
480			`.wr_addr(adr1),`
481			`.data_in(dat1),`
482			`.wr(we),`
483			`.wr_bit(wr_bit_r),`
484			`.ie0(int0),`
485			`.ie1(int1),`
486			`.tr0(tr0),`
487			`.tr1(tr1),`
488			`.t0(t0),`
489			`.t1(t1),`
490			`.tf0(tf0),`
491			`.tf1(tf1),`
492			`.pres_ow(pres_ow),`
493			`.tmod(tmod),`
494			`.tl0(tl0),`
495			`.th0(th0),`
496			`.tl1(tl1),`
497			`.th1(th1));`
498			`else
499			`assign tf0 = 1'b0;`
500			`assign tf1 = 1'b0;`

Browse

Tools

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_sfr.v] - Blame information for rev 186