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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 2

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module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
                   rxd, txd, int, t1_ow);
 
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
input [7:0] rd_addr, data_in, wr_addr;
 
output txd, int, bit_out;
output [7:0] data_out;
 
reg txd, bit_out;
reg [7:0] data_out;
 
reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;
reg receive, receive_buf, rxd_buf, r_int;
//
// mode 2 counter
reg [2:0] mode2_count;
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
reg [10:0] sbuf_rxd_tmp;
//
//tr_count      trancive counter
//re_count      receive counter
reg [3:0] tr_count, re_count;
 
//
// sam_cnt      sample counter
reg [2:0] sam_cnt, sample;
 
assign int = scon[1] | scon [0];
 
//
//serial port control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if ((trans_buf) & !(trans))
    scon[1] <= #1 1'b1;
  else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
    case (scon[7:6])
      2'b00: scon[0] <= #1 1'b1;
      default: begin
        if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
        scon[2] <= #1 sbuf_rxd_tmp[9];
      end
    endcase
  end
 
end
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    sbuf_rxd <= #1 `OC8051_RST_SBUF;
  end
end
 
//
//serial port buffer (transmit)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sbuf_txd <= #1 `OC8051_RST_SBUF;
    tr_start <= 1'b0;
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
    sbuf_txd <= #1 data_in;
    tr_start <= #1 1'b1;
   end else
    tr_start <= #1 1'b0;
end
 
//
// transmit
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans <= #1 1'b0;
    smod_cnt_t <= #1 1'b0;
//
// start transmiting
//
  end else if (tr_start) begin
    case (scon[7:6])
      2'b00: begin  // mode 0
        txd <= #1 sbuf_txd[0];
        tr_count <= #1 4'd1;
      end
      2'b10: begin
        txd <= #1 1'b0;
        tr_count <= #1 4'd0;
      end
      default: begin  // mode 1 and mode 3
        tr_count <= #1 4'b1111;
      end
    endcase
    trans <= #1 1'b1;
    smod_cnt_t <= #1 1'b0;
    mode2_count <= #1 3'b000;
//
// transmiting
//
  end else if (trans)
  begin
    case (scon[7:6])
      2'b00: begin //mode 0
        if (tr_count==9'd8)
        begin
          trans <= #1 1'b0;
          txd <= #1 1'b1;
        end else begin
          txd <= #1 sbuf_txd[tr_count];
          tr_count <= #1 tr_count +1'b1;
        end
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_t))
          begin
            case (tr_count)
              4'd8: txd <= #1 1'b1;  // stop bit
              4'd9: trans <= #1 1'b0;
              4'b1111: txd <= #1 1'b0; //start bit
              default: txd <= #1 sbuf_txd[tr_count];
            endcase
            tr_count <= #1 tr_count +1'b1;
            smod_cnt_t <= #1 1'b0;
          end else smod_cnt_t <= #1 1'b1;
        end
      end
      2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
        if (((pcon[7]) & (mode2_count==3'b011)) | (!(pcon[7]) & (mode2_count==3'b101))) begin
          case (tr_count)
            4'd8: begin
              txd <= #1 scon[3];
            end
            4'd9: begin
              txd <= #1 1'b1; //stop bit
              trans <= #1 1'b0;
            end
            default: begin
              txd <= #1 sbuf_txd[tr_count];
            end
          endcase
          tr_count <= #1 tr_count+1'b1;
          mode2_count <= #1 4'd0;
        end else begin
          mode2_count <= #1 mode2_count + 1'b1;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_t))
          begin
            case (tr_count)
              4'd8: begin
                txd <= #1 scon[3];
              end
              4'd9: begin
                txd <= #1 1'b1; //stop bit
              end
              4'd10: begin
          trans <= #1 1'b0;
        end
              4'b1111: txd <= #1 1'b0; //start bit
              default: begin
                txd <= #1 sbuf_txd[tr_count];
              end
            endcase
            tr_count <= #1 tr_count+1'b1;
            smod_cnt_t <= #1 1'b0;
          end else smod_cnt_t <= #1 1'b1;
        end
      end
    endcase
  end else
    txd <= #1 1'b1;
end
 
//
//power control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
//
// receive
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sample <= #1 3'b000;
    sam_cnt <= #1 3'b000;
    re_count <= #1 4'd0;
    receive <= #1 1'b0;
    sbuf_rxd <= #1 8'h00;
    sbuf_rxd_tmp <= #1 11'd0;
    smod_cnt_r <= #1 1'b0;
    r_int <= #1 1'b0;
    re_start <= #1 1'b0;
  end else if (receive) begin
    case (scon[7:6])
      2'b00: begin // mode 0
        if (re_count==4'd8) begin
          receive <= #1 1'b0;
          r_int <= #1 1'b1;
          sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
        end else begin
          sbuf_rxd_tmp[re_count+1] <= #1 rxd;
          r_int <= #1 1'b0;
        end
        re_count <= #1 re_count + 1'b1;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_r))
          begin
            sam_cnt <= #1 3'b000;
            r_int <= #1 1'b0;
 
            re_count <= #1 re_count +1'b1;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
            if (re_count==4'h9)
            begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              r_int <= #1 1'b1;
            end else r_int <= #1 1'b0;
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sam_cnt <= #1 sam_cnt +1'b1;
            r_int <= #1 1'b0;
          end
        end
      end
      2'b10: begin // mode 2
        if (((pcon[7]) & (sam_cnt==3'b100)) | (!(pcon[7]) & (sam_cnt==3'b110))) begin
          if (re_count==4'd11) begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
              receive <= #1 1'b0;
          end else begin
            sam_cnt <= #1 3'b001;
            sample[0] <= #1 rxd;
            r_int <= #1 1'b0;
          end
    re_count <= #1 re_count + 1'b1;
        end else begin
          r_int <= #1 1'b0;
 
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
          end
    sam_cnt <= #1 sam_cnt + 1'b1;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_r))
          begin
            sam_cnt <= #1 3'b000;
 
            if (re_count==4'd11) begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
            end else begin
              sam_cnt <= #1 3'b000;
              r_int <= #1 1'b0;
            end
 
            re_count <= #1 re_count +1'b1;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
          r_int <= #1 1'b0;
          if (sam_cnt==3'b011)
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sam_cnt <= #1 sam_cnt +1'b1;
          end
        end
      end
    endcase
  end else begin
    case (scon[7:6])
      2'b00: begin
        if ((scon[4]) & !(scon[0]) & !(r_int)) begin
          receive <= #1 1'b1;
        end
      end
      2'b10: begin
        if ((rxd_buf) & !(rxd)) begin
          receive <= #1 1'b1;
        end
      end
      default: begin
        if ((rxd_buf) & !(rxd)) begin
          re_start <= #1 1'b1;
        end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin
          re_start <= #1 1'b0;
          receive <= 1'b1;
        end
      end
    endcase
 
    sample <= #1 3'b000;
    sam_cnt <= #1 3'b000;
    re_count <= #1 4'd0;
    sbuf_rxd_tmp <= #1 11'd0;
    r_int <= #1 1'b0;
  end
end
 
//
//
//
always @(posedge clk)
begin
  if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
     (wr_addr==`OC8051_SFR_SCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
      `OC8051_SFR_PCON: data_out <= #1 pcon;
      default: data_out <= #1 scon;
    endcase
  end
end
 
 
always @(posedge clk)
begin
  trans_buf <= #1 trans;
end
 
always @(posedge clk)
begin
  receive_buf <= #1 receive;
end
 
always @(posedge clk)
begin
  t1_ow_buf <= #1 t1_ow;
end
 
always @(posedge clk)
begin
  rxd_buf <= #1 rxd;
end
 
 
always  @(posedge clk)
begin
  if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
    bit_out <= #1 bit_in;
  end else
    bit_out <= #1 scon[rd_addr[2:0]];
 
end
 
endmodule

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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	simont	`module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,`
2			`rxd, txd, int, t1_ow);`
3
4			`input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;`
5			`input [7:0] rd_addr, data_in, wr_addr;`
6
7			`output txd, int, bit_out;`
8			`output [7:0] data_out;`
9
10			`reg txd, bit_out;`
11			`reg [7:0] data_out;`
12
13			`reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;`
14			`reg receive, receive_buf, rxd_buf, r_int;`
15			`//`
16			`// mode 2 counter`
17			`reg [2:0] mode2_count;`
18			`reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;`
19			`reg [10:0] sbuf_rxd_tmp;`
20			`//`
21			`//tr_count trancive counter`
22			`//re_count receive counter`
23			`reg [3:0] tr_count, re_count;`
24
25			`//`
26			`// sam_cnt sample counter`
27			`reg [2:0] sam_cnt, sample;`
28
29			`assign int = scon[1] \| scon [0];`
30
31			`//`
32			`//serial port control register`
33			`//`
34			`always @(posedge clk or posedge rst)`
35			`begin`
36			`if (rst)`
37			scon <= #1 `OC8051_RST_SCON;
38			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
39			`scon <= #1 data_in;`
40			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
41			`scon[wr_addr[2:0]] <= #1 bit_in;`
42			`else if ((trans_buf) & !(trans))`
43			`scon[1] <= #1 1'b1;`
44			`else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin`
45			`case (scon[7:6])`
46			`2'b00: scon[0] <= #1 1'b1;`
47			`default: begin`
48			`if ((sbuf_rxd_tmp[9]) \| !(scon[5])) scon[0] <= #1 1'b1;`
49			`scon[2] <= #1 sbuf_rxd_tmp[9];`
50			`end`
51			`endcase`
52			`end`
53
54			`end`
55
56			`//`
57			`//serial port buffer (receive)`
58			`//`
59			`always @(posedge clk or posedge rst)`
60			`begin`
61			`if (rst)`
62			`begin`
63			sbuf_rxd <= #1 `OC8051_RST_SBUF;
64			`end`
65			`end`
66
67			`//`
68			`//serial port buffer (transmit)`
69			`//`
70			`always @(posedge clk or posedge rst)`
71			`begin`
72			`if (rst) begin`
73			sbuf_txd <= #1 `OC8051_RST_SBUF;
74			`tr_start <= 1'b0;`
75			end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
76			`sbuf_txd <= #1 data_in;`
77			`tr_start <= #1 1'b1;`
78			`end else`
79			`tr_start <= #1 1'b0;`
80			`end`
81
82			`//`
83			`// transmit`
84			`//`
85			`always @(posedge clk or posedge rst)`
86			`begin`
87			`if (rst) begin`
88			`txd <= #1 1'b1;`
89			`tr_count <= #1 4'd0;`
90			`trans <= #1 1'b0;`
91			`smod_cnt_t <= #1 1'b0;`
92			`//`
93			`// start transmiting`
94			`//`
95			`end else if (tr_start) begin`
96			`case (scon[7:6])`
97			`2'b00: begin // mode 0`
98			`txd <= #1 sbuf_txd[0];`
99			`tr_count <= #1 4'd1;`
100			`end`
101			`2'b10: begin`
102			`txd <= #1 1'b0;`
103			`tr_count <= #1 4'd0;`
104			`end`
105			`default: begin // mode 1 and mode 3`
106			`tr_count <= #1 4'b1111;`
107			`end`
108			`endcase`
109			`trans <= #1 1'b1;`
110			`smod_cnt_t <= #1 1'b0;`
111			`mode2_count <= #1 3'b000;`
112			`//`
113			`// transmiting`
114			`//`
115			`end else if (trans)`
116			`begin`
117			`case (scon[7:6])`
118			`2'b00: begin //mode 0`
119			`if (tr_count==9'd8)`
120			`begin`
121			`trans <= #1 1'b0;`
122			`txd <= #1 1'b1;`
123			`end else begin`
124			`txd <= #1 sbuf_txd[tr_count];`
125			`tr_count <= #1 tr_count +1'b1;`
126			`end`
127			`end`
128			`2'b01: begin // mode 1`
129			`if ((t1_ow) & !(t1_ow_buf))`
130			`begin`
131			`if ((pcon[7]) \| (smod_cnt_t))`
132			`begin`
133			`case (tr_count)`
134			`4'd8: txd <= #1 1'b1; // stop bit`
135			`4'd9: trans <= #1 1'b0;`
136			`4'b1111: txd <= #1 1'b0; //start bit`
137			`default: txd <= #1 sbuf_txd[tr_count];`
138			`endcase`
139			`tr_count <= #1 tr_count +1'b1;`
140			`smod_cnt_t <= #1 1'b0;`
141			`end else smod_cnt_t <= #1 1'b1;`
142			`end`
143			`end`
144			`2'b10: begin // mode 2`
145			`//`
146			`// if smod (pcon[7]) is 1 count to 4 else count to 6`
147			`//`
148			`if (((pcon[7]) & (mode2_count==3'b011)) \| (!(pcon[7]) & (mode2_count==3'b101))) begin`
149			`case (tr_count)`
150			`4'd8: begin`
151			`txd <= #1 scon[3];`
152			`end`
153			`4'd9: begin`
154			`txd <= #1 1'b1; //stop bit`
155			`trans <= #1 1'b0;`
156			`end`
157			`default: begin`
158			`txd <= #1 sbuf_txd[tr_count];`
159			`end`
160			`endcase`
161			`tr_count <= #1 tr_count+1'b1;`
162			`mode2_count <= #1 4'd0;`
163			`end else begin`
164			`mode2_count <= #1 mode2_count + 1'b1;`
165			`end`
166			`end`
167			`default: begin // mode 3`
168			`if ((t1_ow) & !(t1_ow_buf))`
169			`begin`
170			`if ((pcon[7]) \| (smod_cnt_t))`
171			`begin`
172			`case (tr_count)`
173			`4'd8: begin`
174			`txd <= #1 scon[3];`
175			`end`
176			`4'd9: begin`
177			`txd <= #1 1'b1; //stop bit`
178			`end`
179			`4'd10: begin`
180			`trans <= #1 1'b0;`
181			`end`
182			`4'b1111: txd <= #1 1'b0; //start bit`
183			`default: begin`
184			`txd <= #1 sbuf_txd[tr_count];`
185			`end`
186			`endcase`
187			`tr_count <= #1 tr_count+1'b1;`
188			`smod_cnt_t <= #1 1'b0;`
189			`end else smod_cnt_t <= #1 1'b1;`
190			`end`
191			`end`
192			`endcase`
193			`end else`
194			`txd <= #1 1'b1;`
195			`end`
196
197			`//`
198			`//power control register`
199			`//`
200			`always @(posedge clk or posedge rst)`
201			`begin`
202			`if (rst)`
203			`begin`
204			pcon <= #1 `OC8051_RST_PCON;
205			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
206			`pcon <= #1 data_in;`
207			`end`
208
209			`//`
210			`// receive`
211			`//`
212			`always @(posedge clk or posedge rst)`
213			`begin`
214			`if (rst) begin`
215			`sample <= #1 3'b000;`
216			`sam_cnt <= #1 3'b000;`
217			`re_count <= #1 4'd0;`
218			`receive <= #1 1'b0;`
219			`sbuf_rxd <= #1 8'h00;`
220			`sbuf_rxd_tmp <= #1 11'd0;`
221			`smod_cnt_r <= #1 1'b0;`
222			`r_int <= #1 1'b0;`
223			`re_start <= #1 1'b0;`
224			`end else if (receive) begin`
225			`case (scon[7:6])`
226			`2'b00: begin // mode 0`
227			`if (re_count==4'd8) begin`
228			`receive <= #1 1'b0;`
229			`r_int <= #1 1'b1;`
230			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
231			`end else begin`
232			`sbuf_rxd_tmp[re_count+1] <= #1 rxd;`
233			`r_int <= #1 1'b0;`
234			`end`
235			`re_count <= #1 re_count + 1'b1;`
236			`end`
237			`2'b01: begin // mode 1`
238			`if ((t1_ow) & !(t1_ow_buf))`
239			`begin`
240			`if ((pcon[7]) \| (smod_cnt_r))`
241			`begin`
242			`sam_cnt <= #1 3'b000;`
243			`r_int <= #1 1'b0;`
244
245			`re_count <= #1 re_count +1'b1;`
246			`smod_cnt_r <= #1 1'b0;`
247			`end else smod_cnt_r <= #1 1'b1;`
248			`end else begin`
249			`if (sam_cnt==3'b011) begin`
250			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
251			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
252			`else`
253			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
254			`if (re_count==4'h9)`
255			`begin`
256			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
257			`receive <= #1 1'b0;`
258			`r_int <= #1 1'b1;`
259			`end else r_int <= #1 1'b0;`
260			`end else begin`
261			`sample[sam_cnt[1:0]] <= #1 rxd;`
262			`sam_cnt <= #1 sam_cnt +1'b1;`
263			`r_int <= #1 1'b0;`
264			`end`
265			`end`
266			`end`
267			`2'b10: begin // mode 2`
268			`if (((pcon[7]) & (sam_cnt==3'b100)) \| (!(pcon[7]) & (sam_cnt==3'b110))) begin`
269			`if (re_count==4'd11) begin`
270			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
271			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
272			`receive <= #1 1'b0;`
273			`end else begin`
274			`sam_cnt <= #1 3'b001;`
275			`sample[0] <= #1 rxd;`
276			`r_int <= #1 1'b0;`
277			`end`
278			`re_count <= #1 re_count + 1'b1;`
279			`end else begin`
280			`r_int <= #1 1'b0;`
281
282			`if (sam_cnt==3'b011) begin`
283			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
284			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
285			`else`
286			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
287			`end else begin`
288			`sample[sam_cnt[1:0]] <= #1 rxd;`
289			`end`
290			`sam_cnt <= #1 sam_cnt + 1'b1;`
291			`end`
292			`end`
293			`default: begin // mode 3`
294			`if ((t1_ow) & !(t1_ow_buf))`
295			`begin`
296			`if ((pcon[7]) \| (smod_cnt_r))`
297			`begin`
298			`sam_cnt <= #1 3'b000;`
299
300			`if (re_count==4'd11) begin`
301			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
302			`receive <= #1 1'b0;`
303			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
304			`end else begin`
305			`sam_cnt <= #1 3'b000;`
306			`r_int <= #1 1'b0;`
307			`end`
308
309			`re_count <= #1 re_count +1'b1;`
310			`smod_cnt_r <= #1 1'b0;`
311			`end else smod_cnt_r <= #1 1'b1;`
312			`end else begin`
313			`r_int <= #1 1'b0;`
314			`if (sam_cnt==3'b011)`
315			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
316			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
317			`else`
318			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
319			`else begin`
320			`sample[sam_cnt[1:0]] <= #1 rxd;`
321			`sam_cnt <= #1 sam_cnt +1'b1;`
322			`end`
323			`end`
324			`end`
325			`endcase`
326			`end else begin`
327			`case (scon[7:6])`
328			`2'b00: begin`
329			`if ((scon[4]) & !(scon[0]) & !(r_int)) begin`
330			`receive <= #1 1'b1;`
331			`end`
332			`end`
333			`2'b10: begin`
334			`if ((rxd_buf) & !(rxd)) begin`
335			`receive <= #1 1'b1;`
336			`end`
337			`end`
338			`default: begin`
339			`if ((rxd_buf) & !(rxd)) begin`
340			`re_start <= #1 1'b1;`
341			`end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin`
342			`re_start <= #1 1'b0;`
343			`receive <= 1'b1;`
344			`end`
345			`end`
346			`endcase`
347
348			`sample <= #1 3'b000;`
349			`sam_cnt <= #1 3'b000;`
350			`re_count <= #1 4'd0;`
351			`sbuf_rxd_tmp <= #1 11'd0;`
352			`r_int <= #1 1'b0;`
353			`end`
354			`end`
355
356			`//`
357			`//`
358			`//`
359			`always @(posedge clk)`
360			`begin`
361			if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) \|
362			(wr_addr==`OC8051_SFR_SCON))) begin
363			`data_out <= #1 data_in;`
364			`end else begin`
365			`case (rd_addr)`
366			`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
367			`OC8051_SFR_PCON: data_out <= #1 pcon;
368			`default: data_out <= #1 scon;`
369			`endcase`
370			`end`
371			`end`
372
373
374			`always @(posedge clk)`
375			`begin`
376			`trans_buf <= #1 trans;`
377			`end`
378
379			`always @(posedge clk)`
380			`begin`
381			`receive_buf <= #1 receive;`
382			`end`
383
384			`always @(posedge clk)`
385			`begin`
386			`t1_ow_buf <= #1 t1_ow;`
387			`end`
388
389			`always @(posedge clk)`
390			`begin`
391			`rxd_buf <= #1 rxd;`
392			`end`
393
394
395			`always @(posedge clk)`
396			`begin`
397			if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
398			`bit_out <= #1 bit_in;`
399			`end else`
400			`bit_out <= #1 scon[rd_addr[2:0]];`
401
402			`end`
403
404			`endmodule`