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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 4

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module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
                   rxd, txd, intr, t1_ow);
 
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
input [7:0] rd_addr, data_in, wr_addr;
 
output txd, intr, bit_out;
output [7:0] data_out;
 
reg txd, bit_out;
reg [7:0] data_out;
 
reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;
reg receive, receive_buf, rxd_buf, r_int;
//
// mode 2 counter
reg [2:0] mode2_count;
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
reg [10:0] sbuf_rxd_tmp;
//
//tr_count      trancive counter
//re_count      receive counter
reg [3:0] tr_count, re_count;
 
//
// sam_cnt      sample counter
reg [2:0] sam_cnt, sample;
 
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if ((trans_buf) & !(trans))
    scon[1] <= #1 1'b1;
  else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
    case (scon[7:6])
      2'b00: scon[0] <= #1 1'b1;
      default: begin
        if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
        scon[2] <= #1 sbuf_rxd_tmp[9];
      end
    endcase
  end
 
end
 
//
//serial port buffer (transmit)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sbuf_txd <= #1 `OC8051_RST_SBUF;
    tr_start <= #1 1'b0;
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
    sbuf_txd <= #1 data_in;
    tr_start <= #1 1'b1;
   end else
    tr_start <= #1 1'b0;
end
 
//
// transmit
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans <= #1 1'b0;
    smod_cnt_t <= #1 1'b0;
//
// start transmiting
//
  end else if (tr_start) begin
    case (scon[7:6])
      2'b00: begin  // mode 0
        txd <= #1 sbuf_txd[0];
        tr_count <= #1 4'd1;
      end
      2'b10: begin
        txd <= #1 1'b0;
        tr_count <= #1 4'd0;
      end
      default: begin  // mode 1 and mode 3
        tr_count <= #1 4'b1111;
      end
    endcase
    trans <= #1 1'b1;
    smod_cnt_t <= #1 1'b0;
    mode2_count <= #1 3'b000;
//
// transmiting
//
  end else if (trans)
  begin
    case (scon[7:6])
      2'b00: begin //mode 0
        if (tr_count==4'd8)
        begin
          trans <= #1 1'b0;
          txd <= #1 1'b1;
        end else begin
          txd <= #1 sbuf_txd[tr_count];
          tr_count <= #1 tr_count + 4'b1;
        end
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_t))
          begin
            case (tr_count)
              4'd8: txd <= #1 1'b1;  // stop bit
              4'd9: trans <= #1 1'b0;
              4'b1111: txd <= #1 1'b0; //start bit
              default: txd <= #1 sbuf_txd[tr_count];
            endcase
            tr_count <= #1 tr_count + 4'b1;
            smod_cnt_t <= #1 1'b0;
          end else smod_cnt_t <= #1 1'b1;
        end
      end
      2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
        if (((pcon[7]) & (mode2_count==3'b011)) | (!(pcon[7]) & (mode2_count==3'b101))) begin
          case (tr_count)
            4'd8: begin
              txd <= #1 scon[3];
            end
            4'd9: begin
              txd <= #1 1'b1; //stop bit
              trans <= #1 1'b0;
            end
            default: begin
              txd <= #1 sbuf_txd[tr_count];
            end
          endcase
          tr_count <= #1 tr_count+1'b1;
          mode2_count <= #1 3'd0;
        end else begin
          mode2_count <= #1 mode2_count + 3'b1;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_t))
          begin
            case (tr_count)
              4'd8: begin
                txd <= #1 scon[3];
              end
              4'd9: begin
                txd <= #1 1'b1; //stop bit
              end
              4'd10: begin
          trans <= #1 1'b0;
        end
              4'b1111: txd <= #1 1'b0; //start bit
              default: begin
                txd <= #1 sbuf_txd[tr_count];
              end
            endcase
            tr_count <= #1 tr_count+1'b1;
            smod_cnt_t <= #1 1'b0;
          end else smod_cnt_t <= #1 1'b1;
        end
      end
    endcase
  end else
    txd <= #1 1'b1;
end
 
//
//power control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sample <= #1 3'b000;
    sam_cnt <= #1 3'b000;
    re_count <= #1 4'd0;
    receive <= #1 1'b0;
    sbuf_rxd <= #1 8'h00;
    sbuf_rxd_tmp <= #1 11'd0;
    smod_cnt_r <= #1 1'b0;
    r_int <= #1 1'b0;
    re_start <= #1 1'b0;
  end else if (receive) begin
    case (scon[7:6])
      2'b00: begin // mode 0
        if (re_count==4'd8) begin
          receive <= #1 1'b0;
          r_int <= #1 1'b1;
          sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
        end else begin
          sbuf_rxd_tmp[re_count+1] <= #1 rxd;
          r_int <= #1 1'b0;
        end
        re_count <= #1 re_count + 4'b1;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_r))
          begin
            sam_cnt <= #1 3'b000;
            r_int <= #1 1'b0;
 
            re_count <= #1 re_count + 4'b1;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
            if (re_count==4'h9)
            begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              r_int <= #1 1'b1;
            end else r_int <= #1 1'b0;
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sam_cnt <= #1 sam_cnt +1'b1;
            r_int <= #1 1'b0;
          end
        end
      end
      2'b10: begin // mode 2
        if (((pcon[7]) & (sam_cnt==3'b100)) | (!(pcon[7]) & (sam_cnt==3'b110))) begin
          if (re_count==4'd11) begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
              receive <= #1 1'b0;
          end else begin
            sam_cnt <= #1 3'b001;
            sample[0] <= #1 rxd;
            r_int <= #1 1'b0;
          end
    re_count <= #1 re_count + 4'b1;
        end else begin
          r_int <= #1 1'b0;
 
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
          end
    sam_cnt <= #1 sam_cnt + 1'b1;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_r))
          begin
            sam_cnt <= #1 3'b000;
 
            if (re_count==4'd11) begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
            end else begin
              sam_cnt <= #1 3'b000;
              r_int <= #1 1'b0;
            end
 
            re_count <= #1 re_count + 4'b1;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
          r_int <= #1 1'b0;
          if (sam_cnt==3'b011)
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sam_cnt <= #1 sam_cnt +1'b1;
          end
        end
      end
    endcase
  end else begin
    case (scon[7:6])
      2'b00: begin
        if ((scon[4]) & !(scon[0]) & !(r_int)) begin
          receive <= #1 1'b1;
        end
      end
      2'b10: begin
        if ((rxd_buf) & !(rxd)) begin
          receive <= #1 1'b1;
        end
      end
      default: begin
        if ((rxd_buf) & !(rxd)) begin
          re_start <= #1 1'b1;
        end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin
          re_start <= #1 1'b0;
          receive <= 1'b1;
        end
      end
    endcase
 
    sample <= #1 3'b000;
    sam_cnt <= #1 3'b000;
    re_count <= #1 4'd0;
    sbuf_rxd_tmp <= #1 11'd0;
    r_int <= #1 1'b0;
  end
end
 
//
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
     (wr_addr==`OC8051_SFR_SCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
      `OC8051_SFR_PCON: data_out <= #1 pcon;
      default: data_out <= #1 scon;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    trans_buf <= #1 1'b0;
    receive_buf <= #1 1'b0;
    t1_ow_buf <= #1 1'b0;
    rxd_buf <= #1 1'b0;
  end else begin
    trans_buf <= #1 trans;
    receive_buf <= #1 receive;
    t1_ow_buf <= #1 t1_ow;
    rxd_buf <= #1 rxd;
  end
end
 
always  @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
    bit_out <= #1 bit_in;
  end else
    bit_out <= #1 scon[rd_addr[2:0]];
end
 
endmodule

Line No.	Rev	Author	Line
1	2	simont	`module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,`
2	4	markom	`rxd, txd, intr, t1_ow);`
3	2	simont
4			`input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;`
5			`input [7:0] rd_addr, data_in, wr_addr;`
6
7	4	markom	`output txd, intr, bit_out;`
8	2	simont	`output [7:0] data_out;`
9
10			`reg txd, bit_out;`
11			`reg [7:0] data_out;`
12
13			`reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;`
14			`reg receive, receive_buf, rxd_buf, r_int;`
15			`//`
16			`// mode 2 counter`
17			`reg [2:0] mode2_count;`
18			`reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;`
19			`reg [10:0] sbuf_rxd_tmp;`
20			`//`
21			`//tr_count trancive counter`
22			`//re_count receive counter`
23			`reg [3:0] tr_count, re_count;`
24
25			`//`
26			`// sam_cnt sample counter`
27			`reg [2:0] sam_cnt, sample;`
28
29	4	markom	`assign intr = scon[1] \| scon [0];`
30	2	simont
31			`//`
32			`//serial port control register`
33			`//`
34			`always @(posedge clk or posedge rst)`
35			`begin`
36			`if (rst)`
37			scon <= #1 `OC8051_RST_SCON;
38			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
39			`scon <= #1 data_in;`
40			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
41			`scon[wr_addr[2:0]] <= #1 bit_in;`
42			`else if ((trans_buf) & !(trans))`
43			`scon[1] <= #1 1'b1;`
44			`else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin`
45			`case (scon[7:6])`
46			`2'b00: scon[0] <= #1 1'b1;`
47			`default: begin`
48			`if ((sbuf_rxd_tmp[9]) \| !(scon[5])) scon[0] <= #1 1'b1;`
49			`scon[2] <= #1 sbuf_rxd_tmp[9];`
50			`end`
51			`endcase`
52			`end`
53
54			`end`
55
56			`//`
57			`//serial port buffer (transmit)`
58			`//`
59			`always @(posedge clk or posedge rst)`
60			`begin`
61			`if (rst) begin`
62			sbuf_txd <= #1 `OC8051_RST_SBUF;
63	4	markom	`tr_start <= #1 1'b0;`
64	2	simont	end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
65			`sbuf_txd <= #1 data_in;`
66			`tr_start <= #1 1'b1;`
67			`end else`
68			`tr_start <= #1 1'b0;`
69			`end`
70
71			`//`
72			`// transmit`
73			`//`
74			`always @(posedge clk or posedge rst)`
75			`begin`
76			`if (rst) begin`
77			`txd <= #1 1'b1;`
78			`tr_count <= #1 4'd0;`
79			`trans <= #1 1'b0;`
80			`smod_cnt_t <= #1 1'b0;`
81			`//`
82			`// start transmiting`
83			`//`
84			`end else if (tr_start) begin`
85			`case (scon[7:6])`
86			`2'b00: begin // mode 0`
87			`txd <= #1 sbuf_txd[0];`
88			`tr_count <= #1 4'd1;`
89			`end`
90			`2'b10: begin`
91			`txd <= #1 1'b0;`
92			`tr_count <= #1 4'd0;`
93			`end`
94			`default: begin // mode 1 and mode 3`
95			`tr_count <= #1 4'b1111;`
96			`end`
97			`endcase`
98			`trans <= #1 1'b1;`
99			`smod_cnt_t <= #1 1'b0;`
100			`mode2_count <= #1 3'b000;`
101			`//`
102			`// transmiting`
103			`//`
104			`end else if (trans)`
105			`begin`
106			`case (scon[7:6])`
107			`2'b00: begin //mode 0`
108	4	markom	`if (tr_count==4'd8)`
109	2	simont	`begin`
110			`trans <= #1 1'b0;`
111			`txd <= #1 1'b1;`
112			`end else begin`
113			`txd <= #1 sbuf_txd[tr_count];`
114	4	markom	`tr_count <= #1 tr_count + 4'b1;`
115	2	simont	`end`
116			`end`
117			`2'b01: begin // mode 1`
118			`if ((t1_ow) & !(t1_ow_buf))`
119			`begin`
120			`if ((pcon[7]) \| (smod_cnt_t))`
121			`begin`
122			`case (tr_count)`
123			`4'd8: txd <= #1 1'b1; // stop bit`
124			`4'd9: trans <= #1 1'b0;`
125			`4'b1111: txd <= #1 1'b0; //start bit`
126			`default: txd <= #1 sbuf_txd[tr_count];`
127			`endcase`
128	4	markom	`tr_count <= #1 tr_count + 4'b1;`
129	2	simont	`smod_cnt_t <= #1 1'b0;`
130			`end else smod_cnt_t <= #1 1'b1;`
131			`end`
132			`end`
133			`2'b10: begin // mode 2`
134			`//`
135			`// if smod (pcon[7]) is 1 count to 4 else count to 6`
136			`//`
137			`if (((pcon[7]) & (mode2_count==3'b011)) \| (!(pcon[7]) & (mode2_count==3'b101))) begin`
138			`case (tr_count)`
139			`4'd8: begin`
140			`txd <= #1 scon[3];`
141			`end`
142			`4'd9: begin`
143			`txd <= #1 1'b1; //stop bit`
144			`trans <= #1 1'b0;`
145			`end`
146			`default: begin`
147			`txd <= #1 sbuf_txd[tr_count];`
148			`end`
149			`endcase`
150			`tr_count <= #1 tr_count+1'b1;`
151	4	markom	`mode2_count <= #1 3'd0;`
152	2	simont	`end else begin`
153	4	markom	`mode2_count <= #1 mode2_count + 3'b1;`
154	2	simont	`end`
155			`end`
156			`default: begin // mode 3`
157			`if ((t1_ow) & !(t1_ow_buf))`
158			`begin`
159			`if ((pcon[7]) \| (smod_cnt_t))`
160			`begin`
161			`case (tr_count)`
162			`4'd8: begin`
163			`txd <= #1 scon[3];`
164			`end`
165			`4'd9: begin`
166			`txd <= #1 1'b1; //stop bit`
167			`end`
168			`4'd10: begin`
169			`trans <= #1 1'b0;`
170			`end`
171			`4'b1111: txd <= #1 1'b0; //start bit`
172			`default: begin`
173			`txd <= #1 sbuf_txd[tr_count];`
174			`end`
175			`endcase`
176			`tr_count <= #1 tr_count+1'b1;`
177			`smod_cnt_t <= #1 1'b0;`
178			`end else smod_cnt_t <= #1 1'b1;`
179			`end`
180			`end`
181			`endcase`
182			`end else`
183			`txd <= #1 1'b1;`
184			`end`
185
186			`//`
187			`//power control register`
188			`//`
189			`always @(posedge clk or posedge rst)`
190			`begin`
191			`if (rst)`
192			`begin`
193			pcon <= #1 `OC8051_RST_PCON;
194			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
195			`pcon <= #1 data_in;`
196			`end`
197
198			`//`
199	4	markom	`//serial port buffer (receive)`
200	2	simont	`//`
201			`always @(posedge clk or posedge rst)`
202			`begin`
203			`if (rst) begin`
204			`sample <= #1 3'b000;`
205			`sam_cnt <= #1 3'b000;`
206			`re_count <= #1 4'd0;`
207			`receive <= #1 1'b0;`
208			`sbuf_rxd <= #1 8'h00;`
209			`sbuf_rxd_tmp <= #1 11'd0;`
210			`smod_cnt_r <= #1 1'b0;`
211			`r_int <= #1 1'b0;`
212			`re_start <= #1 1'b0;`
213			`end else if (receive) begin`
214			`case (scon[7:6])`
215			`2'b00: begin // mode 0`
216			`if (re_count==4'd8) begin`
217			`receive <= #1 1'b0;`
218			`r_int <= #1 1'b1;`
219			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
220			`end else begin`
221			`sbuf_rxd_tmp[re_count+1] <= #1 rxd;`
222			`r_int <= #1 1'b0;`
223			`end`
224	4	markom	`re_count <= #1 re_count + 4'b1;`
225	2	simont	`end`
226			`2'b01: begin // mode 1`
227			`if ((t1_ow) & !(t1_ow_buf))`
228			`begin`
229			`if ((pcon[7]) \| (smod_cnt_r))`
230			`begin`
231			`sam_cnt <= #1 3'b000;`
232			`r_int <= #1 1'b0;`
233
234	4	markom	`re_count <= #1 re_count + 4'b1;`
235	2	simont	`smod_cnt_r <= #1 1'b0;`
236			`end else smod_cnt_r <= #1 1'b1;`
237			`end else begin`
238			`if (sam_cnt==3'b011) begin`
239			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
240			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
241			`else`
242			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
243			`if (re_count==4'h9)`
244			`begin`
245			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
246			`receive <= #1 1'b0;`
247			`r_int <= #1 1'b1;`
248			`end else r_int <= #1 1'b0;`
249			`end else begin`
250			`sample[sam_cnt[1:0]] <= #1 rxd;`
251			`sam_cnt <= #1 sam_cnt +1'b1;`
252			`r_int <= #1 1'b0;`
253			`end`
254			`end`
255			`end`
256			`2'b10: begin // mode 2`
257			`if (((pcon[7]) & (sam_cnt==3'b100)) \| (!(pcon[7]) & (sam_cnt==3'b110))) begin`
258			`if (re_count==4'd11) begin`
259			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
260			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
261			`receive <= #1 1'b0;`
262			`end else begin`
263			`sam_cnt <= #1 3'b001;`
264			`sample[0] <= #1 rxd;`
265			`r_int <= #1 1'b0;`
266			`end`
267	4	markom	`re_count <= #1 re_count + 4'b1;`
268	2	simont	`end else begin`
269			`r_int <= #1 1'b0;`
270
271			`if (sam_cnt==3'b011) begin`
272			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
273			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
274			`else`
275			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
276			`end else begin`
277			`sample[sam_cnt[1:0]] <= #1 rxd;`
278			`end`
279			`sam_cnt <= #1 sam_cnt + 1'b1;`
280			`end`
281			`end`
282			`default: begin // mode 3`
283			`if ((t1_ow) & !(t1_ow_buf))`
284			`begin`
285			`if ((pcon[7]) \| (smod_cnt_r))`
286			`begin`
287			`sam_cnt <= #1 3'b000;`
288
289			`if (re_count==4'd11) begin`
290			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
291			`receive <= #1 1'b0;`
292			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
293			`end else begin`
294			`sam_cnt <= #1 3'b000;`
295			`r_int <= #1 1'b0;`
296			`end`
297
298	4	markom	`re_count <= #1 re_count + 4'b1;`
299	2	simont	`smod_cnt_r <= #1 1'b0;`
300			`end else smod_cnt_r <= #1 1'b1;`
301			`end else begin`
302			`r_int <= #1 1'b0;`
303			`if (sam_cnt==3'b011)`
304			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
305			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
306			`else`
307			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
308			`else begin`
309			`sample[sam_cnt[1:0]] <= #1 rxd;`
310			`sam_cnt <= #1 sam_cnt +1'b1;`
311			`end`
312			`end`
313			`end`
314			`endcase`
315			`end else begin`
316			`case (scon[7:6])`
317			`2'b00: begin`
318			`if ((scon[4]) & !(scon[0]) & !(r_int)) begin`
319			`receive <= #1 1'b1;`
320			`end`
321			`end`
322			`2'b10: begin`
323			`if ((rxd_buf) & !(rxd)) begin`
324			`receive <= #1 1'b1;`
325			`end`
326			`end`
327			`default: begin`
328			`if ((rxd_buf) & !(rxd)) begin`
329			`re_start <= #1 1'b1;`
330			`end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin`
331			`re_start <= #1 1'b0;`
332			`receive <= 1'b1;`
333			`end`
334			`end`
335			`endcase`
336
337			`sample <= #1 3'b000;`
338			`sam_cnt <= #1 3'b000;`
339			`re_count <= #1 4'd0;`
340			`sbuf_rxd_tmp <= #1 11'd0;`
341			`r_int <= #1 1'b0;`
342			`end`
343			`end`
344
345			`//`
346			`//`
347			`//`
348	4	markom	`always @(posedge clk or posedge rst)`
349	2	simont	`begin`
350	4	markom	`if (rst) data_out <= #1 8'h0;`
351			else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) \|
352	2	simont	(wr_addr==`OC8051_SFR_SCON))) begin
353			`data_out <= #1 data_in;`
354			`end else begin`
355			`case (rd_addr)`
356			`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
357			`OC8051_SFR_PCON: data_out <= #1 pcon;
358			`default: data_out <= #1 scon;`
359			`endcase`
360			`end`
361			`end`
362
363
364	4	markom	`always @(posedge clk or posedge rst)`
365	2	simont	`begin`
366	4	markom	`if (rst) begin`
367			`trans_buf <= #1 1'b0;`
368			`receive_buf <= #1 1'b0;`
369			`t1_ow_buf <= #1 1'b0;`
370			`rxd_buf <= #1 1'b0;`
371			`end else begin`
372			`trans_buf <= #1 trans;`
373			`receive_buf <= #1 receive;`
374			`t1_ow_buf <= #1 t1_ow;`
375			`rxd_buf <= #1 rxd;`
376			`end`
377	2	simont	`end`
378
379	4	markom	`always @(posedge clk or posedge rst)`
380	2	simont	`begin`
381	4	markom	`if (rst) bit_out <= #1 1'b0;`
382			else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
383	2	simont	`bit_out <= #1 bit_in;`
384			`end else`
385			`bit_out <= #1 scon[rd_addr[2:0]];`
386			`end`
387
388			`endmodule`

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