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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 5

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module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
                   rxd, txd, intr, t1_ow);
 
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
input [7:0] rd_addr, data_in, wr_addr;
 
output txd, intr, bit_out;
output [7:0] data_out;
 
reg txd, bit_out;
reg [7:0] data_out;
 
reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;
reg receive, receive_buf, rxd_buf, r_int;
//
// mode 2 counter
reg [2:0] mode2_count;
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
reg [10:0] sbuf_rxd_tmp;
//
//tr_count      trancive counter
//re_count      receive counter
reg [3:0] tr_count, re_count;
 
//
// sam_cnt      sample counter
reg [2:0] sam_cnt, sample;
 
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if ((trans_buf) & !(trans))
    scon[1] <= #1 1'b1;
  else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
    case (scon[7:6])
      2'b00: scon[0] <= #1 1'b1;
      default: begin
        if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
        scon[2] <= #1 sbuf_rxd_tmp[9];
      end
    endcase
  end
 
end
 
//
//serial port buffer (transmit)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sbuf_txd <= #1 `OC8051_RST_SBUF;
    tr_start <= #1 1'b0;
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
    sbuf_txd <= #1 data_in;
    tr_start <= #1 1'b1;
  end else tr_start <= #1 1'b0;
end
 
//
// transmit
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans <= #1 1'b0;
    smod_cnt_t <= #1 1'b0;
//
// start transmiting
//
  end else if (tr_start) begin
    case (scon[7:6])
      2'b00: begin  // mode 0
        txd <= #1 sbuf_txd[0];
        tr_count <= #1 4'd1;
      end
      2'b10: begin
        txd <= #1 1'b0;
        tr_count <= #1 4'd0;
      end
      default: begin  // mode 1 and mode 3
        tr_count <= #1 4'b1111;
      end
    endcase
    trans <= #1 1'b1;
    smod_cnt_t <= #1 1'b0;
    mode2_count <= #1 3'b000;
//
// transmiting
//
  end else if (trans)
  begin
    case (scon[7:6])
      2'b00: begin //mode 0
        if (tr_count==4'd8)
        begin
          trans <= #1 1'b0;
          txd <= #1 1'b1;
        end else begin
          txd <= #1 sbuf_txd[tr_count];
          tr_count <= #1 tr_count + 4'b1;
        end
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_t))
          begin
            case (tr_count)
              4'd8: txd <= #1 1'b1;  // stop bit
              4'd9: trans <= #1 1'b0;
              4'b1111: txd <= #1 1'b0; //start bit
              default: txd <= #1 sbuf_txd[tr_count];
            endcase
            tr_count <= #1 tr_count + 4'b1;
            smod_cnt_t <= #1 1'b0;
          end else smod_cnt_t <= #1 1'b1;
        end
      end
      2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
        if (((pcon[7]) & (mode2_count==3'b011)) | (!(pcon[7]) & (mode2_count==3'b101))) begin
          case (tr_count)
            4'd8: begin
              txd <= #1 scon[3];
            end
            4'd9: begin
              txd <= #1 1'b1; //stop bit
              trans <= #1 1'b0;
            end
            default: begin
              txd <= #1 sbuf_txd[tr_count];
            end
          endcase
          tr_count <= #1 tr_count+1'b1;
          mode2_count <= #1 3'd0;
        end else begin
          mode2_count <= #1 mode2_count + 3'b1;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_t))
          begin
            case (tr_count)
              4'd8: begin
                txd <= #1 scon[3];
              end
              4'd9: begin
                txd <= #1 1'b1; //stop bit
              end
              4'd10: begin
          trans <= #1 1'b0;
        end
              4'b1111: txd <= #1 1'b0; //start bit
              default: begin
                txd <= #1 sbuf_txd[tr_count];
              end
            endcase
            tr_count <= #1 tr_count+1'b1;
            smod_cnt_t <= #1 1'b0;
          end else smod_cnt_t <= #1 1'b1;
        end
      end
    endcase
  end else
    txd <= #1 1'b1;
end
 
//
//power control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sample <= #1 3'b000;
    sam_cnt <= #1 3'b000;
    re_count <= #1 4'd0;
    receive <= #1 1'b0;
    sbuf_rxd <= #1 8'h00;
    sbuf_rxd_tmp <= #1 11'd0;
    smod_cnt_r <= #1 1'b0;
    r_int <= #1 1'b0;
    re_start <= #1 1'b0;
  end else if (receive) begin
    case (scon[7:6])
      2'b00: begin // mode 0
        if (re_count==4'd8) begin
          receive <= #1 1'b0;
          r_int <= #1 1'b1;
          sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
        end else begin
          sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
          r_int <= #1 1'b0;
        end
        re_count <= #1 re_count + 4'd1;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_r))
          begin
            sam_cnt <= #1 3'b000;
            r_int <= #1 1'b0;
 
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
            if (re_count == 4'd9)
            begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              r_int <= #1 1'b1;
            end else r_int <= #1 1'b0;
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sam_cnt <= #1 sam_cnt +1'b1;
            r_int <= #1 1'b0;
          end
        end
      end
      2'b10: begin // mode 2
        if (((pcon[7]) & (sam_cnt==3'b100)) | (!(pcon[7]) & (sam_cnt==3'b110))) begin
          if (re_count==4'd11) begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
              receive <= #1 1'b0;
          end else begin
            sam_cnt <= #1 3'b001;
            sample[0] <= #1 rxd;
            r_int <= #1 1'b0;
          end
    re_count <= #1 re_count + 4'd1;
        end else begin
          r_int <= #1 1'b0;
 
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
          end
    sam_cnt <= #1 sam_cnt + 1'b1;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_r))
          begin
            sam_cnt <= #1 3'b000;
 
            if (re_count==4'd11) begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
            end else begin
              sam_cnt <= #1 3'b000;
              r_int <= #1 1'b0;
            end
 
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
          r_int <= #1 1'b0;
          if (sam_cnt==3'b011)
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sam_cnt <= #1 sam_cnt +1'b1;
          end
        end
      end
    endcase
  end else begin
    case (scon[7:6])
      2'b00: begin
        if ((scon[4]) & !(scon[0]) & !(r_int)) begin
          receive <= #1 1'b1;
        end
      end
      2'b10: begin
        if ((rxd_buf) & !(rxd)) begin
          receive <= #1 1'b1;
        end
      end
      default: begin
        if ((rxd_buf) & !(rxd)) begin
          re_start <= #1 1'b1;
        end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin
          re_start <= #1 1'b0;
          receive <= 1'b1;
        end
      end
    endcase
 
    sample <= #1 3'b000;
    sam_cnt <= #1 3'b000;
    re_count <= #1 4'd0;
    sbuf_rxd_tmp <= #1 11'd0;
    r_int <= #1 1'b0;
  end
end
 
//
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
     (wr_addr==`OC8051_SFR_SCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
      `OC8051_SFR_PCON: data_out <= #1 pcon;
      default: data_out <= #1 scon;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    trans_buf <= #1 1'b0;
    receive_buf <= #1 1'b0;
    t1_ow_buf <= #1 1'b0;
    rxd_buf <= #1 1'b0;
  end else begin
    trans_buf <= #1 trans;
    receive_buf <= #1 receive;
    t1_ow_buf <= #1 t1_ow;
    rxd_buf <= #1 rxd;
  end
end
 
always  @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
    bit_out <= #1 bit_in;
  end else
    bit_out <= #1 scon[rd_addr[2:0]];
end
 
endmodule

Line No.	Rev	Author	Line
1	2	simont	`module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,`
2	4	markom	`rxd, txd, intr, t1_ow);`
3	2	simont
4			`input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;`
5			`input [7:0] rd_addr, data_in, wr_addr;`
6
7	4	markom	`output txd, intr, bit_out;`
8	2	simont	`output [7:0] data_out;`
9
10			`reg txd, bit_out;`
11			`reg [7:0] data_out;`
12
13			`reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;`
14			`reg receive, receive_buf, rxd_buf, r_int;`
15			`//`
16			`// mode 2 counter`
17			`reg [2:0] mode2_count;`
18			`reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;`
19			`reg [10:0] sbuf_rxd_tmp;`
20			`//`
21			`//tr_count trancive counter`
22			`//re_count receive counter`
23			`reg [3:0] tr_count, re_count;`
24
25			`//`
26			`// sam_cnt sample counter`
27			`reg [2:0] sam_cnt, sample;`
28
29	4	markom	`assign intr = scon[1] \| scon [0];`
30	2	simont
31			`//`
32			`//serial port control register`
33			`//`
34			`always @(posedge clk or posedge rst)`
35			`begin`
36			`if (rst)`
37			scon <= #1 `OC8051_RST_SCON;
38			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
39			`scon <= #1 data_in;`
40			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
41			`scon[wr_addr[2:0]] <= #1 bit_in;`
42			`else if ((trans_buf) & !(trans))`
43			`scon[1] <= #1 1'b1;`
44			`else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin`
45			`case (scon[7:6])`
46			`2'b00: scon[0] <= #1 1'b1;`
47			`default: begin`
48			`if ((sbuf_rxd_tmp[9]) \| !(scon[5])) scon[0] <= #1 1'b1;`
49			`scon[2] <= #1 sbuf_rxd_tmp[9];`
50			`end`
51			`endcase`
52			`end`
53
54			`end`
55
56			`//`
57			`//serial port buffer (transmit)`
58			`//`
59			`always @(posedge clk or posedge rst)`
60			`begin`
61			`if (rst) begin`
62			sbuf_txd <= #1 `OC8051_RST_SBUF;
63	4	markom	`tr_start <= #1 1'b0;`
64	2	simont	end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
65			`sbuf_txd <= #1 data_in;`
66			`tr_start <= #1 1'b1;`
67	5	markom	`end else tr_start <= #1 1'b0;`
68	2	simont	`end`
69
70			`//`
71			`// transmit`
72			`//`
73			`always @(posedge clk or posedge rst)`
74			`begin`
75			`if (rst) begin`
76			`txd <= #1 1'b1;`
77			`tr_count <= #1 4'd0;`
78			`trans <= #1 1'b0;`
79			`smod_cnt_t <= #1 1'b0;`
80			`//`
81			`// start transmiting`
82			`//`
83			`end else if (tr_start) begin`
84			`case (scon[7:6])`
85			`2'b00: begin // mode 0`
86			`txd <= #1 sbuf_txd[0];`
87			`tr_count <= #1 4'd1;`
88			`end`
89			`2'b10: begin`
90			`txd <= #1 1'b0;`
91			`tr_count <= #1 4'd0;`
92			`end`
93			`default: begin // mode 1 and mode 3`
94			`tr_count <= #1 4'b1111;`
95			`end`
96			`endcase`
97			`trans <= #1 1'b1;`
98			`smod_cnt_t <= #1 1'b0;`
99			`mode2_count <= #1 3'b000;`
100			`//`
101			`// transmiting`
102			`//`
103			`end else if (trans)`
104			`begin`
105			`case (scon[7:6])`
106			`2'b00: begin //mode 0`
107	4	markom	`if (tr_count==4'd8)`
108	2	simont	`begin`
109			`trans <= #1 1'b0;`
110			`txd <= #1 1'b1;`
111			`end else begin`
112			`txd <= #1 sbuf_txd[tr_count];`
113	4	markom	`tr_count <= #1 tr_count + 4'b1;`
114	2	simont	`end`
115			`end`
116			`2'b01: begin // mode 1`
117			`if ((t1_ow) & !(t1_ow_buf))`
118			`begin`
119			`if ((pcon[7]) \| (smod_cnt_t))`
120			`begin`
121			`case (tr_count)`
122			`4'd8: txd <= #1 1'b1; // stop bit`
123			`4'd9: trans <= #1 1'b0;`
124			`4'b1111: txd <= #1 1'b0; //start bit`
125			`default: txd <= #1 sbuf_txd[tr_count];`
126			`endcase`
127	4	markom	`tr_count <= #1 tr_count + 4'b1;`
128	2	simont	`smod_cnt_t <= #1 1'b0;`
129			`end else smod_cnt_t <= #1 1'b1;`
130			`end`
131			`end`
132			`2'b10: begin // mode 2`
133			`//`
134			`// if smod (pcon[7]) is 1 count to 4 else count to 6`
135			`//`
136			`if (((pcon[7]) & (mode2_count==3'b011)) \| (!(pcon[7]) & (mode2_count==3'b101))) begin`
137			`case (tr_count)`
138			`4'd8: begin`
139			`txd <= #1 scon[3];`
140			`end`
141			`4'd9: begin`
142			`txd <= #1 1'b1; //stop bit`
143			`trans <= #1 1'b0;`
144			`end`
145			`default: begin`
146			`txd <= #1 sbuf_txd[tr_count];`
147			`end`
148			`endcase`
149			`tr_count <= #1 tr_count+1'b1;`
150	4	markom	`mode2_count <= #1 3'd0;`
151	2	simont	`end else begin`
152	4	markom	`mode2_count <= #1 mode2_count + 3'b1;`
153	2	simont	`end`
154			`end`
155			`default: begin // mode 3`
156			`if ((t1_ow) & !(t1_ow_buf))`
157			`begin`
158			`if ((pcon[7]) \| (smod_cnt_t))`
159			`begin`
160			`case (tr_count)`
161			`4'd8: begin`
162			`txd <= #1 scon[3];`
163			`end`
164			`4'd9: begin`
165			`txd <= #1 1'b1; //stop bit`
166			`end`
167			`4'd10: begin`
168			`trans <= #1 1'b0;`
169			`end`
170			`4'b1111: txd <= #1 1'b0; //start bit`
171			`default: begin`
172			`txd <= #1 sbuf_txd[tr_count];`
173			`end`
174			`endcase`
175			`tr_count <= #1 tr_count+1'b1;`
176			`smod_cnt_t <= #1 1'b0;`
177			`end else smod_cnt_t <= #1 1'b1;`
178			`end`
179			`end`
180			`endcase`
181			`end else`
182			`txd <= #1 1'b1;`
183			`end`
184
185			`//`
186			`//power control register`
187			`//`
188			`always @(posedge clk or posedge rst)`
189			`begin`
190			`if (rst)`
191			`begin`
192			pcon <= #1 `OC8051_RST_PCON;
193			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
194			`pcon <= #1 data_in;`
195			`end`
196
197			`//`
198	4	markom	`//serial port buffer (receive)`
199	2	simont	`//`
200			`always @(posedge clk or posedge rst)`
201			`begin`
202			`if (rst) begin`
203			`sample <= #1 3'b000;`
204			`sam_cnt <= #1 3'b000;`
205			`re_count <= #1 4'd0;`
206			`receive <= #1 1'b0;`
207			`sbuf_rxd <= #1 8'h00;`
208			`sbuf_rxd_tmp <= #1 11'd0;`
209			`smod_cnt_r <= #1 1'b0;`
210			`r_int <= #1 1'b0;`
211			`re_start <= #1 1'b0;`
212			`end else if (receive) begin`
213			`case (scon[7:6])`
214			`2'b00: begin // mode 0`
215			`if (re_count==4'd8) begin`
216			`receive <= #1 1'b0;`
217			`r_int <= #1 1'b1;`
218			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
219			`end else begin`
220	5	markom	`sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;`
221	2	simont	`r_int <= #1 1'b0;`
222			`end`
223	5	markom	`re_count <= #1 re_count + 4'd1;`
224	2	simont	`end`
225			`2'b01: begin // mode 1`
226			`if ((t1_ow) & !(t1_ow_buf))`
227			`begin`
228			`if ((pcon[7]) \| (smod_cnt_r))`
229			`begin`
230			`sam_cnt <= #1 3'b000;`
231			`r_int <= #1 1'b0;`
232
233	5	markom	`re_count <= #1 re_count + 4'd1;`
234	2	simont	`smod_cnt_r <= #1 1'b0;`
235			`end else smod_cnt_r <= #1 1'b1;`
236			`end else begin`
237			`if (sam_cnt==3'b011) begin`
238			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
239			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
240			`else`
241			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
242	5	markom	`if (re_count == 4'd9)`
243	2	simont	`begin`
244			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
245			`receive <= #1 1'b0;`
246			`r_int <= #1 1'b1;`
247			`end else r_int <= #1 1'b0;`
248			`end else begin`
249			`sample[sam_cnt[1:0]] <= #1 rxd;`
250			`sam_cnt <= #1 sam_cnt +1'b1;`
251			`r_int <= #1 1'b0;`
252			`end`
253			`end`
254			`end`
255			`2'b10: begin // mode 2`
256			`if (((pcon[7]) & (sam_cnt==3'b100)) \| (!(pcon[7]) & (sam_cnt==3'b110))) begin`
257			`if (re_count==4'd11) begin`
258			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
259			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
260			`receive <= #1 1'b0;`
261			`end else begin`
262			`sam_cnt <= #1 3'b001;`
263			`sample[0] <= #1 rxd;`
264			`r_int <= #1 1'b0;`
265			`end`
266	5	markom	`re_count <= #1 re_count + 4'd1;`
267	2	simont	`end else begin`
268			`r_int <= #1 1'b0;`
269
270			`if (sam_cnt==3'b011) begin`
271			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
272			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
273			`else`
274			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
275			`end else begin`
276			`sample[sam_cnt[1:0]] <= #1 rxd;`
277			`end`
278			`sam_cnt <= #1 sam_cnt + 1'b1;`
279			`end`
280			`end`
281			`default: begin // mode 3`
282			`if ((t1_ow) & !(t1_ow_buf))`
283			`begin`
284			`if ((pcon[7]) \| (smod_cnt_r))`
285			`begin`
286			`sam_cnt <= #1 3'b000;`
287
288			`if (re_count==4'd11) begin`
289			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
290			`receive <= #1 1'b0;`
291			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
292			`end else begin`
293			`sam_cnt <= #1 3'b000;`
294			`r_int <= #1 1'b0;`
295			`end`
296
297	5	markom	`re_count <= #1 re_count + 4'd1;`
298	2	simont	`smod_cnt_r <= #1 1'b0;`
299			`end else smod_cnt_r <= #1 1'b1;`
300			`end else begin`
301			`r_int <= #1 1'b0;`
302			`if (sam_cnt==3'b011)`
303			`if ((sample[0] % sample[1]) \| (sample[0] % sample[2]))`
304			`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
305			`else`
306			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
307			`else begin`
308			`sample[sam_cnt[1:0]] <= #1 rxd;`
309			`sam_cnt <= #1 sam_cnt +1'b1;`
310			`end`
311			`end`
312			`end`
313			`endcase`
314			`end else begin`
315			`case (scon[7:6])`
316			`2'b00: begin`
317			`if ((scon[4]) & !(scon[0]) & !(r_int)) begin`
318			`receive <= #1 1'b1;`
319			`end`
320			`end`
321			`2'b10: begin`
322			`if ((rxd_buf) & !(rxd)) begin`
323			`receive <= #1 1'b1;`
324			`end`
325			`end`
326			`default: begin`
327			`if ((rxd_buf) & !(rxd)) begin`
328			`re_start <= #1 1'b1;`
329			`end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin`
330			`re_start <= #1 1'b0;`
331			`receive <= 1'b1;`
332			`end`
333			`end`
334			`endcase`
335
336			`sample <= #1 3'b000;`
337			`sam_cnt <= #1 3'b000;`
338			`re_count <= #1 4'd0;`
339			`sbuf_rxd_tmp <= #1 11'd0;`
340			`r_int <= #1 1'b0;`
341			`end`
342			`end`
343
344			`//`
345			`//`
346			`//`
347	4	markom	`always @(posedge clk or posedge rst)`
348	2	simont	`begin`
349	4	markom	`if (rst) data_out <= #1 8'h0;`
350			else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) \|
351	2	simont	(wr_addr==`OC8051_SFR_SCON))) begin
352			`data_out <= #1 data_in;`
353			`end else begin`
354			`case (rd_addr)`
355			`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
356			`OC8051_SFR_PCON: data_out <= #1 pcon;
357			`default: data_out <= #1 scon;`
358			`endcase`
359			`end`
360			`end`
361
362
363	4	markom	`always @(posedge clk or posedge rst)`
364	2	simont	`begin`
365	4	markom	`if (rst) begin`
366			`trans_buf <= #1 1'b0;`
367			`receive_buf <= #1 1'b0;`
368			`t1_ow_buf <= #1 1'b0;`
369			`rxd_buf <= #1 1'b0;`
370			`end else begin`
371			`trans_buf <= #1 trans;`
372			`receive_buf <= #1 receive;`
373			`t1_ow_buf <= #1 t1_ow;`
374			`rxd_buf <= #1 rxd;`
375			`end`
376	2	simont	`end`
377
378	4	markom	`always @(posedge clk or posedge rst)`
379	2	simont	`begin`
380	4	markom	`if (rst) bit_out <= #1 1'b0;`
381			else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
382	2	simont	`bit_out <= #1 bit_in;`
383			`end else`
384			`bit_out <= #1 scon[rd_addr[2:0]];`
385			`end`
386
387			`endmodule`

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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 5