URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] [out/] [div16u.out] - Blame information for rev 186

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Loading snapshot worklib.oc8051_tb:v .................... Done
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
ncsim> run
 
Warning!  some objects excluded from $dumpvars due to -access -R
            File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16
           Scope: oc8051_tb
            Time: 0 FS + 0
 
time                    1 step           0: pass
time                 4566 step           1: pass
time                 4576 step           2: pass
time                 4586 step           3: pass
time                 4596 step           4: pass
time                 4666 step           5: pass
time                 4676 step           6: pass
time                 4946 step           7: pass
time                 4956 step           8: pass
time                 5096 step           9: pass
time                 5106 step          10: pass
time                 5186 step          11: pass
 
 Done!
Simulation complete via $finish(1) at time 5186 NS + 2
/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155       $finish;
ncsim> exit

Line No.	Rev	Author	Line
1	2	simont	`Loading snapshot worklib.oc8051_tb:v .................... Done`
2			`ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc`
3			`ncsim> run`
4
5			`Warning! some objects excluded from $dumpvars due to -access -R`
6	41	simont	`File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16`
7	2	simont	`Scope: oc8051_tb`
8			`Time: 0 FS + 0`
9
10			`time 1 step 0: pass`
11	41	simont	`time 4566 step 1: pass`
12			`time 4576 step 2: pass`
13			`time 4586 step 3: pass`
14			`time 4596 step 4: pass`
15			`time 4666 step 5: pass`
16			`time 4676 step 6: pass`
17			`time 4946 step 7: pass`
18			`time 4956 step 8: pass`
19			`time 5096 step 9: pass`
20			`time 5106 step 10: pass`
21			`time 5186 step 11: pass`
22	2	simont
23			`Done!`
24	41	simont	`Simulation complete via $finish(1) at time 5186 NS + 2`
25			`/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish;`
26	2	simont	`ncsim> exit`

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] [out/] [div16u.out] - Blame information for rev 186