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[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] [out/] [timer.out] - Blame information for rev 185

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Line No. Rev Author Line
1 2 simont
Loading snapshot worklib.oc8051_tb:v .................... Done
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ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
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ncsim> run
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Warning!  some objects excluded from $dumpvars due to -access -R
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            File: /home/simont/oc8051/bench/verilog/oc8051_tb.v, line = 154, pos = 16
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           Scope: oc8051_tb
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            Time: 0 FS + 0
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time                    1 step           0: pass
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time                36056 step           1: pass
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time                36156 step           2: pass
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time                36246 step           3: pass
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 Done!
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Simulation complete via $finish(1) at time 36246 NS + 2
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/home/simont/oc8051/bench/verilog/oc8051_tb.v:148       $finish;
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ncsim> exit

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