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[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] [out/] [xram_m.out] - Blame information for rev 186

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Line No. Rev Author Line
1 2 simont
Loading snapshot worklib.oc8051_tb:v .................... Done
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ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
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ncsim> run
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Warning!  some objects excluded from $dumpvars due to -access -R
6 41 simont
            File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16
7 2 simont
           Scope: oc8051_tb
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            Time: 0 FS + 0
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time                    1 step           0: pass
11 41 simont
time              1199286 step           1: pass
12 2 simont
 
13 41 simont
 Done!
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Simulation complete via $finish(1) at time 1199286 NS + 2
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/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155       $finish;
16 2 simont
ncsim> exit

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