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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_alu_src_sel.v] - Blame information for rev 81

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 alu source select module                               ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   Multiplexer wiht whitch we select data on alu sources      ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_alu_src_sel (clk, rst, rd, sel1, sel2, sel3,
                     acc, ram, pc, dptr,
 
                     op1, op2, op3,
 
                     src1, src2, src3);
 
 
input clk, rst, rd, sel3;
input [2:0] sel1, sel2;
input [7:0] acc, ram;
input [15:0] dptr;
input [15:0] pc;
 
 
input [7:0] op1, op2, op3;
 
output [7:0] src1, src2, src3;
 
reg [7:0] src1, src2, src3;
 
reg [7:0] op1_r, op2_r, op3_r;
reg [15:0] pc_r;
 
///////
//
// src1
//
///////
always @(sel1 or op1_r or op2_r or op3_r or pc_r or acc or ram)
begin
  case (sel1)
    `OC8051_AS1_RAM: src1 = ram;
    `OC8051_AS1_ACC: src1 = acc;
    `OC8051_AS1_OP1: src1 = op1_r;
    `OC8051_AS1_OP2: src1 = op2_r;
    `OC8051_AS1_OP3: src1 = op3_r;
    `OC8051_AS1_PCH: src1 = pc_r[15:8];
    `OC8051_AS1_PCL: src1 = pc_r[7:0];
    default: src1 = 8'h00;
  endcase
end
 
///////
//
// src2
//
///////
always @(sel2 or op2_r or pc_r or acc or ram or op1_r or pc)
begin
  case (sel2)
    `OC8051_AS2_ACC: src2= acc;
    `OC8051_AS2_ZERO: src2= 8'h00;
    `OC8051_AS2_RAM: src2= ram;
    `OC8051_AS2_OP2: src2= op2_r;
    `OC8051_AS2_PCL: src2= pc_r[7:0];
    default: src2= 8'h00;
  endcase
end
 
///////
//
// src3
//
///////
 
always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)
begin
  case (sel3)
    `OC8051_AS3_DP:   src3= dptr[15:8];
    `OC8051_AS3_PC:   src3= pc[15:8];
    default: src3= 16'h0;
  endcase
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    op1_r <= #1 8'h00;
    op2_r <= #1 8'h00;
    op3_r <= #1 8'h00;
  end else begin
    op1_r <= #1 op1;
    op2_r <= #1 op2;
    op3_r <= #1 op3;
  end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    pc_r <= #1 16'h0;
  end else if (rd) begin
    pc_r <= #1 pc;
  end
endmodule

Line No.	Rev	Author	Line
1	81	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 alu source select module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Multiplexer wiht whitch we select data on alu sources ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48			`//`
49
50			`// synopsys translate_off`
51			`include "oc8051_timescale.v"
52			`// synopsys translate_on`
53
54			`include "oc8051_defines.v"
55
56
57			`module oc8051_alu_src_sel (clk, rst, rd, sel1, sel2, sel3,`
58			`acc, ram, pc, dptr,`
59
60			`op1, op2, op3,`
61
62			`src1, src2, src3);`
63
64
65			`input clk, rst, rd, sel3;`
66			`input [2:0] sel1, sel2;`
67			`input [7:0] acc, ram;`
68			`input [15:0] dptr;`
69			`input [15:0] pc;`
70
71
72			`input [7:0] op1, op2, op3;`
73
74			`output [7:0] src1, src2, src3;`
75
76			`reg [7:0] src1, src2, src3;`
77
78			`reg [7:0] op1_r, op2_r, op3_r;`
79			`reg [15:0] pc_r;`
80
81			`///////`
82			`//`
83			`// src1`
84			`//`
85			`///////`
86			`always @(sel1 or op1_r or op2_r or op3_r or pc_r or acc or ram)`
87			`begin`
88			`case (sel1)`
89			`OC8051_AS1_RAM: src1 = ram;
90			`OC8051_AS1_ACC: src1 = acc;
91			`OC8051_AS1_OP1: src1 = op1_r;
92			`OC8051_AS1_OP2: src1 = op2_r;
93			`OC8051_AS1_OP3: src1 = op3_r;
94			`OC8051_AS1_PCH: src1 = pc_r[15:8];
95			`OC8051_AS1_PCL: src1 = pc_r[7:0];
96			`default: src1 = 8'h00;`
97			`endcase`
98			`end`
99
100			`///////`
101			`//`
102			`// src2`
103			`//`
104			`///////`
105			`always @(sel2 or op2_r or pc_r or acc or ram or op1_r or pc)`
106			`begin`
107			`case (sel2)`
108			`OC8051_AS2_ACC: src2= acc;
109			`OC8051_AS2_ZERO: src2= 8'h00;
110			`OC8051_AS2_RAM: src2= ram;
111			`OC8051_AS2_OP2: src2= op2_r;
112			`OC8051_AS2_PCL: src2= pc_r[7:0];
113			`default: src2= 8'h00;`
114			`endcase`
115			`end`
116
117			`///////`
118			`//`
119			`// src3`
120			`//`
121			`///////`
122
123			`always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)`
124			`begin`
125			`case (sel3)`
126			`OC8051_AS3_DP: src3= dptr[15:8];
127			`OC8051_AS3_PC: src3= pc[15:8];
128			`default: src3= 16'h0;`
129			`endcase`
130			`end`
131
132
133			`always @(posedge clk or posedge rst)`
134			`if (rst) begin`
135			`op1_r <= #1 8'h00;`
136			`op2_r <= #1 8'h00;`
137			`op3_r <= #1 8'h00;`
138			`end else begin`
139			`op1_r <= #1 op1;`
140			`op2_r <= #1 op2;`
141			`op3_r <= #1 op3;`
142			`end`
143
144			`always @(posedge clk or posedge rst)`
145			`if (rst) begin`
146			`pc_r <= #1 16'h0;`
147			`end else if (rd) begin`
148			`pc_r <= #1 pc;`
149			`end`
150			`endmodule`

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_alu_src_sel.v] - Blame information for rev 81