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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_comp.v] - Blame information for rev 95

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1 95 simont
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  8051 compare                                                ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////   compares selected inputs and set eq to 1 if they are equal ////
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////   Is used for conditional jumps.                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   replace CSS_AZ with CSS_DES                                ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.5  2002/09/30 17:33:59  simont
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// prepared header
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_comp (sel, b_in, cy, acc, des, eq);
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//
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// sel          (in)  select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
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// b_in         (in)  bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
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// cy           (in)  carry flag [oc8051_psw.data_out[7] ]
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// acc          (in)  accumulator [oc8051_acc.data_out]
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// ram          (in)  input from ram [oc8051_ram_sel.out_data]
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// op2          (in)  immediate data [oc8051_op_select.op2_out -r]
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// des          (in)  destination from alu [oc8051_alu.des1 -r]
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// eq           (out) if (src1 == src2) eq = 1  [oc8051_decoder.eq]
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//
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input [1:0] sel;
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input b_in, cy;
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input [7:0] acc, des;
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output eq;
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reg eq;
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always @(sel or b_in or cy or acc or des)
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begin
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  case (sel)
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    `OC8051_CSS_AZ : eq = (acc == 8'h00);
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    `OC8051_CSS_DES : eq = (des == 8'h00);
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    `OC8051_CSS_CY : eq = cy;
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    `OC8051_CSS_BIT : eq = b_in;
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    default: eq = 1'bx;
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  endcase
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end
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endmodule

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