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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_decoder.v] - Blame information for rev 54

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1 40 simont
////////////////////////////////////////////////////////////////////// 
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////                                                              ////
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////  8051 core decoder                                           ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
9
////   Main 8051 core module. decodes instruction and creates     ////
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////   control sigals.                                            ////
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////                                                              ////
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////  To Do:                                                      ////
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////   optimize state machine, especially IDS ASS and AS3         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45 46 simont
// CVS Revision History
46 40 simont
//
47 54 simont
// $Log: not supported by cvs2svn $
48
// Revision 1.11  2002/09/30 17:33:59  simont
49
// prepared header
50 46 simont
//
51 54 simont
//
52 40 simont
 
53
// synopsys translate_off
54
`include "oc8051_timescale.v"
55
// synopsys translate_on
56
 
57
`include "oc8051_defines.v"
58
 
59
 
60
 
61
module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
62
wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
63
pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, we_o, reti,
64 54 simont
rmw, stb_o, ack_i, wr_xaddr, istb, ea, iack);
65
 
66 40 simont
//
67
// clk          (in)  clock
68
// rst          (in)  reset
69
// op_in        (in)  operation code [oc8051_op_select.op1]
70
// eq           (in)  compare result [oc8051_comp.eq]
71
// ram_rd_sel   (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
72
// ram_wr_sel   (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
73
// wr           (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
74
// src_sel1     (out) select alu source 1 [oc8051_alu_src1_sel.sel -r]
75
// src_sel2     (out) select alu source 2 [oc8051_alu_src2_sel.sel -r]
76
// src_sel3     (out) select alu source 3 [oc8051_alu_src3_sel.sel -r]
77
// alu_op       (out) alu operation [oc8051_alu.op_code -r]
78
// psw_set      (out) will we remember cy, ac, ov from alu [oc8051_psw.set -r]
79
// cy_sel       (out) carry in alu select [oc8051_cy_select.cy_sel -r]
80
// comp_sel     (out) compare source select [oc8051_comp.sel]
81
// bit_addr     (out) if instruction is bit addresable [oc8051_ram_top.bit_addr -r, oc8051_acc.wr_bit -r, oc8051_b_register.wr_bit-r, oc8051_sp.wr_bit -r, oc8051_dptr.wr_bit -r, oc8051_psw.wr_bit -r, oc8051_indi_addr.wr_bit -r, oc8051_ports.wr_bit -r]
82
// wad2         (out) write acc from destination 2 [oc8051_acc.wad2 -r]
83
// imm_sel      (out) immediate select [oc8051_immediate_sel.sel -r]
84
// pc_wr        (out) pc write [oc8051_pc.wr]
85
// pc_sel       (out) pc select [oc8051_pc.pc_wr_sel]
86
// rom_addr_sel (out) rom address select (alu destination or pc) [oc8051_rom_addr_sel.select]
87
// ext_addr_sel (out) external address select (dptr or Ri) [oc8051_ext_addr_sel.select]
88
// rd           (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
89
// we_o         (out) write to external rom [pin]
90
// reti         (out) return from interrupt [pin]
91
// rmw          (out) read modify write feature [oc8051_ports.rmw]
92 54 simont
// istb         (out) strobe to instruction rom
93
// ea           (in)  extrnal access
94
// iack         (in)  scknowlage from external rom
95 40 simont
//
96
 
97 54 simont
input clk, rst, eq, ack_i, iack, ea;
98 40 simont
input [7:0] op_in;
99
 
100
output wr, reti, we_o, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
101 54 simont
pc_wr, wad2, rmw, stb_o, wr_xaddr, istb;
102 40 simont
output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
103
output [2:0] ram_wr_sel, imm_sel;
104
output [3:0] alu_op;
105
output rd;
106
 
107 54 simont
reg reti, write_x, rmw, stb_buff, we_buff, istb_t;
108 40 simont
reg wr,  bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2, stb, stbw, wr_xaddr;
109
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
110
reg [3:0] alu_op;
111
reg [2:0] ram_wr_sel, imm_sel;
112
 
113
//
114
// state        if 2'b00 then normal execution, sle instructin that need more than one clock
115
// op           instruction buffer
116
reg [1:0] state;
117
reg [7:0] op;
118
 
119
//
120
// if state = 2'b00 then read nex instruction
121
assign rd = !state[0] && !state[1] && !stb_o;
122 54 simont
 
123
assign istb = (!state[1]) || istb_t;
124 40 simont
 
125
assign stb_o = stb_buff || stbw;
126
assign we_o = we_buff;
127
//assign we_o = write_x || we_buff;
128
 
129
//
130
// main block
131
// case of instruction set control signals
132 54 simont
always @(op_in or eq or state or op or stb_o or istb_t)
133 40 simont
begin
134
  if (stb_o) begin
135
          ram_rd_sel = `OC8051_RRS_DC;
136
          ram_wr_sel = `OC8051_RWS_DC;
137
          src_sel1 = `OC8051_ASS_DC;
138
          src_sel2 = `OC8051_ASS_DC;
139
          alu_op = `OC8051_ALU_NOP;
140
          imm_sel = `OC8051_IDS_DC;
141
          wr = 1'b0;
142
          psw_set = `OC8051_PS_NOT;
143
          cy_sel = `OC8051_CY_0;
144
          pc_wr = `OC8051_PCW_N;
145
          pc_sel = `OC8051_PIS_DC;
146
          src_sel3 = `OC8051_AS3_DC;
147
          comp_sel = `OC8051_CSS_DC;
148
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
149
          wad2 = `OC8051_WAD_N;
150
          rom_addr_sel = `OC8051_RAS_PC;
151
  end else begin
152
    case (state)
153
      2'b01: begin
154
    casex (op)
155
      `OC8051_ACALL :begin
156
          ram_rd_sel = `OC8051_RRS_DC;
157
          ram_wr_sel = `OC8051_RWS_SP;
158
          src_sel1 = `OC8051_ASS_IMM;
159
          src_sel2 = `OC8051_ASS_DC;
160
          alu_op = `OC8051_ALU_NOP;
161
          imm_sel = `OC8051_IDS_PCH;
162
          wr = 1'b1;
163
          psw_set = `OC8051_PS_NOT;
164
          cy_sel = `OC8051_CY_0;
165
          pc_wr = `OC8051_PCW_N;
166
          pc_sel = `OC8051_PIS_DC;
167
          comp_sel = `OC8051_CSS_DC;
168
          src_sel3 = `OC8051_AS3_DC;
169
          comp_sel = `OC8051_CSS_DC;
170
          rmw = `OC8051_RMW_N;
171
          bit_addr = 1'b0;
172
          wad2 = `OC8051_WAD_N;
173
          rom_addr_sel = `OC8051_RAS_PC;
174
 
175
 
176
        end
177
      `OC8051_AJMP : begin
178
          ram_rd_sel = `OC8051_RRS_DC;
179
          ram_wr_sel = `OC8051_RWS_DC;
180
          src_sel1 = `OC8051_ASS_DC;
181
          src_sel2 = `OC8051_ASS_DC;
182
          alu_op = `OC8051_ALU_NOP;
183
          imm_sel = `OC8051_IDS_DC;
184
          wr = 1'b0;
185
          psw_set = `OC8051_PS_NOT;
186
          cy_sel = `OC8051_CY_0;
187
          pc_wr = `OC8051_PCW_N;
188
          pc_sel = `OC8051_PIS_DC;
189
          comp_sel = `OC8051_CSS_DC;
190
          src_sel3 = `OC8051_AS3_DC;
191
          comp_sel = `OC8051_CSS_DC;
192
          rmw = `OC8051_RMW_N;
193
          bit_addr = 1'b0;
194
          wad2 = `OC8051_WAD_N;
195
          rom_addr_sel = `OC8051_RAS_PC;
196
 
197
 
198
        end
199
      `OC8051_LCALL :begin
200
          ram_rd_sel = `OC8051_RRS_DC;
201
          ram_wr_sel = `OC8051_RWS_SP;
202
          src_sel1 = `OC8051_ASS_IMM;
203
          src_sel2 = `OC8051_ASS_DC;
204
          alu_op = `OC8051_ALU_NOP;
205
          imm_sel = `OC8051_IDS_PCH;
206
          wr = 1'b1;
207
          psw_set = `OC8051_PS_NOT;
208
          cy_sel = `OC8051_CY_0;
209
          pc_wr = `OC8051_PCW_N;
210
          pc_sel = `OC8051_PIS_DC;
211
          comp_sel = `OC8051_CSS_DC;
212
          src_sel3 = `OC8051_AS3_DC;
213
          comp_sel = `OC8051_CSS_DC;
214
          rmw = `OC8051_RMW_N;
215
          bit_addr = 1'b0;
216
          wad2 = `OC8051_WAD_N;
217
          rom_addr_sel = `OC8051_RAS_PC;
218
 
219
 
220
        end
221
      `OC8051_MOVC_DP :begin
222
          ram_rd_sel = `OC8051_RRS_DC;
223
          ram_wr_sel = `OC8051_RWS_ACC;
224
          src_sel1 = `OC8051_ASS_IMM;
225
          src_sel2 = `OC8051_ASS_DC;
226
          alu_op = `OC8051_ALU_NOP;
227
          wr = 1'b1;
228
          psw_set = `OC8051_PS_NOT;
229
          cy_sel = `OC8051_CY_0;
230
          pc_wr = `OC8051_PCW_N;
231
          pc_sel = `OC8051_PIS_DC;
232
          imm_sel = `OC8051_IDS_OP1;
233
          src_sel3 = `OC8051_AS3_DP;
234
          comp_sel = `OC8051_CSS_DC;
235
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
236
          wad2 = `OC8051_WAD_N;
237
          rom_addr_sel = `OC8051_RAS_PC;
238
 
239
 
240
        end
241
      `OC8051_MOVC_PC :begin
242
          ram_rd_sel = `OC8051_RRS_DC;
243
          ram_wr_sel = `OC8051_RWS_ACC;
244
          src_sel1 = `OC8051_ASS_IMM;
245
          src_sel2 = `OC8051_ASS_DC;
246
          alu_op = `OC8051_ALU_NOP;
247
          wr = 1'b1;
248
          psw_set = `OC8051_PS_NOT;
249
          cy_sel = `OC8051_CY_0;
250
          pc_wr = `OC8051_PCW_N;
251
          pc_sel = `OC8051_PIS_DC;
252
          imm_sel = `OC8051_IDS_OP1;
253
          src_sel3 = `OC8051_AS3_PC;
254
          comp_sel = `OC8051_CSS_DC;
255
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
256
          wad2 = `OC8051_WAD_N;
257
          rom_addr_sel = `OC8051_RAS_PC;
258
 
259
        end
260
      `OC8051_DIV : begin
261
          ram_rd_sel = `OC8051_RRS_D;
262
          ram_wr_sel = `OC8051_RWS_B;
263
          src_sel1 = `OC8051_ASS_ACC;
264
          src_sel2 = `OC8051_ASS_RAM;
265
          alu_op = `OC8051_ALU_DIV;
266
          wr = 1'b1;
267
          psw_set = `OC8051_PS_OV;
268
          cy_sel = `OC8051_CY_0;
269
          pc_wr = `OC8051_PCW_N;
270
          pc_sel = `OC8051_PIS_DC;
271
          imm_sel = `OC8051_IDS_DC;
272
          src_sel3 = `OC8051_AS3_DC;
273
          comp_sel = `OC8051_CSS_DC;
274
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
275
          wad2 = `OC8051_WAD_Y;
276
          rom_addr_sel = `OC8051_RAS_PC;
277
 
278
        end
279
      `OC8051_MUL : begin
280
          ram_rd_sel = `OC8051_RRS_D;
281
          ram_wr_sel = `OC8051_RWS_B;
282
          src_sel1 = `OC8051_ASS_ACC;
283
          src_sel2 = `OC8051_ASS_RAM;
284
          alu_op = `OC8051_ALU_MUL;
285
          wr = 1'b1;
286
          psw_set = `OC8051_PS_OV;
287
          cy_sel = `OC8051_CY_0;
288
          pc_wr = `OC8051_PCW_N;
289
          pc_sel = `OC8051_PIS_DC;
290
          imm_sel = `OC8051_IDS_DC;
291
          src_sel3 = `OC8051_AS3_DC;
292
          comp_sel = `OC8051_CSS_DC;
293
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
294
          wad2 = `OC8051_WAD_Y;
295
          rom_addr_sel = `OC8051_RAS_PC;
296
 
297
        end
298
      default begin
299
          ram_rd_sel = `OC8051_RRS_DC;
300
          ram_wr_sel = `OC8051_RWS_DC;
301
          src_sel1 = `OC8051_ASS_DC;
302
          src_sel2 = `OC8051_ASS_DC;
303
          alu_op = `OC8051_ALU_NOP;
304
          wr = 1'b0;
305
          psw_set = `OC8051_PS_NOT;
306
          cy_sel = `OC8051_CY_0;
307
          pc_wr = `OC8051_PCW_N;
308
          pc_sel = `OC8051_PIS_DC;
309
          imm_sel = `OC8051_IDS_DC;
310
          src_sel3 = `OC8051_AS3_DC;
311
          comp_sel = `OC8051_CSS_DC;
312
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
313
          wad2 = `OC8051_WAD_N;
314
          rom_addr_sel = `OC8051_RAS_PC;
315
 
316
 
317
      end
318
    endcase
319
    end
320
    2'b10:
321
    casex (op)
322
      `OC8051_CJNE_R : begin
323
          ram_rd_sel = `OC8051_RRS_DC;
324
          ram_wr_sel = `OC8051_RWS_DC;
325
          src_sel1 = `OC8051_ASS_DC;
326
          src_sel2 = `OC8051_ASS_DC;
327
          alu_op = `OC8051_ALU_NOP;
328
          wr = 1'b0;
329
          psw_set = `OC8051_PS_NOT;
330
          cy_sel = `OC8051_CY_0;
331
          pc_wr = !eq;
332
          pc_sel = `OC8051_PIS_ALU;
333
          imm_sel = `OC8051_IDS_DC;
334
          src_sel3 = `OC8051_AS3_DC;
335
          comp_sel = `OC8051_CSS_DES;
336
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
337
          wad2 = `OC8051_WAD_N;
338
          rom_addr_sel = `OC8051_RAS_PC;
339
 
340
 
341
        end
342
      `OC8051_CJNE_I : begin
343
          ram_rd_sel = `OC8051_RRS_DC;
344
          ram_wr_sel = `OC8051_RWS_DC;
345
          src_sel1 = `OC8051_ASS_DC;
346
          src_sel2 = `OC8051_ASS_DC;
347
          alu_op = `OC8051_ALU_NOP;
348
          wr = 1'b0;
349
          psw_set = `OC8051_PS_NOT;
350
          cy_sel = `OC8051_CY_0;
351
          pc_wr = !eq;
352
          pc_sel = `OC8051_PIS_ALU;
353
          imm_sel = `OC8051_IDS_DC;
354
          src_sel3 = `OC8051_AS3_DC;
355
          comp_sel = `OC8051_CSS_DES;
356
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
357
          wad2 = `OC8051_WAD_N;
358
          rom_addr_sel = `OC8051_RAS_PC;
359
 
360
 
361
        end
362
      `OC8051_CJNE_D : begin
363
          ram_rd_sel = `OC8051_RRS_DC;
364
          ram_wr_sel = `OC8051_RWS_DC;
365
          src_sel1 = `OC8051_ASS_DC;
366
          src_sel2 = `OC8051_ASS_DC;
367
          alu_op = `OC8051_ALU_NOP;
368
          wr = 1'b0;
369
          psw_set = `OC8051_PS_NOT;
370
          cy_sel = `OC8051_CY_0;
371
          pc_wr = !eq;
372
          pc_sel = `OC8051_PIS_ALU;
373
          imm_sel = `OC8051_IDS_DC;
374
          src_sel3 = `OC8051_AS3_DC;
375
          comp_sel = `OC8051_CSS_DES;
376
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
377
          wad2 = `OC8051_WAD_N;
378
          rom_addr_sel = `OC8051_RAS_PC;
379
 
380
 
381
        end
382
      `OC8051_CJNE_C : begin
383
          ram_rd_sel = `OC8051_RRS_DC;
384
          ram_wr_sel = `OC8051_RWS_DC;
385
          src_sel1 = `OC8051_ASS_DC;
386
          src_sel2 = `OC8051_ASS_DC;
387
          alu_op = `OC8051_ALU_NOP;
388
          wr = 1'b0;
389
          psw_set = `OC8051_PS_NOT;
390
          cy_sel = `OC8051_CY_0;
391
          pc_wr = !eq;
392
          pc_sel = `OC8051_PIS_ALU;
393
          imm_sel = `OC8051_IDS_DC;
394
          src_sel3 = `OC8051_AS3_DC;
395
          comp_sel = `OC8051_CSS_DES;
396
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
397
          wad2 = `OC8051_WAD_N;
398
          rom_addr_sel = `OC8051_RAS_PC;
399
 
400
 
401
        end
402
      `OC8051_DJNZ_R : begin
403
          ram_rd_sel = `OC8051_RRS_DC;
404
          ram_wr_sel = `OC8051_RWS_DC;
405
          src_sel1 = `OC8051_ASS_DC;
406
          src_sel2 = `OC8051_ASS_DC;
407
          alu_op = `OC8051_ALU_NOP;
408
          wr = 1'b0;
409
          psw_set = `OC8051_PS_NOT;
410
          cy_sel = `OC8051_CY_0;
411
          pc_wr = !eq;
412
          pc_sel = `OC8051_PIS_ALU;
413
          imm_sel = `OC8051_IDS_DC;
414
          src_sel3 = `OC8051_AS3_DC;
415
          comp_sel = `OC8051_CSS_DES;
416
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
417
          wad2 = `OC8051_WAD_N;
418
          rom_addr_sel = `OC8051_RAS_PC;
419
 
420
 
421
        end
422
      `OC8051_DJNZ_D : begin
423
          ram_rd_sel = `OC8051_RRS_DC;
424
          ram_wr_sel = `OC8051_RWS_DC;
425
          src_sel1 = `OC8051_ASS_DC;
426
          src_sel2 = `OC8051_ASS_DC;
427
          alu_op = `OC8051_ALU_NOP;
428
          wr = 1'b0;
429
          psw_set = `OC8051_PS_NOT;
430
          cy_sel = `OC8051_CY_0;
431
          pc_wr = !eq;
432
          pc_sel = `OC8051_PIS_ALU;
433
          imm_sel = `OC8051_IDS_DC;
434
          src_sel3 = `OC8051_AS3_DC;
435
          comp_sel = `OC8051_CSS_DES;
436
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
437
          wad2 = `OC8051_WAD_N;
438
          rom_addr_sel = `OC8051_RAS_PC;
439
 
440
 
441
        end
442
      `OC8051_JB : begin
443
          ram_rd_sel = `OC8051_RRS_DC;
444
          ram_wr_sel = `OC8051_RWS_DC;
445
          src_sel1 = `OC8051_ASS_DC;
446
          src_sel2 = `OC8051_ASS_DC;
447
          alu_op = `OC8051_ALU_NOP;
448
          wr = 1'b0;
449
          psw_set = `OC8051_PS_NOT;
450
          cy_sel = `OC8051_CY_0;
451
          pc_wr = eq;
452
          pc_sel = `OC8051_PIS_ALU;
453
          imm_sel = `OC8051_IDS_DC;
454
          src_sel3 = `OC8051_AS3_DC;
455
          comp_sel = `OC8051_CSS_BIT;
456
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
457
          wad2 = `OC8051_WAD_N;
458
          rom_addr_sel = `OC8051_RAS_PC;
459
 
460
 
461
        end
462
      `OC8051_JBC : begin
463
          ram_rd_sel = `OC8051_RRS_DC;
464
          ram_wr_sel = `OC8051_RWS_D;
465
          src_sel1 = `OC8051_ASS_DC;
466
          src_sel2 = `OC8051_ASS_DC;
467
          alu_op = `OC8051_ALU_NOP;
468
          wr = 1'b1;
469
          psw_set = `OC8051_PS_NOT;
470
          cy_sel = `OC8051_CY_0;
471
          pc_wr = eq;
472
          pc_sel = `OC8051_PIS_ALU;
473
          imm_sel = `OC8051_IDS_DC;
474
          src_sel3 = `OC8051_AS3_DC;
475
          comp_sel = `OC8051_CSS_BIT;
476
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
477
          wad2 = `OC8051_WAD_N;
478
          rom_addr_sel = `OC8051_RAS_PC;
479
 
480
 
481
        end
482
      `OC8051_JC : begin
483
          ram_rd_sel = `OC8051_RRS_DC;
484
          ram_wr_sel = `OC8051_RWS_DC;
485
          src_sel1 = `OC8051_ASS_DC;
486
          src_sel2 = `OC8051_ASS_DC;
487
          alu_op = `OC8051_ALU_NOP;
488
          wr = 1'b0;
489
          psw_set = `OC8051_PS_NOT;
490
          cy_sel = `OC8051_CY_0;
491
          pc_wr = eq;
492
          pc_sel = `OC8051_PIS_ALU;
493
          imm_sel = `OC8051_IDS_DC;
494
          src_sel3 = `OC8051_AS3_DC;
495
          comp_sel = `OC8051_CSS_CY;
496
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
497
          wad2 = `OC8051_WAD_N;
498
          rom_addr_sel = `OC8051_RAS_PC;
499
 
500
 
501
        end
502
      `OC8051_JMP : begin
503
          ram_rd_sel = `OC8051_RRS_DC;
504
          ram_wr_sel = `OC8051_RWS_DC;
505
          src_sel1 = `OC8051_ASS_DC;
506
          src_sel2 = `OC8051_ASS_DC;
507
          alu_op = `OC8051_ALU_NOP;
508
          wr = 1'b0;
509
          psw_set = `OC8051_PS_NOT;
510
          cy_sel = `OC8051_CY_0;
511
          pc_wr = `OC8051_PCW_Y;
512
          pc_sel = `OC8051_PIS_ALU;
513
          imm_sel = `OC8051_IDS_DC;
514
          src_sel3 = `OC8051_AS3_DC;
515
          comp_sel = `OC8051_CSS_BIT;
516
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
517
          wad2 = `OC8051_WAD_N;
518
          rom_addr_sel = `OC8051_RAS_PC;
519
 
520
 
521
        end
522
      `OC8051_JNB : begin
523
          ram_rd_sel = `OC8051_RRS_DC;
524
          ram_wr_sel = `OC8051_RWS_DC;
525
          src_sel1 = `OC8051_ASS_DC;
526
          src_sel2 = `OC8051_ASS_DC;
527
          alu_op = `OC8051_ALU_NOP;
528
          wr = 1'b0;
529
          psw_set = `OC8051_PS_NOT;
530
          cy_sel = `OC8051_CY_0;
531
          pc_wr = !eq;
532
          pc_sel = `OC8051_PIS_ALU;
533
          imm_sel = `OC8051_IDS_DC;
534
          src_sel3 = `OC8051_AS3_DC;
535
          comp_sel = `OC8051_CSS_BIT;
536
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
537
          wad2 = `OC8051_WAD_N;
538
          rom_addr_sel = `OC8051_RAS_PC;
539
 
540
 
541
        end
542
      `OC8051_JNC : begin
543
          ram_rd_sel = `OC8051_RRS_DC;
544
          ram_wr_sel = `OC8051_RWS_DC;
545
          src_sel1 = `OC8051_ASS_DC;
546
          src_sel2 = `OC8051_ASS_DC;
547
          alu_op = `OC8051_ALU_NOP;
548
          wr = 1'b0;
549
          psw_set = `OC8051_PS_NOT;
550
          cy_sel = `OC8051_CY_0;
551
          pc_wr = !eq;
552
          pc_sel = `OC8051_PIS_ALU;
553
          imm_sel = `OC8051_IDS_DC;
554
          src_sel3 = `OC8051_AS3_DC;
555
          comp_sel = `OC8051_CSS_CY;
556
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
557
          wad2 = `OC8051_WAD_N;
558
          rom_addr_sel = `OC8051_RAS_PC;
559
 
560
 
561
        end
562
      `OC8051_JNZ : begin
563
          ram_rd_sel = `OC8051_RRS_DC;
564
          ram_wr_sel = `OC8051_RWS_DC;
565
          src_sel1 = `OC8051_ASS_DC;
566
          src_sel2 = `OC8051_ASS_DC;
567
          alu_op = `OC8051_ALU_NOP;
568
          wr = 1'b0;
569
          psw_set = `OC8051_PS_NOT;
570
          cy_sel = `OC8051_CY_0;
571
          pc_wr = !eq;
572
          pc_sel = `OC8051_PIS_ALU;
573
          imm_sel = `OC8051_IDS_DC;
574
          src_sel3 = `OC8051_AS3_DC;
575
          comp_sel = `OC8051_CSS_AZ;
576
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
577
          wad2 = `OC8051_WAD_N;
578
          rom_addr_sel = `OC8051_RAS_PC;
579
 
580
 
581
        end
582
      `OC8051_JZ : begin
583
          ram_rd_sel = `OC8051_RRS_DC;
584
          ram_wr_sel = `OC8051_RWS_DC;
585
          src_sel1 = `OC8051_ASS_DC;
586
          src_sel2 = `OC8051_ASS_DC;
587
          alu_op = `OC8051_ALU_NOP;
588
          wr = 1'b0;
589
          psw_set = `OC8051_PS_NOT;
590
          cy_sel = `OC8051_CY_0;
591
          pc_wr = eq;
592
          pc_sel = `OC8051_PIS_ALU;
593
          imm_sel = `OC8051_IDS_DC;
594
          src_sel3 = `OC8051_AS3_DC;
595
          comp_sel = `OC8051_CSS_AZ;
596
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
597
          wad2 = `OC8051_WAD_N;
598
          rom_addr_sel = `OC8051_RAS_PC;
599
 
600
 
601
        end
602
      `OC8051_MOVC_DP :begin
603
          ram_rd_sel = `OC8051_RRS_DC;
604
          ram_wr_sel = `OC8051_RWS_DC;
605
          src_sel1 = `OC8051_ASS_DC;
606
          src_sel2 = `OC8051_ASS_DC;
607
          alu_op = `OC8051_ALU_NOP;
608
          wr = 1'b0;
609
          psw_set = `OC8051_PS_NOT;
610
          cy_sel = `OC8051_CY_0;
611
          pc_wr = `OC8051_PCW_N;
612
          pc_sel = `OC8051_PIS_DC;
613
          imm_sel = `OC8051_IDS_DC;
614
          src_sel3 = `OC8051_AS3_DP;
615
          comp_sel = `OC8051_CSS_DC;
616
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
617
          wad2 = `OC8051_WAD_N;
618
          rom_addr_sel = `OC8051_RAS_DES;
619
 
620
 
621
        end
622
      `OC8051_MOVC_PC :begin
623
          ram_rd_sel = `OC8051_RRS_DC;
624
          ram_wr_sel = `OC8051_RWS_DC;
625
          src_sel1 = `OC8051_ASS_DC;
626
          src_sel2 = `OC8051_ASS_DC;
627
          alu_op = `OC8051_ALU_NOP;
628
          wr = 1'b0;
629
          psw_set = `OC8051_PS_NOT;
630
          cy_sel = `OC8051_CY_0;
631
          pc_wr = `OC8051_PCW_N;
632
          pc_sel = `OC8051_PIS_DC;
633
          imm_sel = `OC8051_IDS_DC;
634
          src_sel3 = `OC8051_AS3_PC;
635
          comp_sel = `OC8051_CSS_DC;
636
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
637
          wad2 = `OC8051_WAD_N;
638
          rom_addr_sel = `OC8051_RAS_DES;
639
 
640
        end
641
      `OC8051_SJMP : begin
642
          ram_rd_sel = `OC8051_RRS_DC;
643
          ram_wr_sel = `OC8051_RWS_DC;
644
          src_sel1 = `OC8051_ASS_DC;
645
          src_sel2 = `OC8051_ASS_DC;
646
          alu_op = `OC8051_ALU_NOP;
647
          wr = 1'b0;
648
          psw_set = `OC8051_PS_NOT;
649
          cy_sel = `OC8051_CY_0;
650
          pc_wr = `OC8051_PCW_Y;
651
          pc_sel = `OC8051_PIS_ALU;
652
          imm_sel = `OC8051_IDS_DC;
653
          src_sel3 = `OC8051_AS3_DC;
654
          comp_sel = `OC8051_CSS_DC;
655
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
656
          wad2 = `OC8051_WAD_N;
657
          rom_addr_sel = `OC8051_RAS_PC;
658
 
659
        end
660
      `OC8051_DIV : begin
661
          ram_rd_sel = `OC8051_RRS_D;
662
          ram_wr_sel = `OC8051_RWS_B;
663
          src_sel1 = `OC8051_ASS_ACC;
664
          src_sel2 = `OC8051_ASS_RAM;
665
          alu_op = `OC8051_ALU_DIV;
666
          wr = 1'b0;
667
          psw_set = `OC8051_PS_OV;
668
          cy_sel = `OC8051_CY_0;
669
          pc_wr = `OC8051_PCW_N;
670
          pc_sel = `OC8051_PIS_DC;
671
          imm_sel = `OC8051_IDS_DC;
672
          src_sel3 = `OC8051_AS3_DC;
673
          comp_sel = `OC8051_CSS_DC;
674
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
675
          wad2 = `OC8051_WAD_N;
676
          rom_addr_sel = `OC8051_RAS_PC;
677
 
678
        end
679
      `OC8051_MUL : begin
680
          ram_rd_sel = `OC8051_RRS_D;
681
          ram_wr_sel = `OC8051_RWS_B;
682
          src_sel1 = `OC8051_ASS_ACC;
683
          src_sel2 = `OC8051_ASS_RAM;
684
          alu_op = `OC8051_ALU_MUL;
685
          wr = 1'b0;
686
          psw_set = `OC8051_PS_OV;
687
          cy_sel = `OC8051_CY_0;
688
          pc_wr = `OC8051_PCW_N;
689
          pc_sel = `OC8051_PIS_DC;
690
          imm_sel = `OC8051_IDS_DC;
691
          src_sel3 = `OC8051_AS3_DC;
692
          comp_sel = `OC8051_CSS_DC;
693
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
694
          wad2 = `OC8051_WAD_N;
695
          rom_addr_sel = `OC8051_RAS_PC;
696
 
697
        end
698
      default begin
699
          ram_rd_sel = `OC8051_RRS_DC;
700
          ram_wr_sel = `OC8051_RWS_DC;
701
          src_sel1 = `OC8051_ASS_DC;
702
          src_sel2 = `OC8051_ASS_DC;
703
          alu_op = `OC8051_ALU_NOP;
704
          wr = 1'b0;
705
          psw_set = `OC8051_PS_NOT;
706
          cy_sel = `OC8051_CY_0;
707
          pc_wr = `OC8051_PCW_N;
708
          pc_sel = `OC8051_PIS_DC;
709
          imm_sel = `OC8051_IDS_DC;
710
          src_sel3 = `OC8051_AS3_DC;
711
          comp_sel = `OC8051_CSS_DC;
712
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
713
          wad2 = `OC8051_WAD_N;
714
          rom_addr_sel = `OC8051_RAS_PC;
715
 
716
      end
717
    endcase
718
 
719
    2'b11:
720
    casex (op)
721
      `OC8051_CJNE_R : begin
722
          ram_rd_sel = `OC8051_RRS_DC;
723
          ram_wr_sel = `OC8051_RWS_DC;
724
          src_sel1 = `OC8051_ASS_IMM;
725
          src_sel2 = `OC8051_ASS_IMM;
726
          alu_op = `OC8051_ALU_PCS;
727
          wr = 1'b0;
728
          psw_set = `OC8051_PS_NOT;
729
          cy_sel = `OC8051_CY_0;
730
          pc_wr = `OC8051_PCW_N;
731
          pc_sel = `OC8051_PIS_DC;
732
          imm_sel = `OC8051_IDS_OP3_PCL;
733
          src_sel3 = `OC8051_AS3_PC;
734
          comp_sel = `OC8051_CSS_DC;
735
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
736
          wad2 = `OC8051_WAD_N;
737
          rom_addr_sel = `OC8051_RAS_PC;
738
 
739
        end
740
      `OC8051_CJNE_I : begin
741
          ram_rd_sel = `OC8051_RRS_DC;
742
          ram_wr_sel = `OC8051_RWS_DC;
743
          src_sel1 = `OC8051_ASS_IMM;
744
          src_sel2 = `OC8051_ASS_IMM;
745
          alu_op = `OC8051_ALU_PCS;
746
          wr = 1'b0;
747
          psw_set = `OC8051_PS_NOT;
748
          cy_sel = `OC8051_CY_0;
749
          pc_wr = `OC8051_PCW_N;
750
          pc_sel = `OC8051_PIS_DC;
751
          imm_sel = `OC8051_IDS_OP3_PCL;
752
          src_sel3 = `OC8051_AS3_PC;
753
          comp_sel = `OC8051_CSS_DC;
754
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
755
          wad2 = `OC8051_WAD_N;
756
          rom_addr_sel = `OC8051_RAS_PC;
757
 
758
        end
759
      `OC8051_CJNE_D : begin
760
          ram_rd_sel = `OC8051_RRS_DC;
761
          ram_wr_sel = `OC8051_RWS_DC;
762
          src_sel1 = `OC8051_ASS_IMM;
763
          src_sel2 = `OC8051_ASS_IMM;
764
          alu_op = `OC8051_ALU_PCS;
765
          wr = 1'b0;
766
          psw_set = `OC8051_PS_NOT;
767
          cy_sel = `OC8051_CY_0;
768
          pc_wr = `OC8051_PCW_N;
769
          pc_sel = `OC8051_PIS_DC;
770
          imm_sel = `OC8051_IDS_OP3_PCL;
771
          src_sel3 = `OC8051_AS3_PC;
772
          comp_sel = `OC8051_CSS_DC;
773
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
774
          wad2 = `OC8051_WAD_N;
775
          rom_addr_sel = `OC8051_RAS_PC;
776
 
777
        end
778
      `OC8051_CJNE_C : begin
779
          ram_rd_sel = `OC8051_RRS_DC;
780
          ram_wr_sel = `OC8051_RWS_DC;
781
          src_sel1 = `OC8051_ASS_IMM;
782
          src_sel2 = `OC8051_ASS_IMM;
783
          alu_op = `OC8051_ALU_PCS;
784
          wr = 1'b0;
785
          psw_set = `OC8051_PS_NOT;
786
          cy_sel = `OC8051_CY_0;
787
          pc_wr = `OC8051_PCW_N;
788
          pc_sel = `OC8051_PIS_DC;
789
          imm_sel = `OC8051_IDS_OP3_PCL;
790
          src_sel3 = `OC8051_AS3_PC;
791
          comp_sel = `OC8051_CSS_DC;
792
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
793
          wad2 = `OC8051_WAD_N;
794
          rom_addr_sel = `OC8051_RAS_PC;
795
 
796
        end
797
      `OC8051_DJNZ_R : begin
798
          ram_rd_sel = `OC8051_RRS_DC;
799
          ram_wr_sel = `OC8051_RWS_DC;
800
          src_sel1 = `OC8051_ASS_IMM;
801
          src_sel2 = `OC8051_ASS_IMM;
802
          alu_op = `OC8051_ALU_PCS;
803
          wr = 1'b0;
804
          psw_set = `OC8051_PS_NOT;
805
          cy_sel = `OC8051_CY_0;
806
          pc_wr = `OC8051_PCW_N;
807
          pc_sel = `OC8051_PIS_DC;
808
          imm_sel = `OC8051_IDS_OP2_PCL;
809
          src_sel3 = `OC8051_AS3_PC;
810
          comp_sel = `OC8051_CSS_DC;
811
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
812
          wad2 = `OC8051_WAD_N;
813
          rom_addr_sel = `OC8051_RAS_PC;
814
 
815
        end
816
      `OC8051_DJNZ_D : begin
817
          ram_rd_sel = `OC8051_RRS_DC;
818
          ram_wr_sel = `OC8051_RWS_DC;
819
          src_sel1 = `OC8051_ASS_IMM;
820
          src_sel2 = `OC8051_ASS_IMM;
821
          alu_op = `OC8051_ALU_PCS;
822
          wr = 1'b0;
823
          psw_set = `OC8051_PS_NOT;
824
          cy_sel = `OC8051_CY_0;
825
          pc_wr = `OC8051_PCW_N;
826
          pc_sel = `OC8051_PIS_DC;
827
          imm_sel = `OC8051_IDS_OP3_PCL;
828
          src_sel3 = `OC8051_AS3_PC;
829
          comp_sel = `OC8051_CSS_DC;
830
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
831
          wad2 = `OC8051_WAD_N;
832
          rom_addr_sel = `OC8051_RAS_PC;
833
 
834
        end
835
      `OC8051_RET : begin
836
          ram_rd_sel = `OC8051_RRS_SP;
837
          ram_wr_sel = `OC8051_RWS_DC;
838
          src_sel1 = `OC8051_ASS_RAM;
839
          src_sel2 = `OC8051_ASS_DC;
840
          alu_op = `OC8051_ALU_NOP;
841
          wr = 1'b0;
842
          psw_set = `OC8051_PS_NOT;
843
          cy_sel = `OC8051_CY_0;
844
          pc_wr = `OC8051_PCW_Y;
845
          pc_sel = `OC8051_PIS_SP;
846
          imm_sel = `OC8051_IDS_DC;
847
          src_sel3 = `OC8051_AS3_DC;
848
          comp_sel = `OC8051_CSS_DC;
849
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
850
          wad2 = `OC8051_WAD_N;
851
          rom_addr_sel = `OC8051_RAS_PC;
852
 
853
        end
854
      `OC8051_RETI : begin
855
          ram_rd_sel = `OC8051_RRS_SP;
856
          ram_wr_sel = `OC8051_RWS_DC;
857
          src_sel1 = `OC8051_ASS_RAM;
858
          src_sel2 = `OC8051_ASS_DC;
859
          alu_op = `OC8051_ALU_NOP;
860
          wr = 1'b0;
861
          psw_set = `OC8051_PS_NOT;
862
          cy_sel = `OC8051_CY_0;
863
          pc_wr = `OC8051_PCW_Y;
864
          pc_sel = `OC8051_PIS_SP;
865
          imm_sel = `OC8051_IDS_DC;
866
          src_sel3 = `OC8051_AS3_DC;
867
          comp_sel = `OC8051_CSS_DC;
868
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
869
          wad2 = `OC8051_WAD_N;
870
          rom_addr_sel = `OC8051_RAS_PC;
871
 
872
        end
873
      `OC8051_DIV : begin
874
          ram_rd_sel = `OC8051_RRS_D;
875
          ram_wr_sel = `OC8051_RWS_B;
876
          src_sel1 = `OC8051_ASS_ACC;
877
          src_sel2 = `OC8051_ASS_RAM;
878
          alu_op = `OC8051_ALU_DIV;
879
          wr = 1'b0;
880
          psw_set = `OC8051_PS_OV;
881
          cy_sel = `OC8051_CY_0;
882
          pc_wr = `OC8051_PCW_N;
883
          pc_sel = `OC8051_PIS_DC;
884
          imm_sel = `OC8051_IDS_DC;
885
          src_sel3 = `OC8051_AS3_DC;
886
          comp_sel = `OC8051_CSS_DC;
887
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
888
          wad2 = `OC8051_WAD_N;
889
          rom_addr_sel = `OC8051_RAS_PC;
890
 
891
        end
892
      `OC8051_MUL : begin
893
          ram_rd_sel = `OC8051_RRS_D;
894
          ram_wr_sel = `OC8051_RWS_B;
895
          src_sel1 = `OC8051_ASS_ACC;
896
          src_sel2 = `OC8051_ASS_RAM;
897
          alu_op = `OC8051_ALU_MUL;
898
          wr = 1'b0;
899
          psw_set = `OC8051_PS_OV;
900
          cy_sel = `OC8051_CY_0;
901
          pc_wr = `OC8051_PCW_N;
902
          pc_sel = `OC8051_PIS_DC;
903
          imm_sel = `OC8051_IDS_DC;
904
          src_sel3 = `OC8051_AS3_DC;
905
          comp_sel = `OC8051_CSS_DC;
906
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
907
          wad2 = `OC8051_WAD_N;
908
          rom_addr_sel = `OC8051_RAS_PC;
909
 
910
        end
911
     default begin
912
          ram_rd_sel = `OC8051_RRS_DC;
913
          ram_wr_sel = `OC8051_RWS_DC;
914
          src_sel1 = `OC8051_ASS_DC;
915
          src_sel2 = `OC8051_ASS_DC;
916
          alu_op = `OC8051_ALU_NOP;
917
          wr = 1'b0;
918
          psw_set = `OC8051_PS_NOT;
919
          cy_sel = `OC8051_CY_0;
920
          pc_wr = `OC8051_PCW_N;
921
          pc_sel = `OC8051_PIS_DC;
922
          imm_sel = `OC8051_IDS_DC;
923
          src_sel3 = `OC8051_AS3_DC;
924
          comp_sel = `OC8051_CSS_DC;
925
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
926
          wad2 = `OC8051_WAD_N;
927
          rom_addr_sel = `OC8051_RAS_PC;
928
 
929
      end
930
    endcase
931
    default: begin
932
    casex (op_in)
933
      `OC8051_ACALL :begin
934
          ram_rd_sel = `OC8051_RRS_DC;
935
          ram_wr_sel = `OC8051_RWS_SP;
936
          src_sel1 = `OC8051_ASS_IMM;
937
          src_sel2 = `OC8051_ASS_DC;
938
          alu_op = `OC8051_ALU_NOP;
939
          imm_sel = `OC8051_IDS_PCL;
940
          wr = 1'b1;
941
          psw_set = `OC8051_PS_NOT;
942
          cy_sel = `OC8051_CY_0;
943
          pc_wr = `OC8051_PCW_Y;
944
          pc_sel = `OC8051_PIS_I11;
945
          src_sel3 = `OC8051_AS3_DC;
946
          comp_sel = `OC8051_CSS_DC;
947
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
948
          wad2 = `OC8051_WAD_N;
949
          rom_addr_sel = `OC8051_RAS_PC;
950
 
951
        end
952
      `OC8051_AJMP : begin
953
          ram_rd_sel = `OC8051_RRS_DC;
954
          ram_wr_sel = `OC8051_RWS_DC;
955
          src_sel1 = `OC8051_ASS_DC;
956
          src_sel2 = `OC8051_ASS_DC;
957
          alu_op = `OC8051_ALU_NOP;
958
          imm_sel = `OC8051_IDS_DC;
959
          wr = 1'b0;
960
          psw_set = `OC8051_PS_NOT;
961
          cy_sel = `OC8051_CY_0;
962
          pc_wr = `OC8051_PCW_Y;
963
          pc_sel = `OC8051_PIS_I11;
964
          src_sel3 = `OC8051_AS3_DC;
965
          comp_sel = `OC8051_CSS_DC;
966
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
967
          wad2 = `OC8051_WAD_N;
968
          rom_addr_sel = `OC8051_RAS_PC;
969
 
970
        end
971
      `OC8051_ADD_R : begin
972
          ram_rd_sel = `OC8051_RRS_RN;
973
          ram_wr_sel = `OC8051_RWS_ACC;
974
          src_sel1 = `OC8051_ASS_ACC;
975
          src_sel2 = `OC8051_ASS_RAM;
976
          alu_op = `OC8051_ALU_ADD;
977
          wr = 1'b1;
978
          psw_set = `OC8051_PS_AC;
979
          cy_sel = `OC8051_CY_0;
980
          pc_wr = `OC8051_PCW_N;
981
          pc_sel = `OC8051_PIS_DC;
982
          imm_sel = `OC8051_IDS_DC;
983
          src_sel3 = `OC8051_AS3_DC;
984
          comp_sel = `OC8051_CSS_DC;
985
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
986
          wad2 = `OC8051_WAD_N;
987
          rom_addr_sel = `OC8051_RAS_PC;
988
 
989
        end
990
      `OC8051_ADDC_R : begin
991
          ram_rd_sel = `OC8051_RRS_RN;
992
          ram_wr_sel = `OC8051_RWS_ACC;
993
          src_sel1 = `OC8051_ASS_ACC;
994
          src_sel2 = `OC8051_ASS_RAM;
995
          alu_op = `OC8051_ALU_ADD;
996
          wr = 1'b1;
997
          psw_set = `OC8051_PS_AC;
998
          cy_sel = `OC8051_CY_PSW;
999
          pc_wr = `OC8051_PCW_N;
1000
          pc_sel = `OC8051_PIS_DC;
1001
          imm_sel = `OC8051_IDS_DC;
1002
          src_sel3 = `OC8051_AS3_DC;
1003
          comp_sel = `OC8051_CSS_DC;
1004
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1005
          wad2 = `OC8051_WAD_N;
1006
          rom_addr_sel = `OC8051_RAS_PC;
1007
 
1008
        end
1009
      `OC8051_ANL_R : begin
1010
          ram_rd_sel = `OC8051_RRS_RN;
1011
          ram_wr_sel = `OC8051_RWS_ACC;
1012
          src_sel1 = `OC8051_ASS_ACC;
1013
          src_sel2 = `OC8051_ASS_RAM;
1014
          alu_op = `OC8051_ALU_AND;
1015
          wr = 1'b1;
1016
          psw_set = `OC8051_PS_NOT;
1017
          cy_sel = `OC8051_CY_0;
1018
          pc_wr = `OC8051_PCW_N;
1019
          pc_sel = `OC8051_PIS_DC;
1020
          imm_sel = `OC8051_IDS_DC;
1021
          src_sel3 = `OC8051_AS3_DC;
1022
          comp_sel = `OC8051_CSS_DC;
1023
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1024
          wad2 = `OC8051_WAD_N;
1025
          rom_addr_sel = `OC8051_RAS_PC;
1026
 
1027
        end
1028
      `OC8051_CJNE_R : begin
1029
          ram_rd_sel = `OC8051_RRS_RN;
1030
          ram_wr_sel = `OC8051_RWS_DC;
1031
          src_sel1 = `OC8051_ASS_RAM;
1032
          src_sel2 = `OC8051_ASS_IMM;
1033
          alu_op = `OC8051_ALU_SUB;
1034
          wr = 1'b0;
1035
          psw_set = `OC8051_PS_CY;
1036
          cy_sel = `OC8051_CY_0;
1037
          pc_wr = `OC8051_PCW_N;
1038
          pc_sel = `OC8051_PIS_DC;
1039
          imm_sel = `OC8051_IDS_OP2;
1040
          src_sel3 = `OC8051_AS3_DC;
1041
          comp_sel = `OC8051_CSS_DC;
1042
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1043
          wad2 = `OC8051_WAD_N;
1044
          rom_addr_sel = `OC8051_RAS_PC;
1045
 
1046
        end
1047
      `OC8051_DEC_R : begin
1048
          ram_rd_sel = `OC8051_RRS_RN;
1049
          ram_wr_sel = `OC8051_RWS_RN;
1050
          src_sel1 = `OC8051_ASS_RAM;
1051
          src_sel2 = `OC8051_ASS_ZERO;
1052
          alu_op = `OC8051_ALU_SUB;
1053
          wr = 1'b1;
1054
          psw_set = `OC8051_PS_NOT;
1055
          cy_sel = `OC8051_CY_1;
1056
          pc_wr = `OC8051_PCW_N;
1057
          pc_sel = `OC8051_PIS_DC;
1058
          imm_sel = `OC8051_IDS_DC;
1059
          src_sel3 = `OC8051_AS3_DC;
1060
          comp_sel = `OC8051_CSS_DC;
1061
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1062
          wad2 = `OC8051_WAD_N;
1063
          rom_addr_sel = `OC8051_RAS_PC;
1064
 
1065
        end
1066
      `OC8051_DJNZ_R : begin
1067
          ram_rd_sel = `OC8051_RRS_RN;
1068
          ram_wr_sel = `OC8051_RWS_RN;
1069
          src_sel1 = `OC8051_ASS_RAM;
1070
          src_sel2 = `OC8051_ASS_ZERO;
1071
          alu_op = `OC8051_ALU_SUB;
1072
          wr = 1'b1;
1073
          psw_set = `OC8051_PS_NOT;
1074
          cy_sel = `OC8051_CY_1;
1075
          pc_wr = `OC8051_PCW_N;
1076
          pc_sel = `OC8051_PIS_DC;
1077
          imm_sel = `OC8051_IDS_DC;
1078
          src_sel3 = `OC8051_AS3_DC;
1079
          comp_sel = `OC8051_CSS_DC;
1080
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1081
          wad2 = `OC8051_WAD_N;
1082
          rom_addr_sel = `OC8051_RAS_PC;
1083
 
1084
        end
1085
      `OC8051_INC_R : begin
1086
          ram_rd_sel = `OC8051_RRS_RN;
1087
          ram_wr_sel = `OC8051_RWS_RN;
1088
          src_sel1 = `OC8051_ASS_RAM;
1089
          src_sel2 = `OC8051_ASS_ZERO;
1090
          alu_op = `OC8051_ALU_ADD;
1091
          wr = 1'b1;
1092
          psw_set = `OC8051_PS_NOT;
1093
          cy_sel = `OC8051_CY_1;
1094
          pc_wr = `OC8051_PCW_N;
1095
          pc_sel = `OC8051_PIS_DC;
1096
          imm_sel = `OC8051_IDS_DC;
1097
          src_sel3 = `OC8051_AS3_DC;
1098
          comp_sel = `OC8051_CSS_DC;
1099
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1100
          wad2 = `OC8051_WAD_N;
1101
          rom_addr_sel = `OC8051_RAS_PC;
1102
 
1103
        end
1104
      `OC8051_MOV_R : begin
1105
          ram_rd_sel = `OC8051_RRS_RN;
1106
          ram_wr_sel = `OC8051_RWS_ACC;
1107
          src_sel1 = `OC8051_ASS_RAM;
1108
          src_sel2 = `OC8051_ASS_DC;
1109
          alu_op = `OC8051_ALU_NOP;
1110
          wr = 1'b1;
1111
          psw_set = `OC8051_PS_NOT;
1112
          cy_sel = `OC8051_CY_0;
1113
          pc_wr = `OC8051_PCW_N;
1114
          pc_sel = `OC8051_PIS_DC;
1115
          imm_sel = `OC8051_IDS_DC;
1116
          src_sel3 = `OC8051_AS3_DC;
1117
          comp_sel = `OC8051_CSS_DC;
1118
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1119
          wad2 = `OC8051_WAD_N;
1120
          rom_addr_sel = `OC8051_RAS_PC;
1121
 
1122
        end
1123
 
1124
      `OC8051_MOV_AR : begin
1125
          ram_rd_sel = `OC8051_RRS_DC;
1126
          ram_wr_sel = `OC8051_RWS_RN;
1127
          src_sel1 = `OC8051_ASS_ACC;
1128
          src_sel2 = `OC8051_ASS_DC;
1129
          alu_op = `OC8051_ALU_NOP;
1130
          wr = 1'b1;
1131
          psw_set = `OC8051_PS_NOT;
1132
          cy_sel = `OC8051_CY_0;
1133
          pc_wr = `OC8051_PCW_N;
1134
          pc_sel = `OC8051_PIS_DC;
1135
          imm_sel = `OC8051_IDS_DC;
1136
          src_sel3 = `OC8051_AS3_DC;
1137
          comp_sel = `OC8051_CSS_DC;
1138
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1139
          wad2 = `OC8051_WAD_N;
1140
          rom_addr_sel = `OC8051_RAS_PC;
1141
 
1142
        end
1143
      `OC8051_MOV_DR : begin
1144
          ram_rd_sel = `OC8051_RRS_D;
1145
          ram_wr_sel = `OC8051_RWS_RN;
1146
          src_sel1 = `OC8051_ASS_RAM;
1147
          src_sel2 = `OC8051_ASS_DC;
1148
          alu_op = `OC8051_ALU_NOP;
1149
          wr = 1'b1;
1150
          psw_set = `OC8051_PS_NOT;
1151
          cy_sel = `OC8051_CY_0;
1152
          pc_wr = `OC8051_PCW_N;
1153
          pc_sel = `OC8051_PIS_DC;
1154
          imm_sel = `OC8051_IDS_DC;
1155
          src_sel3 = `OC8051_AS3_DC;
1156
          comp_sel = `OC8051_CSS_DC;
1157
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1158
          wad2 = `OC8051_WAD_N;
1159
          rom_addr_sel = `OC8051_RAS_PC;
1160
 
1161
        end
1162
      `OC8051_MOV_CR : begin
1163
          ram_rd_sel = `OC8051_RRS_DC;
1164
          ram_wr_sel = `OC8051_RWS_RN;
1165
          src_sel1 = `OC8051_ASS_IMM;
1166
          src_sel2 = `OC8051_ASS_DC;
1167
          alu_op = `OC8051_ALU_NOP;
1168
          wr = 1'b1;
1169
          psw_set = `OC8051_PS_NOT;
1170
          cy_sel = `OC8051_CY_0;
1171
          pc_wr = `OC8051_PCW_N;
1172
          pc_sel = `OC8051_PIS_DC;
1173
          imm_sel = `OC8051_IDS_OP2;
1174
          src_sel3 = `OC8051_AS3_DC;
1175
          comp_sel = `OC8051_CSS_DC;
1176
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1177
          wad2 = `OC8051_WAD_N;
1178
          rom_addr_sel = `OC8051_RAS_PC;
1179
 
1180
        end
1181
      `OC8051_MOV_RD : begin
1182
          ram_rd_sel = `OC8051_RRS_RN;
1183
          ram_wr_sel = `OC8051_RWS_D;
1184
          src_sel1 = `OC8051_ASS_RAM;
1185
          src_sel2 = `OC8051_ASS_DC;
1186
          alu_op = `OC8051_ALU_NOP;
1187
          wr = 1'b1;
1188
          psw_set = `OC8051_PS_NOT;
1189
          cy_sel = `OC8051_CY_0;
1190
          pc_wr = `OC8051_PCW_N;
1191
          pc_sel = `OC8051_PIS_DC;
1192
          imm_sel = `OC8051_IDS_DC;
1193
          src_sel3 = `OC8051_AS3_DC;
1194
          comp_sel = `OC8051_CSS_DC;
1195
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1196
          wad2 = `OC8051_WAD_N;
1197
          rom_addr_sel = `OC8051_RAS_PC;
1198
 
1199
        end
1200
      `OC8051_ORL_R : begin
1201
          ram_rd_sel = `OC8051_RRS_RN;
1202
          ram_wr_sel = `OC8051_RWS_ACC;
1203
          src_sel1 = `OC8051_ASS_RAM;
1204
          src_sel2 = `OC8051_ASS_ACC;
1205
          alu_op = `OC8051_ALU_OR;
1206
          wr = 1'b1;
1207
          psw_set = `OC8051_PS_NOT;
1208
          cy_sel = `OC8051_CY_0;
1209
          pc_wr = `OC8051_PCW_N;
1210
          pc_sel = `OC8051_PIS_DC;
1211
          imm_sel = `OC8051_IDS_DC;
1212
          src_sel3 = `OC8051_AS3_DC;
1213
          comp_sel = `OC8051_CSS_DC;
1214
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1215
          wad2 = `OC8051_WAD_N;
1216
          rom_addr_sel = `OC8051_RAS_PC;
1217
 
1218
        end
1219
      `OC8051_SUBB_R : begin
1220
          ram_rd_sel = `OC8051_RRS_RN;
1221
          ram_wr_sel = `OC8051_RWS_ACC;
1222
          src_sel1 = `OC8051_ASS_ACC;
1223
          src_sel2 = `OC8051_ASS_RAM;
1224
          alu_op = `OC8051_ALU_SUB;
1225
          wr = 1'b1;
1226
          psw_set = `OC8051_PS_AC;
1227
          cy_sel = `OC8051_CY_PSW;
1228
          pc_wr = `OC8051_PCW_N;
1229
          pc_sel = `OC8051_PIS_DC;
1230
          imm_sel = `OC8051_IDS_DC;
1231
          src_sel3 = `OC8051_AS3_DC;
1232
          comp_sel = `OC8051_CSS_DC;
1233
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1234
          wad2 = `OC8051_WAD_N;
1235
          rom_addr_sel = `OC8051_RAS_PC;
1236
 
1237
        end
1238
      `OC8051_XCH_R : begin
1239
          ram_rd_sel = `OC8051_RRS_RN;
1240
          ram_wr_sel = `OC8051_RWS_RN;
1241
          src_sel1 = `OC8051_ASS_RAM;
1242
          src_sel2 = `OC8051_ASS_ACC;
1243
          alu_op = `OC8051_ALU_XCH;
1244
          wr = 1'b1;
1245
          psw_set = `OC8051_PS_NOT;
1246
          cy_sel = `OC8051_CY_1;
1247
          pc_wr = `OC8051_PCW_N;
1248
          pc_sel = `OC8051_PIS_DC;
1249
          imm_sel = `OC8051_IDS_DC;
1250
          src_sel3 = `OC8051_AS3_DC;
1251
          comp_sel = `OC8051_CSS_DC;
1252
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1253
          wad2 = `OC8051_WAD_Y;
1254
          rom_addr_sel = `OC8051_RAS_PC;
1255
 
1256
        end
1257
      `OC8051_XRL_R : begin
1258
          ram_rd_sel = `OC8051_RRS_RN;
1259
          ram_wr_sel = `OC8051_RWS_ACC;
1260
          src_sel1 = `OC8051_ASS_RAM;
1261
          src_sel2 = `OC8051_ASS_ACC;
1262
          alu_op = `OC8051_ALU_XOR;
1263
          wr = 1'b1;
1264
          psw_set = `OC8051_PS_NOT;
1265
          cy_sel = `OC8051_CY_0;
1266
          pc_wr = `OC8051_PCW_N;
1267
          pc_sel = `OC8051_PIS_DC;
1268
          imm_sel = `OC8051_IDS_DC;
1269
          src_sel3 = `OC8051_AS3_DC;
1270
          comp_sel = `OC8051_CSS_DC;
1271
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1272
          wad2 = `OC8051_WAD_N;
1273
          rom_addr_sel = `OC8051_RAS_PC;
1274
 
1275
        end
1276
 
1277
//op_code [7:1]
1278
      `OC8051_ADD_I : begin
1279
          ram_rd_sel = `OC8051_RRS_I;
1280
          ram_wr_sel = `OC8051_RWS_ACC;
1281
          src_sel1 = `OC8051_ASS_ACC;
1282
          src_sel2 = `OC8051_ASS_RAM;
1283
          alu_op = `OC8051_ALU_ADD;
1284
          wr = 1'b1;
1285
          psw_set = `OC8051_PS_AC;
1286
          cy_sel = `OC8051_CY_0;
1287
          pc_wr = `OC8051_PCW_N;
1288
          pc_sel = `OC8051_PIS_DC;
1289
          imm_sel = `OC8051_IDS_DC;
1290
          src_sel3 = `OC8051_AS3_DC;
1291
          comp_sel = `OC8051_CSS_DC;
1292
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1293
          wad2 = `OC8051_WAD_N;
1294
          rom_addr_sel = `OC8051_RAS_PC;
1295
 
1296
        end
1297
      `OC8051_ADDC_I : begin
1298
          ram_rd_sel = `OC8051_RRS_I;
1299
          ram_wr_sel = `OC8051_RWS_ACC;
1300
          src_sel1 = `OC8051_ASS_ACC;
1301
          src_sel2 = `OC8051_ASS_RAM;
1302
          alu_op = `OC8051_ALU_ADD;
1303
          wr = 1'b1;
1304
          psw_set = `OC8051_PS_AC;
1305
          cy_sel = `OC8051_CY_PSW;
1306
          pc_wr = `OC8051_PCW_N;
1307
          pc_sel = `OC8051_PIS_DC;
1308
          imm_sel = `OC8051_IDS_DC;
1309
          src_sel3 = `OC8051_AS3_DC;
1310
          comp_sel = `OC8051_CSS_DC;
1311
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1312
          wad2 = `OC8051_WAD_N;
1313
          rom_addr_sel = `OC8051_RAS_PC;
1314
 
1315
        end
1316
      `OC8051_ANL_I : begin
1317
          ram_rd_sel = `OC8051_RRS_I;
1318
          ram_wr_sel = `OC8051_RWS_ACC;
1319
          src_sel1 = `OC8051_ASS_ACC;
1320
          src_sel2 = `OC8051_ASS_RAM;
1321
          alu_op = `OC8051_ALU_AND;
1322
          wr = 1'b1;
1323
          psw_set = `OC8051_PS_NOT;
1324
          cy_sel = `OC8051_CY_0;
1325
          pc_wr = `OC8051_PCW_N;
1326
          pc_sel = `OC8051_PIS_DC;
1327
          imm_sel = `OC8051_IDS_DC;
1328
          src_sel3 = `OC8051_AS3_DC;
1329
          comp_sel = `OC8051_CSS_DC;
1330
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1331
          wad2 = `OC8051_WAD_N;
1332
          rom_addr_sel = `OC8051_RAS_PC;
1333
 
1334
        end
1335
      `OC8051_CJNE_I : begin
1336
          ram_rd_sel = `OC8051_RRS_I;
1337
          ram_wr_sel = `OC8051_RWS_DC;
1338
          src_sel1 = `OC8051_ASS_RAM;
1339
          src_sel2 = `OC8051_ASS_IMM;
1340
          alu_op = `OC8051_ALU_SUB;
1341
          wr = 1'b0;
1342
          psw_set = `OC8051_PS_CY;
1343
          cy_sel = `OC8051_CY_0;
1344
          pc_wr = `OC8051_PCW_N;
1345
          pc_sel = `OC8051_PIS_DC;
1346
          imm_sel = `OC8051_IDS_OP2;
1347
          src_sel3 = `OC8051_AS3_DC;
1348
          comp_sel = `OC8051_CSS_DC;
1349
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1350
          wad2 = `OC8051_WAD_N;
1351
          rom_addr_sel = `OC8051_RAS_PC;
1352
 
1353
        end
1354
      `OC8051_DEC_I : begin
1355
          ram_rd_sel = `OC8051_RRS_I;
1356
          ram_wr_sel = `OC8051_RWS_I;
1357
          src_sel1 = `OC8051_ASS_RAM;
1358
          src_sel2 = `OC8051_ASS_ZERO;
1359
          alu_op = `OC8051_ALU_SUB;
1360
          wr = 1'b1;
1361
          psw_set = `OC8051_PS_NOT;
1362
          cy_sel = `OC8051_CY_1;
1363
          pc_wr = `OC8051_PCW_N;
1364
          pc_sel = `OC8051_PIS_DC;
1365
          imm_sel = `OC8051_IDS_DC;
1366
          src_sel3 = `OC8051_AS3_DC;
1367
          comp_sel = `OC8051_CSS_DC;
1368
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1369
          wad2 = `OC8051_WAD_N;
1370
          rom_addr_sel = `OC8051_RAS_PC;
1371
 
1372
        end
1373
      `OC8051_INC_I : begin
1374
          ram_rd_sel = `OC8051_RRS_I;
1375
          ram_wr_sel = `OC8051_RWS_I;
1376
          src_sel1 = `OC8051_ASS_RAM;
1377
          src_sel2 = `OC8051_ASS_ZERO;
1378
          alu_op = `OC8051_ALU_ADD;
1379
          wr = 1'b1;
1380
          psw_set = `OC8051_PS_NOT;
1381
          cy_sel = `OC8051_CY_1;
1382
          pc_wr = `OC8051_PCW_N;
1383
          pc_sel = `OC8051_PIS_DC;
1384
          imm_sel = `OC8051_IDS_DC;
1385
          src_sel3 = `OC8051_AS3_DC;
1386
          comp_sel = `OC8051_CSS_DC;
1387
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1388
          wad2 = `OC8051_WAD_N;
1389
          rom_addr_sel = `OC8051_RAS_PC;
1390
 
1391
        end
1392
      `OC8051_MOV_I : begin
1393
          ram_rd_sel = `OC8051_RRS_I;
1394
          ram_wr_sel = `OC8051_RWS_ACC;
1395
          src_sel1 = `OC8051_ASS_RAM;
1396
          src_sel2 = `OC8051_ASS_DC;
1397
          alu_op = `OC8051_ALU_NOP;
1398
          wr = 1'b1;
1399
          psw_set = `OC8051_PS_NOT;
1400
          cy_sel = `OC8051_CY_0;
1401
          pc_wr = `OC8051_PCW_N;
1402
          pc_sel = `OC8051_PIS_DC;
1403
          imm_sel = `OC8051_IDS_DC;
1404
          src_sel3 = `OC8051_AS3_DC;
1405
          comp_sel = `OC8051_CSS_DC;
1406
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1407
          wad2 = `OC8051_WAD_N;
1408
          rom_addr_sel = `OC8051_RAS_PC;
1409
 
1410
        end
1411
      `OC8051_MOV_ID : begin
1412
          ram_rd_sel = `OC8051_RRS_I;
1413
          ram_wr_sel = `OC8051_RWS_D;
1414
          src_sel1 = `OC8051_ASS_RAM;
1415
          src_sel2 = `OC8051_ASS_DC;
1416
          alu_op = `OC8051_ALU_NOP;
1417
          wr = 1'b1;
1418
          psw_set = `OC8051_PS_NOT;
1419
          cy_sel = `OC8051_CY_0;
1420
          pc_wr = `OC8051_PCW_N;
1421
          pc_sel = `OC8051_PIS_DC;
1422
          imm_sel = `OC8051_IDS_DC;
1423
          src_sel3 = `OC8051_AS3_DC;
1424
          comp_sel = `OC8051_CSS_DC;
1425
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1426
          wad2 = `OC8051_WAD_N;
1427
          rom_addr_sel = `OC8051_RAS_PC;
1428
 
1429
        end
1430
      `OC8051_MOV_AI : begin
1431
          ram_rd_sel = `OC8051_RRS_DC;
1432
          ram_wr_sel = `OC8051_RWS_I;
1433
          src_sel1 = `OC8051_ASS_ACC;
1434
          src_sel2 = `OC8051_ASS_DC;
1435
          alu_op = `OC8051_ALU_NOP;
1436
          wr = 1'b1;
1437
          psw_set = `OC8051_PS_NOT;
1438
          cy_sel = `OC8051_CY_0;
1439
          pc_wr = `OC8051_PCW_N;
1440
          pc_sel = `OC8051_PIS_DC;
1441
          imm_sel = `OC8051_IDS_DC;
1442
          src_sel3 = `OC8051_AS3_DC;
1443
          comp_sel = `OC8051_CSS_DC;
1444
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1445
          wad2 = `OC8051_WAD_N;
1446
          rom_addr_sel = `OC8051_RAS_PC;
1447
 
1448
        end
1449
      `OC8051_MOV_DI : begin
1450
          ram_rd_sel = `OC8051_RRS_D;
1451
          ram_wr_sel = `OC8051_RWS_I;
1452
          src_sel1 = `OC8051_ASS_RAM;
1453
          src_sel2 = `OC8051_ASS_DC;
1454
          alu_op = `OC8051_ALU_NOP;
1455
          wr = 1'b1;
1456
          psw_set = `OC8051_PS_NOT;
1457
          cy_sel = `OC8051_CY_0;
1458
          pc_wr = `OC8051_PCW_N;
1459
          pc_sel = `OC8051_PIS_DC;
1460
          imm_sel = `OC8051_IDS_DC;
1461
          src_sel3 = `OC8051_AS3_DC;
1462
          comp_sel = `OC8051_CSS_DC;
1463
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1464
          wad2 = `OC8051_WAD_N;
1465
          rom_addr_sel = `OC8051_RAS_PC;
1466
 
1467
        end
1468
      `OC8051_MOV_CI : begin
1469
          ram_rd_sel = `OC8051_RRS_DC;
1470
          ram_wr_sel = `OC8051_RWS_I;
1471
          src_sel1 = `OC8051_ASS_IMM;
1472
          src_sel2 = `OC8051_ASS_DC;
1473
          alu_op = `OC8051_ALU_NOP;
1474
          wr = 1'b1;
1475
          psw_set = `OC8051_PS_NOT;
1476
          cy_sel = `OC8051_CY_0;
1477
          pc_wr = `OC8051_PCW_N;
1478
          pc_sel = `OC8051_PIS_DC;
1479
          imm_sel = `OC8051_IDS_OP2;
1480
          src_sel3 = `OC8051_AS3_DC;
1481
          comp_sel = `OC8051_CSS_DC;
1482
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1483
          wad2 = `OC8051_WAD_N;
1484
          rom_addr_sel = `OC8051_RAS_PC;
1485
 
1486
        end
1487
      `OC8051_MOVX_IA : begin
1488
          ram_rd_sel = `OC8051_RRS_DC;
1489
          ram_wr_sel = `OC8051_RWS_ACC;
1490
          src_sel1 = `OC8051_ASS_XRAM;
1491
          src_sel2 = `OC8051_ASS_DC;
1492
          alu_op = `OC8051_ALU_NOP;
1493
          wr = 1'b0;
1494
          psw_set = `OC8051_PS_NOT;
1495
          cy_sel = `OC8051_CY_0;
1496
          pc_wr = `OC8051_PCW_N;
1497
          pc_sel = `OC8051_PIS_DC;
1498
          imm_sel = `OC8051_IDS_OP2;
1499
          src_sel3 = `OC8051_AS3_DC;
1500
          comp_sel = `OC8051_CSS_DC;
1501
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1502
          wad2 = `OC8051_WAD_N;
1503
          rom_addr_sel = `OC8051_RAS_PC;
1504
        end
1505
      `OC8051_MOVX_AI :begin
1506
          ram_rd_sel = `OC8051_RRS_DC;
1507
          ram_wr_sel = `OC8051_RWS_ACC;
1508
          src_sel1 = `OC8051_ASS_DC;
1509
          src_sel2 = `OC8051_ASS_DC;
1510
          alu_op = `OC8051_ALU_NOP;
1511
          wr = 1'b0;
1512
          psw_set = `OC8051_PS_NOT;
1513
          cy_sel = `OC8051_CY_0;
1514
          pc_wr = `OC8051_PCW_N;
1515
          pc_sel = `OC8051_PIS_DC;
1516
          imm_sel = `OC8051_IDS_OP2;
1517
          src_sel3 = `OC8051_AS3_DC;
1518
          comp_sel = `OC8051_CSS_DC;
1519
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1520
          wad2 = `OC8051_WAD_N;
1521
          rom_addr_sel = `OC8051_RAS_PC;
1522
        end
1523
      `OC8051_ORL_I : begin
1524
          ram_rd_sel = `OC8051_RRS_I;
1525
          ram_wr_sel = `OC8051_RWS_ACC;
1526
          src_sel1 = `OC8051_ASS_RAM;
1527
          src_sel2 = `OC8051_ASS_ACC;
1528
          alu_op = `OC8051_ALU_OR;
1529
          wr = 1'b1;
1530
          psw_set = `OC8051_PS_NOT;
1531
          cy_sel = `OC8051_CY_0;
1532
          pc_wr = `OC8051_PCW_N;
1533
          pc_sel = `OC8051_PIS_DC;
1534
          imm_sel = `OC8051_IDS_DC;
1535
          src_sel3 = `OC8051_AS3_DC;
1536
          comp_sel = `OC8051_CSS_DC;
1537
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1538
          wad2 = `OC8051_WAD_N;
1539
          rom_addr_sel = `OC8051_RAS_PC;
1540
 
1541
        end
1542
      `OC8051_SUBB_I : begin
1543
          ram_rd_sel = `OC8051_RRS_I;
1544
          ram_wr_sel = `OC8051_RWS_ACC;
1545
          src_sel1 = `OC8051_ASS_ACC;
1546
          src_sel2 = `OC8051_ASS_RAM;
1547
          alu_op = `OC8051_ALU_SUB;
1548
          wr = 1'b1;
1549
          psw_set = `OC8051_PS_AC;
1550
          cy_sel = `OC8051_CY_PSW;
1551
          pc_wr = `OC8051_PCW_N;
1552
          pc_sel = `OC8051_PIS_DC;
1553
          imm_sel = `OC8051_IDS_DC;
1554
          src_sel3 = `OC8051_AS3_DC;
1555
          comp_sel = `OC8051_CSS_DC;
1556
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1557
          wad2 = `OC8051_WAD_N;
1558
          rom_addr_sel = `OC8051_RAS_PC;
1559
 
1560
        end
1561
      `OC8051_XCH_I : begin
1562
          ram_rd_sel = `OC8051_RRS_I;
1563
          ram_wr_sel = `OC8051_RWS_I;
1564
          src_sel1 = `OC8051_ASS_RAM;
1565
          src_sel2 = `OC8051_ASS_ACC;
1566
          alu_op = `OC8051_ALU_XCH;
1567
          wr = 1'b1;
1568
          psw_set = `OC8051_PS_NOT;
1569
          cy_sel = `OC8051_CY_1;
1570
          pc_wr = `OC8051_PCW_N;
1571
          pc_sel = `OC8051_PIS_DC;
1572
          imm_sel = `OC8051_IDS_DC;
1573
          src_sel3 = `OC8051_AS3_DC;
1574
          comp_sel = `OC8051_CSS_DC;
1575
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1576
          wad2 = `OC8051_WAD_Y;
1577
          rom_addr_sel = `OC8051_RAS_PC;
1578
 
1579
        end
1580
      `OC8051_XCHD :begin
1581
          ram_rd_sel = `OC8051_RRS_I;
1582
          ram_wr_sel = `OC8051_RWS_I;
1583
          src_sel1 = `OC8051_ASS_RAM;
1584
          src_sel2 = `OC8051_ASS_ACC;
1585
          alu_op = `OC8051_ALU_XCH;
1586
          wr = 1'b1;
1587
          psw_set = `OC8051_PS_NOT;
1588
          cy_sel = `OC8051_CY_0;
1589
          pc_wr = `OC8051_PCW_N;
1590
          pc_sel = `OC8051_PIS_DC;
1591
          imm_sel = `OC8051_IDS_DC;
1592
          src_sel3 = `OC8051_AS3_DC;
1593
          comp_sel = `OC8051_CSS_DC;
1594
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1595
          wad2 = `OC8051_WAD_Y;
1596
          rom_addr_sel = `OC8051_RAS_PC;
1597
 
1598
        end
1599
      `OC8051_XRL_I : begin
1600
          ram_rd_sel = `OC8051_RRS_I;
1601
          ram_wr_sel = `OC8051_RWS_ACC;
1602
          src_sel1 = `OC8051_ASS_RAM;
1603
          src_sel2 = `OC8051_ASS_ACC;
1604
          alu_op = `OC8051_ALU_XOR;
1605
          wr = 1'b1;
1606
          psw_set = `OC8051_PS_NOT;
1607
          cy_sel = `OC8051_CY_0;
1608
          pc_wr = `OC8051_PCW_N;
1609
          pc_sel = `OC8051_PIS_DC;
1610
          imm_sel = `OC8051_IDS_DC;
1611
          src_sel3 = `OC8051_AS3_DC;
1612
          comp_sel = `OC8051_CSS_DC;
1613
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1614
          wad2 = `OC8051_WAD_N;
1615
          rom_addr_sel = `OC8051_RAS_PC;
1616
 
1617
        end
1618
 
1619
//op_code [7:0]
1620
      `OC8051_ADD_D : begin
1621
          ram_rd_sel = `OC8051_RRS_D;
1622
          ram_wr_sel = `OC8051_RWS_ACC;
1623
          src_sel1 = `OC8051_ASS_ACC;
1624
          src_sel2 = `OC8051_ASS_RAM;
1625
          alu_op = `OC8051_ALU_ADD;
1626
          wr = 1'b1;
1627
          psw_set = `OC8051_PS_AC;
1628
          cy_sel = `OC8051_CY_0;
1629
          pc_wr = `OC8051_PCW_N;
1630
          pc_sel = `OC8051_PIS_DC;
1631
          imm_sel = `OC8051_IDS_DC;
1632
          src_sel3 = `OC8051_AS3_DC;
1633
          comp_sel = `OC8051_CSS_DC;
1634
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1635
          wad2 = `OC8051_WAD_N;
1636
          rom_addr_sel = `OC8051_RAS_PC;
1637
 
1638
        end
1639
      `OC8051_ADD_C : begin
1640
          ram_rd_sel = `OC8051_RRS_DC;
1641
          ram_wr_sel = `OC8051_RWS_ACC;
1642
          src_sel1 = `OC8051_ASS_IMM;
1643
          src_sel2 = `OC8051_ASS_ACC;
1644
          alu_op = `OC8051_ALU_ADD;
1645
          wr = 1'b1;
1646
          psw_set = `OC8051_PS_AC;
1647
          cy_sel = `OC8051_CY_0;
1648
          pc_wr = `OC8051_PCW_N;
1649
          pc_sel = `OC8051_PIS_DC;
1650
          imm_sel = `OC8051_IDS_OP2;
1651
          src_sel3 = `OC8051_AS3_DC;
1652
          comp_sel = `OC8051_CSS_DC;
1653
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1654
          wad2 = `OC8051_WAD_N;
1655
          rom_addr_sel = `OC8051_RAS_PC;
1656
 
1657
        end
1658
      `OC8051_ADDC_D : begin
1659
          ram_rd_sel = `OC8051_RRS_D;
1660
          ram_wr_sel = `OC8051_RWS_ACC;
1661
          src_sel1 = `OC8051_ASS_ACC;
1662
          src_sel2 = `OC8051_ASS_RAM;
1663
          alu_op = `OC8051_ALU_ADD;
1664
          wr = 1'b1;
1665
          psw_set = `OC8051_PS_AC;
1666
          cy_sel = `OC8051_CY_PSW;
1667
          pc_wr = `OC8051_PCW_N;
1668
          pc_sel = `OC8051_PIS_DC;
1669
          imm_sel = `OC8051_IDS_DC;
1670
          src_sel3 = `OC8051_AS3_DC;
1671
          comp_sel = `OC8051_CSS_DC;
1672
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1673
          wad2 = `OC8051_WAD_N;
1674
          rom_addr_sel = `OC8051_RAS_PC;
1675
 
1676
        end
1677
      `OC8051_ADDC_C : begin
1678
          ram_rd_sel = `OC8051_RRS_DC;
1679
          ram_wr_sel = `OC8051_RWS_ACC;
1680
          src_sel1 = `OC8051_ASS_IMM;
1681
          src_sel2 = `OC8051_ASS_ACC;
1682
          alu_op = `OC8051_ALU_ADD;
1683
          wr = 1'b1;
1684
          psw_set = `OC8051_PS_AC;
1685
          cy_sel = `OC8051_CY_PSW;
1686
          pc_wr = `OC8051_PCW_N;
1687
          pc_sel = `OC8051_PIS_DC;
1688
          imm_sel = `OC8051_IDS_OP2;
1689
          src_sel3 = `OC8051_AS3_DC;
1690
          comp_sel = `OC8051_CSS_DC;
1691
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1692
          wad2 = `OC8051_WAD_N;
1693
          rom_addr_sel = `OC8051_RAS_PC;
1694
 
1695
        end
1696
      `OC8051_ANL_D : begin
1697
          ram_rd_sel = `OC8051_RRS_D;
1698
          ram_wr_sel = `OC8051_RWS_ACC;
1699
          src_sel1 = `OC8051_ASS_ACC;
1700
          src_sel2 = `OC8051_ASS_RAM;
1701
          alu_op = `OC8051_ALU_AND;
1702
          wr = 1'b1;
1703
          psw_set = `OC8051_PS_NOT;
1704
          cy_sel = `OC8051_CY_0;
1705
          pc_wr = `OC8051_PCW_N;
1706
          pc_sel = `OC8051_PIS_DC;
1707
          imm_sel = `OC8051_IDS_DC;
1708
          src_sel3 = `OC8051_AS3_DC;
1709
          comp_sel = `OC8051_CSS_DC;
1710
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1711
          wad2 = `OC8051_WAD_N;
1712
          rom_addr_sel = `OC8051_RAS_PC;
1713
 
1714
        end
1715
      `OC8051_ANL_C : begin
1716
          ram_rd_sel = `OC8051_RRS_DC;
1717
          ram_wr_sel = `OC8051_RWS_ACC;
1718
          src_sel1 = `OC8051_ASS_IMM;
1719
          src_sel2 = `OC8051_ASS_ACC;
1720
          alu_op = `OC8051_ALU_AND;
1721
          wr = 1'b1;
1722
          psw_set = `OC8051_PS_NOT;
1723
          cy_sel = `OC8051_CY_0;
1724
          pc_wr = `OC8051_PCW_N;
1725
          pc_sel = `OC8051_PIS_DC;
1726
          imm_sel = `OC8051_IDS_OP2;
1727
          src_sel3 = `OC8051_AS3_DC;
1728
          comp_sel = `OC8051_CSS_DC;
1729
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1730
          wad2 = `OC8051_WAD_N;
1731
          rom_addr_sel = `OC8051_RAS_PC;
1732
 
1733
        end
1734
      `OC8051_ANL_DD : begin
1735
          ram_rd_sel = `OC8051_RRS_D;
1736
          ram_wr_sel = `OC8051_RWS_D;
1737
          src_sel1 = `OC8051_ASS_ACC;
1738
          src_sel2 = `OC8051_ASS_RAM;
1739
          alu_op = `OC8051_ALU_AND;
1740
          wr = 1'b1;
1741
          psw_set = `OC8051_PS_NOT;
1742
          cy_sel = `OC8051_CY_0;
1743
          pc_wr = `OC8051_PCW_N;
1744
          pc_sel = `OC8051_PIS_DC;
1745
          imm_sel = `OC8051_IDS_DC;
1746
          src_sel3 = `OC8051_AS3_DC;
1747
          comp_sel = `OC8051_CSS_DC;
1748
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1749
          wad2 = `OC8051_WAD_N;
1750
          rom_addr_sel = `OC8051_RAS_PC;
1751
 
1752
        end
1753
      `OC8051_ANL_DC : begin
1754
          ram_rd_sel = `OC8051_RRS_D;
1755
          ram_wr_sel = `OC8051_RWS_D;
1756
          src_sel1 = `OC8051_ASS_IMM;
1757
          src_sel2 = `OC8051_ASS_RAM;
1758
          alu_op = `OC8051_ALU_AND;
1759
          wr = 1'b1;
1760
          psw_set = `OC8051_PS_NOT;
1761
          cy_sel = `OC8051_CY_0;
1762
          pc_wr = `OC8051_PCW_N;
1763
          pc_sel = `OC8051_PIS_DC;
1764
          imm_sel = `OC8051_IDS_OP3;
1765
          src_sel3 = `OC8051_AS3_DC;
1766
          comp_sel = `OC8051_CSS_DC;
1767
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1768
          wad2 = `OC8051_WAD_N;
1769
          rom_addr_sel = `OC8051_RAS_PC;
1770
 
1771
        end
1772
      `OC8051_ANL_B : begin
1773
          ram_rd_sel = `OC8051_RRS_D;
1774
          ram_wr_sel = `OC8051_RWS_DC;
1775
          src_sel1 = `OC8051_ASS_DC;
1776
          src_sel2 = `OC8051_ASS_DC;
1777
          alu_op = `OC8051_ALU_AND;
1778
          wr = 1'b0;
1779
          psw_set = `OC8051_PS_CY;
1780
          cy_sel = `OC8051_CY_PSW;
1781
          pc_wr = `OC8051_PCW_N;
1782
          pc_sel = `OC8051_PIS_DC;
1783
          imm_sel = `OC8051_IDS_DC;
1784
          src_sel3 = `OC8051_AS3_DC;
1785
          comp_sel = `OC8051_CSS_DC;
1786
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1787
          wad2 = `OC8051_WAD_N;
1788
          rom_addr_sel = `OC8051_RAS_PC;
1789
 
1790
        end
1791
      `OC8051_ANL_NB : begin
1792
          ram_rd_sel = `OC8051_RRS_D;
1793
          ram_wr_sel = `OC8051_RWS_DC;
1794
          src_sel1 = `OC8051_ASS_DC;
1795
          src_sel2 = `OC8051_ASS_DC;
1796
          alu_op = `OC8051_ALU_RR;
1797
          wr = 1'b0;
1798
          psw_set = `OC8051_PS_CY;
1799
          cy_sel = `OC8051_CY_PSW;
1800
          pc_wr = `OC8051_PCW_N;
1801
          pc_sel = `OC8051_PIS_DC;
1802
          imm_sel = `OC8051_IDS_DC;
1803
          src_sel3 = `OC8051_AS3_DC;
1804
          comp_sel = `OC8051_CSS_DC;
1805
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1806
          wad2 = `OC8051_WAD_N;
1807
          rom_addr_sel = `OC8051_RAS_PC;
1808
 
1809
        end
1810
      `OC8051_CJNE_D : begin
1811
          ram_rd_sel = `OC8051_RRS_D;
1812
          ram_wr_sel = `OC8051_RWS_DC;
1813
          src_sel1 = `OC8051_ASS_ACC;
1814
          src_sel2 = `OC8051_ASS_RAM;
1815
          alu_op = `OC8051_ALU_SUB;
1816
          wr = 1'b0;
1817
          psw_set = `OC8051_PS_CY;
1818
          cy_sel = `OC8051_CY_0;
1819
          pc_wr = `OC8051_PCW_N;
1820
          pc_sel = `OC8051_PIS_DC;
1821
          imm_sel = `OC8051_IDS_DC;
1822
          src_sel3 = `OC8051_AS3_DC;
1823
          comp_sel = `OC8051_CSS_DC;
1824
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1825
          wad2 = `OC8051_WAD_N;
1826
          rom_addr_sel = `OC8051_RAS_PC;
1827
 
1828
        end
1829
      `OC8051_CJNE_C : begin
1830
          ram_rd_sel = `OC8051_RRS_DC;
1831
          ram_wr_sel = `OC8051_RWS_DC;
1832
          src_sel1 = `OC8051_ASS_ACC;
1833
          src_sel2 = `OC8051_ASS_IMM;
1834
          alu_op = `OC8051_ALU_SUB;
1835
          wr = 1'b0;
1836
          psw_set = `OC8051_PS_CY;
1837
          cy_sel = `OC8051_CY_0;
1838
          pc_wr = `OC8051_PCW_N;
1839
          pc_sel = `OC8051_PIS_DC;
1840
          imm_sel = `OC8051_IDS_OP2;
1841
          src_sel3 = `OC8051_AS3_DC;
1842
          comp_sel = `OC8051_CSS_DC;
1843
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1844
          wad2 = `OC8051_WAD_N;
1845
          rom_addr_sel = `OC8051_RAS_PC;
1846
 
1847
        end
1848
      `OC8051_CLR_A : begin
1849
          ram_rd_sel = `OC8051_RRS_DC;
1850
          ram_wr_sel = `OC8051_RWS_ACC;
1851
          src_sel1 = `OC8051_ASS_ACC;
1852
          src_sel2 = `OC8051_ASS_ACC;
1853
          alu_op = `OC8051_ALU_SUB;
1854
          wr = 1'b1;
1855
          psw_set = `OC8051_PS_NOT;
1856
          cy_sel = `OC8051_CY_0;
1857
          pc_wr = `OC8051_PCW_N;
1858
          pc_sel = `OC8051_PIS_DC;
1859
          imm_sel = `OC8051_IDS_DC;
1860
          src_sel3 = `OC8051_AS3_PC;
1861
          comp_sel = `OC8051_CSS_DC;
1862
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1863
          wad2 = `OC8051_WAD_N;
1864
          rom_addr_sel = `OC8051_RAS_PC;
1865
 
1866
        end
1867
      `OC8051_CLR_C : begin
1868
          ram_rd_sel = `OC8051_RRS_DC;
1869
          ram_wr_sel = `OC8051_RWS_DC;
1870
          src_sel1 = `OC8051_ASS_DC;
1871
          src_sel2 = `OC8051_ASS_DC;
1872
          alu_op = `OC8051_ALU_NOP;
1873
          wr = 1'b0;
1874
          psw_set = `OC8051_PS_CY;
1875
          cy_sel = `OC8051_CY_0;
1876
          pc_wr = `OC8051_PCW_N;
1877
          pc_sel = `OC8051_PIS_DC;
1878
          imm_sel = `OC8051_IDS_DC;
1879
          src_sel3 = `OC8051_AS3_PC;
1880
          comp_sel = `OC8051_CSS_DC;
1881
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1882
          wad2 = `OC8051_WAD_N;
1883
          rom_addr_sel = `OC8051_RAS_PC;
1884
 
1885
        end
1886
      `OC8051_CLR_B : begin
1887
          ram_rd_sel = `OC8051_RRS_D;
1888
          ram_wr_sel = `OC8051_RWS_D;
1889
          src_sel1 = `OC8051_ASS_DC;
1890
          src_sel2 = `OC8051_ASS_DC;
1891
          alu_op = `OC8051_ALU_NOP;
1892
          wr = 1'b1;
1893
          psw_set = `OC8051_PS_NOT;
1894
          cy_sel = `OC8051_CY_0;
1895
          pc_wr = `OC8051_PCW_N;
1896
          pc_sel = `OC8051_PIS_DC;
1897
          imm_sel = `OC8051_IDS_DC;
1898
          src_sel3 = `OC8051_AS3_PC;
1899
          comp_sel = `OC8051_CSS_DC;
1900
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1901
          wad2 = `OC8051_WAD_N;
1902
          rom_addr_sel = `OC8051_RAS_PC;
1903
 
1904
        end
1905
      `OC8051_CPL_A : begin
1906
          ram_rd_sel = `OC8051_RRS_DC;
1907
          ram_wr_sel = `OC8051_RWS_ACC;
1908
          src_sel1 = `OC8051_ASS_ACC;
1909
          src_sel2 = `OC8051_ASS_DC;
1910
          alu_op = `OC8051_ALU_NOT;
1911
          wr = 1'b1;
1912
          psw_set = `OC8051_PS_NOT;
1913
          cy_sel = `OC8051_CY_0;
1914
          pc_wr = `OC8051_PCW_N;
1915
          pc_sel = `OC8051_PIS_DC;
1916
          imm_sel = `OC8051_IDS_OP3;   ///****
1917
          src_sel3 = `OC8051_AS3_DC;
1918
          comp_sel = `OC8051_CSS_DC;
1919
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1920
          wad2 = `OC8051_WAD_N;
1921
          rom_addr_sel = `OC8051_RAS_PC;
1922
 
1923
        end
1924
      `OC8051_CPL_C : begin
1925
          ram_rd_sel = `OC8051_RRS_DC;
1926
          ram_wr_sel = `OC8051_RWS_DC;
1927
          src_sel1 = `OC8051_ASS_DC;
1928
          src_sel2 = `OC8051_ASS_DC;
1929
          alu_op = `OC8051_ALU_NOT;
1930
          wr = 1'b0;
1931
          psw_set = `OC8051_PS_CY;
1932
          cy_sel = `OC8051_CY_PSW;
1933
          pc_wr = `OC8051_PCW_N;
1934
          pc_sel = `OC8051_PIS_DC;
1935
          imm_sel = `OC8051_IDS_OP3;  ///*****
1936
          src_sel3 = `OC8051_AS3_DC;
1937
          comp_sel = `OC8051_CSS_DC;
1938
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1939
          wad2 = `OC8051_WAD_N;
1940
          rom_addr_sel = `OC8051_RAS_PC;
1941
 
1942
        end
1943
      `OC8051_CPL_B : begin
1944
          ram_rd_sel = `OC8051_RRS_D;
1945
          ram_wr_sel = `OC8051_RWS_D;
1946
          src_sel1 = `OC8051_ASS_DC;
1947
          src_sel2 = `OC8051_ASS_DC;
1948
          alu_op = `OC8051_ALU_NOT;
1949
          wr = 1'b1;
1950
          psw_set = `OC8051_PS_NOT;
1951
          cy_sel = `OC8051_CY_RAM;
1952
          pc_wr = `OC8051_PCW_N;
1953
          pc_sel = `OC8051_PIS_DC;
1954
          imm_sel = `OC8051_IDS_OP3;  ///***
1955
          src_sel3 = `OC8051_AS3_DC;
1956
          comp_sel = `OC8051_CSS_DC;
1957
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1958
          wad2 = `OC8051_WAD_N;
1959
          rom_addr_sel = `OC8051_RAS_PC;
1960
 
1961
        end
1962
      `OC8051_DA : begin
1963
          ram_rd_sel = `OC8051_RRS_DC;
1964
          ram_wr_sel = `OC8051_RWS_ACC;
1965
          src_sel1 = `OC8051_ASS_ACC;
1966
          src_sel2 = `OC8051_ASS_DC;
1967
          alu_op = `OC8051_ALU_DA;
1968
          wr = 1'b1;
1969
          psw_set = `OC8051_PS_CY;
1970
          cy_sel = `OC8051_CY_PSW;
1971
          pc_wr = `OC8051_PCW_N;
1972
          pc_sel = `OC8051_PIS_DC;
1973
          imm_sel = `OC8051_IDS_DC;
1974
          src_sel3 = `OC8051_AS3_DC;
1975
          comp_sel = `OC8051_CSS_DC;
1976
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1977
          wad2 = `OC8051_WAD_N;
1978
          rom_addr_sel = `OC8051_RAS_PC;
1979
 
1980
        end
1981
      `OC8051_DEC_A : begin
1982
          ram_rd_sel = `OC8051_RRS_DC;
1983
          ram_wr_sel = `OC8051_RWS_ACC;
1984
          src_sel1 = `OC8051_ASS_ACC;
1985
          src_sel2 = `OC8051_ASS_ZERO;
1986
          alu_op = `OC8051_ALU_SUB;
1987
          wr = 1'b1;
1988
          psw_set = `OC8051_PS_NOT;
1989
          cy_sel = `OC8051_CY_1;
1990
          pc_wr = `OC8051_PCW_N;
1991
          pc_sel = `OC8051_PIS_DC;
1992
          imm_sel = `OC8051_IDS_DC;
1993
          src_sel3 = `OC8051_AS3_DC;
1994
          comp_sel = `OC8051_CSS_DC;
1995
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1996
          wad2 = `OC8051_WAD_N;
1997
          rom_addr_sel = `OC8051_RAS_PC;
1998
 
1999
        end
2000
      `OC8051_DEC_D : begin
2001
          ram_rd_sel = `OC8051_RRS_D;
2002
          ram_wr_sel = `OC8051_RWS_D;
2003
          src_sel1 = `OC8051_ASS_RAM;
2004
          src_sel2 = `OC8051_ASS_ZERO;
2005
          alu_op = `OC8051_ALU_SUB;
2006
          wr = 1'b1;
2007
          psw_set = `OC8051_PS_NOT;
2008
          cy_sel = `OC8051_CY_1;
2009
          pc_wr = `OC8051_PCW_N;
2010
          pc_sel = `OC8051_PIS_DC;
2011
          imm_sel = `OC8051_IDS_DC;
2012
          src_sel3 = `OC8051_AS3_DC;
2013
          comp_sel = `OC8051_CSS_DC;
2014
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2015
          wad2 = `OC8051_WAD_N;
2016
          rom_addr_sel = `OC8051_RAS_PC;
2017
 
2018
        end
2019
      `OC8051_DIV : begin
2020
          ram_rd_sel = `OC8051_RRS_D;
2021
          ram_wr_sel = `OC8051_RWS_B;
2022
          src_sel1 = `OC8051_ASS_ACC;
2023
          src_sel2 = `OC8051_ASS_RAM;
2024
          alu_op = `OC8051_ALU_DIV;
2025
          wr = 1'b0;
2026
          psw_set = `OC8051_PS_OV;
2027
          cy_sel = `OC8051_CY_0;
2028
          pc_wr = `OC8051_PCW_N;
2029
          pc_sel = `OC8051_PIS_DC;
2030
          imm_sel = `OC8051_IDS_DC;
2031
          src_sel3 = `OC8051_AS3_DC;
2032
          comp_sel = `OC8051_CSS_DC;
2033
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2034
          wad2 = `OC8051_WAD_N;
2035
          rom_addr_sel = `OC8051_RAS_PC;
2036
 
2037
        end
2038
      `OC8051_DJNZ_D : begin
2039
          ram_rd_sel = `OC8051_RRS_D;
2040
          ram_wr_sel = `OC8051_RWS_D;
2041
          src_sel1 = `OC8051_ASS_RAM;
2042
          src_sel2 = `OC8051_ASS_ZERO;
2043
          alu_op = `OC8051_ALU_SUB;
2044
          wr = 1'b1;
2045
          psw_set = `OC8051_PS_NOT;
2046
          cy_sel = `OC8051_CY_1;
2047
          pc_wr = `OC8051_PCW_N;
2048
          pc_sel = `OC8051_PIS_DC;
2049
          imm_sel = `OC8051_IDS_DC;
2050
          src_sel3 = `OC8051_AS3_DC;
2051
          comp_sel = `OC8051_CSS_DC;
2052
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2053
          wad2 = `OC8051_WAD_N;
2054
          rom_addr_sel = `OC8051_RAS_PC;
2055
 
2056
        end
2057
      `OC8051_INC_A : begin
2058
          ram_rd_sel = `OC8051_RRS_DC;
2059
          ram_wr_sel = `OC8051_RWS_ACC;
2060
          src_sel1 = `OC8051_ASS_ACC;
2061
          src_sel2 = `OC8051_ASS_ZERO;
2062
          alu_op = `OC8051_ALU_ADD;
2063
          wr = 1'b1;
2064
          psw_set = `OC8051_PS_NOT;
2065
          cy_sel = `OC8051_CY_1;
2066
          pc_wr = `OC8051_PCW_N;
2067
          pc_sel = `OC8051_PIS_DC;
2068
          imm_sel = `OC8051_IDS_DC;
2069
          src_sel3 = `OC8051_AS3_DC;
2070
          comp_sel = `OC8051_CSS_DC;
2071
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2072
          wad2 = `OC8051_WAD_N;
2073
          rom_addr_sel = `OC8051_RAS_PC;
2074
 
2075
        end
2076
      `OC8051_INC_D : begin
2077
          ram_rd_sel = `OC8051_RRS_D;
2078
          ram_wr_sel = `OC8051_RWS_D;
2079
          src_sel1 = `OC8051_ASS_RAM;
2080
          src_sel2 = `OC8051_ASS_ZERO;
2081
          alu_op = `OC8051_ALU_ADD;
2082
          wr = 1'b1;
2083
          psw_set = `OC8051_PS_NOT;
2084
          cy_sel = `OC8051_CY_1;
2085
          pc_wr = `OC8051_PCW_N;
2086
          pc_sel = `OC8051_PIS_DC;
2087
          imm_sel = `OC8051_IDS_DC;
2088
          src_sel3 = `OC8051_AS3_DC;
2089
          comp_sel = `OC8051_CSS_DC;
2090
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2091
          wad2 = `OC8051_WAD_N;
2092
          rom_addr_sel = `OC8051_RAS_PC;
2093
 
2094
        end
2095
      `OC8051_INC_DP : begin
2096
          ram_rd_sel = `OC8051_RRS_D;
2097
          ram_wr_sel = `OC8051_RWS_DPTR;
2098
          src_sel1 = `OC8051_ASS_RAM;
2099
          src_sel2 = `OC8051_ASS_ZERO;
2100
          alu_op = `OC8051_ALU_ADD;
2101
          wr = 1'b1;
2102
          psw_set = `OC8051_PS_NOT;
2103
          cy_sel = `OC8051_CY_1;
2104
          pc_wr = `OC8051_PCW_N;
2105
          pc_sel = `OC8051_PIS_DC;
2106
          imm_sel = `OC8051_IDS_DC;
2107
          src_sel3 = `OC8051_AS3_DP;
2108
          comp_sel = `OC8051_CSS_DC;
2109
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2110
          wad2 = `OC8051_WAD_N;
2111
          rom_addr_sel = `OC8051_RAS_PC;
2112
 
2113
        end
2114
      `OC8051_JB : begin
2115
          ram_rd_sel = `OC8051_RRS_D;
2116
          ram_wr_sel = `OC8051_RWS_DC;
2117
          src_sel1 = `OC8051_ASS_IMM;
2118
          src_sel2 = `OC8051_ASS_IMM;
2119
          alu_op = `OC8051_ALU_PCS;
2120
          wr = 1'b0;
2121
          psw_set = `OC8051_PS_NOT;
2122
          cy_sel = `OC8051_CY_0;
2123
          pc_wr = `OC8051_PCW_N;
2124
          pc_sel = `OC8051_PIS_DC;
2125
          imm_sel = `OC8051_IDS_OP3_PCL;
2126
          src_sel3 = `OC8051_AS3_PC;
2127
          comp_sel = `OC8051_CSS_BIT;
2128
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2129
          wad2 = `OC8051_WAD_N;
2130
          rom_addr_sel = `OC8051_RAS_PC;
2131
 
2132
        end
2133
      `OC8051_JBC :begin
2134
          ram_rd_sel = `OC8051_RRS_D;
2135
          ram_wr_sel = `OC8051_RWS_DC;
2136
          src_sel1 = `OC8051_ASS_IMM;
2137
          src_sel2 = `OC8051_ASS_IMM;
2138
          alu_op = `OC8051_ALU_PCS;
2139
          wr = 1'b0;
2140
          psw_set = `OC8051_PS_NOT;
2141
          cy_sel = `OC8051_CY_0;
2142
          pc_wr = `OC8051_PCW_N;
2143
          pc_sel = `OC8051_PIS_DC;
2144
          imm_sel = `OC8051_IDS_OP3_PCL;
2145
          src_sel3 = `OC8051_AS3_PC;
2146
          comp_sel = `OC8051_CSS_BIT;
2147
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2148
          wad2 = `OC8051_WAD_N;
2149
          rom_addr_sel = `OC8051_RAS_PC;
2150
 
2151
        end
2152
      `OC8051_JC : begin
2153
          ram_rd_sel = `OC8051_RRS_DC;
2154
          ram_wr_sel = `OC8051_RWS_DC;
2155
          src_sel1 = `OC8051_ASS_IMM;
2156
          src_sel2 = `OC8051_ASS_IMM;
2157
          alu_op = `OC8051_ALU_PCS;
2158
          wr = 1'b0;
2159
          psw_set = `OC8051_PS_NOT;
2160
          cy_sel = `OC8051_CY_0;
2161
          pc_wr = `OC8051_PCW_N;
2162
          pc_sel = `OC8051_PIS_DC;
2163
          imm_sel = `OC8051_IDS_OP2_PCL;
2164
          src_sel3 = `OC8051_AS3_PC;
2165
          comp_sel = `OC8051_CSS_CY;
2166
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2167
          wad2 = `OC8051_WAD_N;
2168
          rom_addr_sel = `OC8051_RAS_PC;
2169
 
2170
        end
2171
      `OC8051_JMP : begin
2172
          ram_rd_sel = `OC8051_RRS_D;
2173
          ram_wr_sel = `OC8051_RWS_DC;
2174
          src_sel1 = `OC8051_ASS_ACC;
2175
          src_sel2 = `OC8051_ASS_RAM;
2176
          alu_op = `OC8051_ALU_ADD;
2177
          wr = 1'b0;
2178
          psw_set = `OC8051_PS_NOT;
2179
          cy_sel = `OC8051_CY_0;
2180
          pc_wr = `OC8051_PCW_N;
2181
          pc_sel = `OC8051_PIS_DC;
2182
          imm_sel = `OC8051_IDS_DC;
2183
          src_sel3 = `OC8051_AS3_DP;
2184
          comp_sel = `OC8051_CSS_BIT;
2185
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2186
          wad2 = `OC8051_WAD_N;
2187
          rom_addr_sel = `OC8051_RAS_PC;
2188
 
2189
        end
2190
      `OC8051_JNB : begin
2191
          ram_rd_sel = `OC8051_RRS_D;
2192
          ram_wr_sel = `OC8051_RWS_DC;
2193
          src_sel1 = `OC8051_ASS_IMM;
2194
          src_sel2 = `OC8051_ASS_IMM;
2195
          alu_op = `OC8051_ALU_PCS;
2196
          wr = 1'b0;
2197
          psw_set = `OC8051_PS_NOT;
2198
          cy_sel = `OC8051_CY_0;
2199
          pc_wr = `OC8051_PCW_N;
2200
          pc_sel = `OC8051_PIS_DC;
2201
          imm_sel = `OC8051_IDS_OP3_PCL;
2202
          src_sel3 = `OC8051_AS3_PC;
2203
          comp_sel = `OC8051_CSS_BIT;
2204
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2205
          wad2 = `OC8051_WAD_N;
2206
          rom_addr_sel = `OC8051_RAS_PC;
2207
 
2208
        end
2209
      `OC8051_JNC : begin
2210
          ram_rd_sel = `OC8051_RRS_DC;
2211
          ram_wr_sel = `OC8051_RWS_DC;
2212
          src_sel1 = `OC8051_ASS_IMM;
2213
          src_sel2 = `OC8051_ASS_IMM;
2214
          alu_op = `OC8051_ALU_PCS;
2215
          wr = 1'b0;
2216
          psw_set = `OC8051_PS_NOT;
2217
          cy_sel = `OC8051_CY_0;
2218
          pc_wr = `OC8051_PCW_N;
2219
          pc_sel = `OC8051_PIS_DC;
2220
          imm_sel = `OC8051_IDS_OP2_PCL;
2221
          src_sel3 = `OC8051_AS3_PC;
2222
          comp_sel = `OC8051_CSS_CY;
2223
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2224
          wad2 = `OC8051_WAD_N;
2225
          rom_addr_sel = `OC8051_RAS_PC;
2226
 
2227
        end
2228
      `OC8051_JNZ :begin
2229
          ram_rd_sel = `OC8051_RRS_DC;
2230
          ram_wr_sel = `OC8051_RWS_DC;
2231
          src_sel1 = `OC8051_ASS_IMM;
2232
          src_sel2 = `OC8051_ASS_IMM;
2233
          alu_op = `OC8051_ALU_PCS;
2234
          wr = 1'b0;
2235
          psw_set = `OC8051_PS_NOT;
2236
          cy_sel = `OC8051_CY_0;
2237
          pc_wr = `OC8051_PCW_N;
2238
          pc_sel = `OC8051_PIS_DC;
2239
          imm_sel = `OC8051_IDS_OP2_PCL;
2240
          src_sel3 = `OC8051_AS3_PC;
2241
          comp_sel = `OC8051_CSS_AZ;
2242
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2243
          wad2 = `OC8051_WAD_N;
2244
          rom_addr_sel = `OC8051_RAS_PC;
2245
 
2246
        end
2247
      `OC8051_JZ : begin
2248
          ram_rd_sel = `OC8051_RRS_DC;
2249
          ram_wr_sel = `OC8051_RWS_DC;
2250
          src_sel1 = `OC8051_ASS_IMM;
2251
          src_sel2 = `OC8051_ASS_IMM;
2252
          alu_op = `OC8051_ALU_PCS;
2253
          wr = 1'b0;
2254
          psw_set = `OC8051_PS_NOT;
2255
          cy_sel = `OC8051_CY_0;
2256
          pc_wr = `OC8051_PCW_N;
2257
          pc_sel = `OC8051_PIS_DC;
2258
          imm_sel = `OC8051_IDS_OP2_PCL;
2259
          src_sel3 = `OC8051_AS3_PC;
2260
          comp_sel = `OC8051_CSS_AZ;
2261
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2262
          wad2 = `OC8051_WAD_N;
2263
          rom_addr_sel = `OC8051_RAS_PC;
2264
 
2265
        end
2266
      `OC8051_LCALL :begin
2267
          ram_rd_sel = `OC8051_RRS_DC;
2268
          ram_wr_sel = `OC8051_RWS_SP;
2269
          src_sel1 = `OC8051_ASS_IMM;
2270
          src_sel2 = `OC8051_ASS_DC;
2271
          alu_op = `OC8051_ALU_NOP;
2272
          imm_sel = `OC8051_IDS_PCL;
2273
          wr = 1'b1;
2274
          psw_set = `OC8051_PS_NOT;
2275
          cy_sel = `OC8051_CY_0;
2276
          pc_wr = `OC8051_PCW_Y;
2277
          pc_sel = `OC8051_PIS_I16;
2278
          src_sel3 = `OC8051_AS3_DC;
2279
          comp_sel = `OC8051_CSS_DC;
2280
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2281
          wad2 = `OC8051_WAD_N;
2282
          rom_addr_sel = `OC8051_RAS_PC;
2283
 
2284
        end
2285
      `OC8051_LJMP : begin
2286
          ram_rd_sel = `OC8051_RRS_DC;
2287
          ram_wr_sel = `OC8051_RWS_DC;
2288
          src_sel1 = `OC8051_ASS_DC;
2289
          src_sel2 = `OC8051_ASS_DC;
2290
          alu_op = `OC8051_ALU_NOP;
2291
          imm_sel = `OC8051_IDS_DC;
2292
          wr = 1'b0;
2293
          psw_set = `OC8051_PS_NOT;
2294
          cy_sel = `OC8051_CY_0;
2295
          pc_wr = `OC8051_PCW_Y;
2296
          pc_sel = `OC8051_PIS_I16;
2297
          src_sel3 = `OC8051_AS3_DC;
2298
          comp_sel = `OC8051_CSS_DC;
2299
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2300
          wad2 = `OC8051_WAD_N;
2301
          rom_addr_sel = `OC8051_RAS_PC;
2302
 
2303
        end
2304
      `OC8051_MOV_D : begin
2305
          ram_rd_sel = `OC8051_RRS_D;
2306
          ram_wr_sel = `OC8051_RWS_ACC;
2307
          src_sel1 = `OC8051_ASS_RAM;
2308
          src_sel2 = `OC8051_ASS_DC;
2309
          alu_op = `OC8051_ALU_NOP;
2310
          wr = 1'b1;
2311
          psw_set = `OC8051_PS_NOT;
2312
          cy_sel = `OC8051_CY_0;
2313
          pc_wr = `OC8051_PCW_N;
2314
          pc_sel = `OC8051_PIS_DC;
2315
          imm_sel = `OC8051_IDS_DC;
2316
          src_sel3 = `OC8051_AS3_DC;
2317
          comp_sel = `OC8051_CSS_DC;
2318
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2319
          wad2 = `OC8051_WAD_N;
2320
          rom_addr_sel = `OC8051_RAS_PC;
2321
 
2322
        end
2323
      `OC8051_MOV_C : begin
2324
          ram_rd_sel = `OC8051_RRS_DC;
2325
          ram_wr_sel = `OC8051_RWS_ACC;
2326
          src_sel1 = `OC8051_ASS_IMM;
2327
          src_sel2 = `OC8051_ASS_DC;
2328
          alu_op = `OC8051_ALU_NOP;
2329
          wr = 1'b1;
2330
          psw_set = `OC8051_PS_NOT;
2331
          cy_sel = `OC8051_CY_0;
2332
          pc_wr = `OC8051_PCW_N;
2333
          pc_sel = `OC8051_PIS_DC;
2334
          imm_sel = `OC8051_IDS_OP2;
2335
          src_sel3 = `OC8051_AS3_DC;
2336
          comp_sel = `OC8051_CSS_DC;
2337
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2338
          wad2 = `OC8051_WAD_N;
2339
          rom_addr_sel = `OC8051_RAS_PC;
2340
 
2341
        end
2342
 
2343
      `OC8051_MOV_DA : begin
2344
          ram_rd_sel = `OC8051_RRS_DC;
2345
          ram_wr_sel = `OC8051_RWS_D;
2346
          src_sel1 = `OC8051_ASS_ACC;
2347
          src_sel2 = `OC8051_ASS_DC;
2348
          alu_op = `OC8051_ALU_NOP;
2349
          wr = 1'b1;
2350
          psw_set = `OC8051_PS_NOT;
2351
          cy_sel = `OC8051_CY_0;
2352
          pc_wr = `OC8051_PCW_N;
2353
          pc_sel = `OC8051_PIS_DC;
2354
          imm_sel = `OC8051_IDS_DC;
2355
          src_sel3 = `OC8051_AS3_DC;
2356
          comp_sel = `OC8051_CSS_DC;
2357
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2358
          wad2 = `OC8051_WAD_N;
2359
          rom_addr_sel = `OC8051_RAS_PC;
2360
 
2361
        end
2362
      `OC8051_MOV_DD : begin
2363
          ram_rd_sel = `OC8051_RRS_D;
2364
          ram_wr_sel = `OC8051_RWS_D3;
2365
          src_sel1 = `OC8051_ASS_RAM;
2366
          src_sel2 = `OC8051_ASS_DC;
2367
          alu_op = `OC8051_ALU_NOP;
2368
          wr = 1'b1;
2369
          psw_set = `OC8051_PS_NOT;
2370
          cy_sel = `OC8051_CY_0;
2371
          pc_wr = `OC8051_PCW_N;
2372
          pc_sel = `OC8051_PIS_DC;
2373
          imm_sel = `OC8051_IDS_OP2;
2374
          src_sel3 = `OC8051_AS3_DC;
2375
          comp_sel = `OC8051_CSS_DC;
2376
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2377
          wad2 = `OC8051_WAD_N;
2378
          rom_addr_sel = `OC8051_RAS_PC;
2379
 
2380
        end
2381
      `OC8051_MOV_CD : begin
2382
          ram_rd_sel = `OC8051_RRS_DC;
2383
          ram_wr_sel = `OC8051_RWS_D;
2384
          src_sel1 = `OC8051_ASS_IMM;
2385
          src_sel2 = `OC8051_ASS_DC;
2386
          alu_op = `OC8051_ALU_NOP;
2387
          wr = 1'b1;
2388
          psw_set = `OC8051_PS_NOT;
2389
          cy_sel = `OC8051_CY_0;
2390
          pc_wr = `OC8051_PCW_N;
2391
          pc_sel = `OC8051_PIS_DC;
2392
          imm_sel = `OC8051_IDS_OP3;
2393
          src_sel3 = `OC8051_AS3_DC;
2394
          comp_sel = `OC8051_CSS_DC;
2395
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2396
          wad2 = `OC8051_WAD_N;
2397
          rom_addr_sel = `OC8051_RAS_PC;
2398
 
2399
        end
2400
      `OC8051_MOV_BC : begin
2401
          ram_rd_sel = `OC8051_RRS_D;
2402
          ram_wr_sel = `OC8051_RWS_DC;
2403
          src_sel1 = `OC8051_ASS_DC;
2404
          src_sel2 = `OC8051_ASS_DC;
2405
          alu_op = `OC8051_ALU_NOP;
2406
          wr = 1'b0;
2407
          psw_set = `OC8051_PS_CY;
2408
          cy_sel = `OC8051_CY_RAM;
2409
          pc_wr = `OC8051_PCW_N;
2410
          pc_sel = `OC8051_PIS_DC;
2411
          imm_sel = `OC8051_IDS_DC;
2412
          src_sel3 = `OC8051_AS3_DC;
2413
          comp_sel = `OC8051_CSS_DC;
2414
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2415
          wad2 = `OC8051_WAD_N;
2416
          rom_addr_sel = `OC8051_RAS_PC;
2417
 
2418
        end
2419
      `OC8051_MOV_CB : begin
2420
          ram_rd_sel = `OC8051_RRS_D;
2421
          ram_wr_sel = `OC8051_RWS_D;
2422
          src_sel1 = `OC8051_ASS_DC;
2423
          src_sel2 = `OC8051_ASS_DC;
2424
          alu_op = `OC8051_ALU_NOP;
2425
          wr = 1'b1;
2426
          psw_set = `OC8051_PS_NOT;
2427
          cy_sel = `OC8051_CY_PSW;
2428
          pc_wr = `OC8051_PCW_N;
2429
          pc_sel = `OC8051_PIS_DC;
2430
          imm_sel = `OC8051_IDS_OP3;
2431
          src_sel3 = `OC8051_AS3_DC;
2432
          comp_sel = `OC8051_CSS_DC;
2433
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2434
          wad2 = `OC8051_WAD_N;
2435
          rom_addr_sel = `OC8051_RAS_PC;
2436
 
2437
        end
2438
      `OC8051_MOV_DP : begin  ///***
2439
          ram_rd_sel = `OC8051_RRS_DC;
2440
          ram_wr_sel = `OC8051_RWS_DPTR;
2441
          src_sel1 = `OC8051_ASS_IMM;
2442
          src_sel2 = `OC8051_ASS_IMM;
2443
          alu_op = `OC8051_ALU_NOP;
2444
          wr = 1'b1;
2445
          psw_set = `OC8051_PS_NOT;
2446
          cy_sel = `OC8051_CY_0;
2447
          pc_wr = `OC8051_PCW_N;
2448
          pc_sel = `OC8051_PIS_DC;
2449
          imm_sel = `OC8051_IDS_OP3_OP2;
2450
          src_sel3 = `OC8051_AS3_DC;
2451
          comp_sel = `OC8051_CSS_DC;
2452
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2453
          wad2 = `OC8051_WAD_N;
2454
          rom_addr_sel = `OC8051_RAS_PC;
2455
 
2456
        end
2457
      `OC8051_MOVC_DP :begin
2458
          ram_rd_sel = `OC8051_RRS_D;
2459
          ram_wr_sel = `OC8051_RWS_DC;
2460
          src_sel1 = `OC8051_ASS_ACC;
2461
          src_sel2 = `OC8051_ASS_RAM;
2462
          alu_op = `OC8051_ALU_ADD;
2463
          wr = 1'b0;
2464
          psw_set = `OC8051_PS_NOT;
2465
          cy_sel = `OC8051_CY_0;
2466
          pc_wr = `OC8051_PCW_N;
2467
          pc_sel = `OC8051_PIS_DC;
2468
          imm_sel = `OC8051_IDS_DC;
2469
          src_sel3 = `OC8051_AS3_DP;
2470
          comp_sel = `OC8051_CSS_DC;
2471
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2472
          wad2 = `OC8051_WAD_N;
2473
          rom_addr_sel = `OC8051_RAS_PC;
2474
 
2475
        end
2476
      `OC8051_MOVC_PC : begin
2477
          ram_rd_sel = `OC8051_RRS_DC;
2478
          ram_wr_sel = `OC8051_RWS_DC;
2479
          src_sel1 = `OC8051_ASS_IMM;
2480
          src_sel2 = `OC8051_ASS_ACC;
2481
          alu_op = `OC8051_ALU_ADD;
2482
          wr = 1'b0;
2483
          psw_set = `OC8051_PS_NOT;
2484
          cy_sel = `OC8051_CY_0;
2485
          pc_wr = `OC8051_PCW_N;
2486
          pc_sel = `OC8051_PIS_DC;
2487
          imm_sel = `OC8051_IDS_PCL;
2488
          src_sel3 = `OC8051_AS3_PC;
2489
          comp_sel = `OC8051_CSS_DC;
2490
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2491
          wad2 = `OC8051_WAD_N;
2492
          rom_addr_sel = `OC8051_RAS_PC;
2493
 
2494
        end
2495
      `OC8051_MOVX_PA : begin
2496
          ram_rd_sel = `OC8051_RRS_DC;
2497
          ram_wr_sel = `OC8051_RWS_ACC;
2498
          src_sel1 = `OC8051_ASS_XRAM;
2499
          src_sel2 = `OC8051_ASS_DC;
2500
          alu_op = `OC8051_ALU_NOP;
2501
          wr = 1'b0;
2502
          psw_set = `OC8051_PS_NOT;
2503
          cy_sel = `OC8051_CY_0;
2504
          pc_wr = `OC8051_PCW_N;
2505
          pc_sel = `OC8051_PIS_DC;
2506
          imm_sel = `OC8051_IDS_OP2;
2507
          src_sel3 = `OC8051_AS3_DC;
2508
          comp_sel = `OC8051_CSS_DC;
2509
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2510
          wad2 = `OC8051_WAD_N;
2511
          rom_addr_sel = `OC8051_RAS_PC;
2512
        end
2513
      `OC8051_MOVX_AP : begin
2514
          ram_rd_sel = `OC8051_RRS_DC;
2515
          ram_wr_sel = `OC8051_RWS_DC;
2516
          src_sel1 = `OC8051_ASS_XRAM;
2517
          src_sel2 = `OC8051_ASS_DC;
2518
          alu_op = `OC8051_ALU_NOP;
2519
          wr = 1'b0;
2520
          psw_set = `OC8051_PS_NOT;
2521
          cy_sel = `OC8051_CY_0;
2522
          pc_wr = `OC8051_PCW_N;
2523
          pc_sel = `OC8051_PIS_DC;
2524
          imm_sel = `OC8051_IDS_DC;
2525
          src_sel3 = `OC8051_AS3_DC;
2526
          comp_sel = `OC8051_CSS_DC;
2527
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2528
          wad2 = `OC8051_WAD_N;
2529
          rom_addr_sel = `OC8051_RAS_PC;
2530
        end
2531
      `OC8051_MUL : begin
2532
          ram_rd_sel = `OC8051_RRS_D;
2533
          ram_wr_sel = `OC8051_RWS_B;
2534
          src_sel1 = `OC8051_ASS_ACC;
2535
          src_sel2 = `OC8051_ASS_RAM;
2536
          alu_op = `OC8051_ALU_MUL;
2537
          wr = 1'b0;
2538
          psw_set = `OC8051_PS_OV;
2539
          cy_sel = `OC8051_CY_0;
2540
          pc_wr = `OC8051_PCW_N;
2541
          pc_sel = `OC8051_PIS_DC;
2542
          imm_sel = `OC8051_IDS_DC;
2543
          src_sel3 = `OC8051_AS3_DC;
2544
          comp_sel = `OC8051_CSS_DC;
2545
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2546
          wad2 = `OC8051_WAD_N;
2547
          rom_addr_sel = `OC8051_RAS_PC;
2548
 
2549
        end
2550
      `OC8051_ORL_D : begin
2551
          ram_rd_sel = `OC8051_RRS_D;
2552
          ram_wr_sel = `OC8051_RWS_ACC;
2553
          src_sel1 = `OC8051_ASS_RAM;
2554
          src_sel2 = `OC8051_ASS_ACC;
2555
          alu_op = `OC8051_ALU_OR;
2556
          wr = 1'b1;
2557
          psw_set = `OC8051_PS_NOT;
2558
          cy_sel = `OC8051_CY_0;
2559
          pc_wr = `OC8051_PCW_N;
2560
          pc_sel = `OC8051_PIS_DC;
2561
          imm_sel = `OC8051_IDS_DC;
2562
          src_sel3 = `OC8051_AS3_DC;
2563
          comp_sel = `OC8051_CSS_DC;
2564
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2565
          wad2 = `OC8051_WAD_N;
2566
          rom_addr_sel = `OC8051_RAS_PC;
2567
 
2568
        end
2569
      `OC8051_ORL_C : begin
2570
          ram_rd_sel = `OC8051_RRS_DC;
2571
          ram_wr_sel = `OC8051_RWS_ACC;
2572
          src_sel1 = `OC8051_ASS_IMM;
2573
          src_sel2 = `OC8051_ASS_ACC;
2574
          alu_op = `OC8051_ALU_OR;
2575
          wr = 1'b1;
2576
          psw_set = `OC8051_PS_NOT;
2577
          cy_sel = `OC8051_CY_0;
2578
          pc_wr = `OC8051_PCW_N;
2579
          pc_sel = `OC8051_PIS_DC;
2580
          imm_sel = `OC8051_IDS_OP2;
2581
          src_sel3 = `OC8051_AS3_DC;
2582
          comp_sel = `OC8051_CSS_DC;
2583
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2584
          wad2 = `OC8051_WAD_N;
2585
          rom_addr_sel = `OC8051_RAS_PC;
2586
 
2587
        end
2588
      `OC8051_ORL_AD : begin
2589
          ram_rd_sel = `OC8051_RRS_D;
2590
          ram_wr_sel = `OC8051_RWS_D;
2591
          src_sel1 = `OC8051_ASS_RAM;
2592
          src_sel2 = `OC8051_ASS_ACC;
2593
          alu_op = `OC8051_ALU_OR;
2594
          wr = 1'b1;
2595
          psw_set = `OC8051_PS_NOT;
2596
          cy_sel = `OC8051_CY_0;
2597
          pc_wr = `OC8051_PCW_N;
2598
          pc_sel = `OC8051_PIS_DC;
2599
          imm_sel = `OC8051_IDS_DC;
2600
          src_sel3 = `OC8051_AS3_DC;
2601
          comp_sel = `OC8051_CSS_DC;
2602
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2603
          wad2 = `OC8051_WAD_N;
2604
          rom_addr_sel = `OC8051_RAS_PC;
2605
 
2606
        end
2607
      `OC8051_ORL_CD : begin
2608
          ram_rd_sel = `OC8051_RRS_D;
2609
          ram_wr_sel = `OC8051_RWS_D;
2610
          src_sel1 = `OC8051_ASS_IMM;
2611
          src_sel2 = `OC8051_ASS_RAM;
2612
          alu_op = `OC8051_ALU_OR;
2613
          wr = 1'b1;
2614
          psw_set = `OC8051_PS_NOT;
2615
          cy_sel = `OC8051_CY_0;
2616
          pc_wr = `OC8051_PCW_N;
2617
          pc_sel = `OC8051_PIS_DC;
2618
          imm_sel = `OC8051_IDS_OP3;
2619
          src_sel3 = `OC8051_AS3_DC;
2620
          comp_sel = `OC8051_CSS_DC;
2621
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2622
          wad2 = `OC8051_WAD_N;
2623
          rom_addr_sel = `OC8051_RAS_PC;
2624
 
2625
        end
2626
      `OC8051_ORL_B : begin
2627
          ram_rd_sel = `OC8051_RRS_D;
2628
          ram_wr_sel = `OC8051_RWS_DC;
2629
          src_sel1 = `OC8051_ASS_DC;
2630
          src_sel2 = `OC8051_ASS_DC;
2631
          alu_op = `OC8051_ALU_OR;
2632
          wr = 1'b0;
2633
          psw_set = `OC8051_PS_CY;
2634
          cy_sel = `OC8051_CY_PSW;
2635
          pc_wr = `OC8051_PCW_N;
2636
          pc_sel = `OC8051_PIS_DC;
2637
          imm_sel = `OC8051_IDS_DC;
2638
          src_sel3 = `OC8051_AS3_DC;
2639
          comp_sel = `OC8051_CSS_DC;
2640
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2641
          wad2 = `OC8051_WAD_N;
2642
          rom_addr_sel = `OC8051_RAS_PC;
2643
 
2644
        end
2645
      `OC8051_ORL_NB : begin
2646
          ram_rd_sel = `OC8051_RRS_D;
2647
          ram_wr_sel = `OC8051_RWS_DC;
2648
          src_sel1 = `OC8051_ASS_DC;
2649
          src_sel2 = `OC8051_ASS_DC;
2650
          alu_op = `OC8051_ALU_RL;
2651
          wr = 1'b0;
2652
          psw_set = `OC8051_PS_CY;
2653
          cy_sel = `OC8051_CY_PSW;
2654
          pc_wr = `OC8051_PCW_N;
2655
          pc_sel = `OC8051_PIS_DC;
2656
          imm_sel = `OC8051_IDS_DC;
2657
          src_sel3 = `OC8051_AS3_DC;
2658
          comp_sel = `OC8051_CSS_DC;
2659
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2660
          wad2 = `OC8051_WAD_N;
2661
          rom_addr_sel = `OC8051_RAS_PC;
2662
 
2663
        end
2664
      `OC8051_POP : begin
2665
          ram_rd_sel = `OC8051_RRS_SP;
2666
          ram_wr_sel = `OC8051_RWS_D;
2667
          src_sel1 = `OC8051_ASS_RAM;
2668
          src_sel2 = `OC8051_ASS_DC;
2669
          alu_op = `OC8051_ALU_NOP;
2670
          wr = 1'b1;
2671
          psw_set = `OC8051_PS_NOT;
2672
          cy_sel = `OC8051_CY_0;
2673
          pc_wr = `OC8051_PCW_N;
2674
          pc_sel = `OC8051_PIS_DC;
2675
          imm_sel = `OC8051_IDS_DC;
2676
          src_sel3 = `OC8051_AS3_DC;
2677
          comp_sel = `OC8051_CSS_DC;
2678
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2679
          wad2 = `OC8051_WAD_N;
2680
          rom_addr_sel = `OC8051_RAS_PC;
2681
 
2682
        end
2683
      `OC8051_PUSH : begin
2684
          ram_rd_sel = `OC8051_RRS_D;
2685
          ram_wr_sel = `OC8051_RWS_SP;
2686
          src_sel1 = `OC8051_ASS_RAM;
2687
          src_sel2 = `OC8051_ASS_DC;
2688
          alu_op = `OC8051_ALU_NOP;
2689
          wr = 1'b1;
2690
          psw_set = `OC8051_PS_NOT;
2691
          cy_sel = `OC8051_CY_0;
2692
          pc_wr = `OC8051_PCW_N;
2693
          pc_sel = `OC8051_PIS_DC;
2694
          imm_sel = `OC8051_IDS_DC;
2695
          src_sel3 = `OC8051_AS3_DC;
2696
          comp_sel = `OC8051_CSS_DC;
2697
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2698
          wad2 = `OC8051_WAD_N;
2699
          rom_addr_sel = `OC8051_RAS_PC;
2700
 
2701
        end
2702
      `OC8051_RET : begin
2703
          ram_rd_sel = `OC8051_RRS_SP;
2704
          ram_wr_sel = `OC8051_RWS_DC;
2705
          src_sel1 = `OC8051_ASS_RAM;
2706
          src_sel2 = `OC8051_ASS_DC;
2707
          alu_op = `OC8051_ALU_NOP;
2708
          wr = 1'b0;
2709
          psw_set = `OC8051_PS_NOT;
2710
          cy_sel = `OC8051_CY_0;
2711
          pc_wr = `OC8051_PCW_N;
2712
          pc_sel = `OC8051_PIS_DC;
2713
          imm_sel = `OC8051_IDS_DC;
2714
          src_sel3 = `OC8051_AS3_DC;
2715
          comp_sel = `OC8051_CSS_DC;
2716
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2717
          wad2 = `OC8051_WAD_N;
2718
          rom_addr_sel = `OC8051_RAS_PC;
2719
 
2720
        end
2721
      `OC8051_RETI : begin
2722
          ram_rd_sel = `OC8051_RRS_SP;
2723
          ram_wr_sel = `OC8051_RWS_DC;
2724
          src_sel1 = `OC8051_ASS_RAM;
2725
          src_sel2 = `OC8051_ASS_DC;
2726
          alu_op = `OC8051_ALU_NOP;
2727
          wr = 1'b0;
2728
          psw_set = `OC8051_PS_NOT;
2729
          cy_sel = `OC8051_CY_0;
2730
          pc_wr = `OC8051_PCW_N;
2731
          pc_sel = `OC8051_PIS_DC;
2732
          imm_sel = `OC8051_IDS_DC;
2733
          src_sel3 = `OC8051_AS3_DC;
2734
          comp_sel = `OC8051_CSS_DC;
2735
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2736
          wad2 = `OC8051_WAD_N;
2737
          rom_addr_sel = `OC8051_RAS_PC;
2738
 
2739
        end
2740
      `OC8051_RL : begin
2741
          ram_rd_sel = `OC8051_RRS_DC;
2742
          ram_wr_sel = `OC8051_RWS_ACC;
2743
          src_sel1 = `OC8051_ASS_ACC;
2744
          src_sel2 = `OC8051_ASS_DC;
2745
          alu_op = `OC8051_ALU_RL;
2746
          wr = 1'b1;
2747
          psw_set = `OC8051_PS_NOT;
2748
          cy_sel = `OC8051_CY_0;
2749
          pc_wr = `OC8051_PCW_N;
2750
          pc_sel = `OC8051_PIS_DC;
2751
          imm_sel = `OC8051_IDS_DC;
2752
          src_sel3 = `OC8051_AS3_DC;
2753
          comp_sel = `OC8051_CSS_DC;
2754
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2755
          wad2 = `OC8051_WAD_N;
2756
          rom_addr_sel = `OC8051_RAS_PC;
2757
 
2758
        end
2759
      `OC8051_RLC : begin
2760
          ram_rd_sel = `OC8051_RRS_DC;
2761
          ram_wr_sel = `OC8051_RWS_ACC;
2762
          src_sel1 = `OC8051_ASS_ACC;
2763
          src_sel2 = `OC8051_ASS_DC;
2764
          alu_op = `OC8051_ALU_RLC;
2765
          wr = 1'b1;
2766
          psw_set = `OC8051_PS_CY;
2767
          cy_sel = `OC8051_CY_PSW;
2768
          pc_wr = `OC8051_PCW_N;
2769
          pc_sel = `OC8051_PIS_DC;
2770
          imm_sel = `OC8051_IDS_DC;
2771
          src_sel3 = `OC8051_AS3_DC;
2772
          comp_sel = `OC8051_CSS_DC;
2773
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2774
          wad2 = `OC8051_WAD_N;
2775
          rom_addr_sel = `OC8051_RAS_PC;
2776
 
2777
        end
2778
      `OC8051_RR : begin
2779
          ram_rd_sel = `OC8051_RRS_DC;
2780
          ram_wr_sel = `OC8051_RWS_ACC;
2781
          src_sel1 = `OC8051_ASS_ACC;
2782
          src_sel2 = `OC8051_ASS_DC;
2783
          alu_op = `OC8051_ALU_RR;
2784
          wr = 1'b1;
2785
          psw_set = `OC8051_PS_NOT;
2786
          cy_sel = `OC8051_CY_0;
2787
          pc_wr = `OC8051_PCW_N;
2788
          pc_sel = `OC8051_PIS_DC;
2789
          imm_sel = `OC8051_IDS_DC;
2790
          src_sel3 = `OC8051_AS3_DC;
2791
          comp_sel = `OC8051_CSS_DC;
2792
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2793
          wad2 = `OC8051_WAD_N;
2794
          rom_addr_sel = `OC8051_RAS_PC;
2795
 
2796
        end
2797
      `OC8051_RRC : begin
2798
          ram_rd_sel = `OC8051_RRS_DC;
2799
          ram_wr_sel = `OC8051_RWS_ACC;
2800
          src_sel1 = `OC8051_ASS_ACC;
2801
          src_sel2 = `OC8051_ASS_DC;
2802
          alu_op = `OC8051_ALU_RRC;
2803
          wr = 1'b1;
2804
          psw_set = `OC8051_PS_CY;
2805
          cy_sel = `OC8051_CY_PSW;
2806
          pc_wr = `OC8051_PCW_N;
2807
          pc_sel = `OC8051_PIS_DC;
2808
          imm_sel = `OC8051_IDS_DC;
2809
          src_sel3 = `OC8051_AS3_DC;
2810
          comp_sel = `OC8051_CSS_DC;
2811
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2812
          wad2 = `OC8051_WAD_N;
2813
          rom_addr_sel = `OC8051_RAS_PC;
2814
 
2815
        end
2816
      `OC8051_SETB_C : begin
2817
          ram_rd_sel = `OC8051_RRS_DC;
2818
          ram_wr_sel = `OC8051_RWS_DC;
2819
          src_sel1 = `OC8051_ASS_DC;
2820
          src_sel2 = `OC8051_ASS_DC;
2821
          alu_op = `OC8051_ALU_NOP;
2822
          wr = 1'b0;
2823
          psw_set = `OC8051_PS_CY;
2824
          cy_sel = `OC8051_CY_1;
2825
          pc_wr = `OC8051_PCW_N;
2826
          pc_sel = `OC8051_PIS_DC;
2827
          imm_sel = `OC8051_IDS_DC;
2828
          src_sel3 = `OC8051_AS3_PC;
2829
          comp_sel = `OC8051_CSS_DC;
2830
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2831
          wad2 = `OC8051_WAD_N;
2832
          rom_addr_sel = `OC8051_RAS_PC;
2833
 
2834
        end
2835
      `OC8051_SETB_B : begin
2836
          ram_rd_sel = `OC8051_RRS_D;
2837
          ram_wr_sel = `OC8051_RWS_D;
2838
          src_sel1 = `OC8051_ASS_DC;
2839
          src_sel2 = `OC8051_ASS_DC;
2840
          alu_op = `OC8051_ALU_NOP;
2841
          wr = 1'b1;
2842
          psw_set = `OC8051_PS_NOT;
2843
          cy_sel = `OC8051_CY_1;
2844
          pc_wr = `OC8051_PCW_N;
2845
          pc_sel = `OC8051_PIS_DC;
2846
          imm_sel = `OC8051_IDS_DC;
2847
          src_sel3 = `OC8051_AS3_PC;
2848
          comp_sel = `OC8051_CSS_DC;
2849
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2850
          wad2 = `OC8051_WAD_N;
2851
          rom_addr_sel = `OC8051_RAS_PC;
2852
 
2853
        end
2854
      `OC8051_SJMP : begin
2855
          ram_rd_sel = `OC8051_RRS_DC;
2856
          ram_wr_sel = `OC8051_RWS_DC;
2857
          src_sel1 = `OC8051_ASS_IMM;
2858
          src_sel2 = `OC8051_ASS_IMM;
2859
          alu_op = `OC8051_ALU_PCS;
2860
          wr = 1'b0;
2861
          psw_set = `OC8051_PS_NOT;
2862
          cy_sel = `OC8051_CY_0;
2863
          pc_wr = `OC8051_PCW_N;
2864
          pc_sel = `OC8051_PIS_DC;
2865
          imm_sel = `OC8051_IDS_OP2_PCL;
2866
          src_sel3 = `OC8051_AS3_PC;
2867
          comp_sel = `OC8051_CSS_DC;
2868
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2869
          wad2 = `OC8051_WAD_N;
2870
          rom_addr_sel = `OC8051_RAS_PC;
2871
 
2872
        end
2873
      `OC8051_SUBB_D : begin
2874
          ram_rd_sel = `OC8051_RRS_D;
2875
          ram_wr_sel = `OC8051_RWS_ACC;
2876
          src_sel1 = `OC8051_ASS_ACC;
2877
          src_sel2 = `OC8051_ASS_RAM;
2878
          alu_op = `OC8051_ALU_SUB;
2879
          wr = 1'b1;
2880
          psw_set = `OC8051_PS_AC;
2881
          cy_sel = `OC8051_CY_PSW;
2882
          pc_wr = `OC8051_PCW_N;
2883
          pc_sel = `OC8051_PIS_DC;
2884
          imm_sel = `OC8051_IDS_DC;
2885
          src_sel3 = `OC8051_AS3_DC;
2886
          comp_sel = `OC8051_CSS_DC;
2887
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2888
          wad2 = `OC8051_WAD_N;
2889
          rom_addr_sel = `OC8051_RAS_PC;
2890
 
2891
        end
2892
      `OC8051_SUBB_C : begin
2893
          ram_rd_sel = `OC8051_RRS_DC;
2894
          ram_wr_sel = `OC8051_RWS_ACC;
2895
          src_sel1 = `OC8051_ASS_ACC;
2896
          src_sel2 = `OC8051_ASS_IMM;
2897
          alu_op = `OC8051_ALU_SUB;
2898
          wr = 1'b1;
2899
          psw_set = `OC8051_PS_AC;
2900
          cy_sel = `OC8051_CY_PSW;
2901
          pc_wr = `OC8051_PCW_N;
2902
          pc_sel = `OC8051_PIS_DC;
2903
          imm_sel = `OC8051_IDS_OP2;
2904
          src_sel3 = `OC8051_AS3_DC;
2905
          comp_sel = `OC8051_CSS_DC;
2906
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2907
          wad2 = `OC8051_WAD_N;
2908
          rom_addr_sel = `OC8051_RAS_PC;
2909
 
2910
        end
2911
      `OC8051_SWAP : begin
2912
          ram_rd_sel = `OC8051_RRS_DC;
2913
          ram_wr_sel = `OC8051_RWS_DC;
2914
          src_sel1 = `OC8051_ASS_ACC;
2915
          src_sel2 = `OC8051_ASS_DC;
2916
          alu_op = `OC8051_ALU_RLC;
2917
          wr = 1'b0;
2918
          psw_set = `OC8051_PS_NOT;
2919
          cy_sel = `OC8051_CY_0;
2920
          pc_wr = `OC8051_PCW_N;
2921
          pc_sel = `OC8051_PIS_DC;
2922
          imm_sel = `OC8051_IDS_DC;
2923
          src_sel3 = `OC8051_AS3_DC;
2924
          comp_sel = `OC8051_CSS_DC;
2925
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2926
          wad2 = `OC8051_WAD_Y;
2927
          rom_addr_sel = `OC8051_RAS_PC;
2928
 
2929
        end
2930
      `OC8051_XCH_D : begin
2931
          ram_rd_sel = `OC8051_RRS_D;
2932
          ram_wr_sel = `OC8051_RWS_D;
2933
          src_sel1 = `OC8051_ASS_RAM;
2934
          src_sel2 = `OC8051_ASS_ACC;
2935
          alu_op = `OC8051_ALU_XCH;
2936
          wr = 1'b1;
2937
          psw_set = `OC8051_PS_NOT;
2938
          cy_sel = `OC8051_CY_1;
2939
          pc_wr = `OC8051_PCW_N;
2940
          pc_sel = `OC8051_PIS_DC;
2941
          imm_sel = `OC8051_IDS_DC;
2942
          src_sel3 = `OC8051_AS3_DC;
2943
          comp_sel = `OC8051_CSS_DC;
2944
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2945
          wad2 = `OC8051_WAD_Y;
2946
          rom_addr_sel = `OC8051_RAS_PC;
2947
 
2948
        end
2949
      `OC8051_XRL_D : begin
2950
          ram_rd_sel = `OC8051_RRS_D;
2951
          ram_wr_sel = `OC8051_RWS_ACC;
2952
          src_sel1 = `OC8051_ASS_RAM;
2953
          src_sel2 = `OC8051_ASS_ACC;
2954
          alu_op = `OC8051_ALU_XOR;
2955
          wr = 1'b1;
2956
          psw_set = `OC8051_PS_NOT;
2957
          cy_sel = `OC8051_CY_0;
2958
          pc_wr = `OC8051_PCW_N;
2959
          pc_sel = `OC8051_PIS_DC;
2960
          imm_sel = `OC8051_IDS_DC;
2961
          src_sel3 = `OC8051_AS3_DC;
2962
          comp_sel = `OC8051_CSS_DC;
2963
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2964
          wad2 = `OC8051_WAD_N;
2965
          rom_addr_sel = `OC8051_RAS_PC;
2966
 
2967
        end
2968
      `OC8051_XRL_C : begin
2969
          ram_rd_sel = `OC8051_RRS_DC;
2970
          ram_wr_sel = `OC8051_RWS_ACC;
2971
          src_sel1 = `OC8051_ASS_IMM;
2972
          src_sel2 = `OC8051_ASS_ACC;
2973
          alu_op = `OC8051_ALU_XOR;
2974
          wr = 1'b1;
2975
          psw_set = `OC8051_PS_NOT;
2976
          cy_sel = `OC8051_CY_0;
2977
          pc_wr = `OC8051_PCW_N;
2978
          pc_sel = `OC8051_PIS_DC;
2979
          imm_sel = `OC8051_IDS_OP2;
2980
          src_sel3 = `OC8051_AS3_DC;
2981
          comp_sel = `OC8051_CSS_DC;
2982
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2983
          wad2 = `OC8051_WAD_N;
2984
          rom_addr_sel = `OC8051_RAS_PC;
2985
 
2986
        end
2987
      `OC8051_XRL_AD : begin
2988
          ram_rd_sel = `OC8051_RRS_D;
2989
          ram_wr_sel = `OC8051_RWS_D;
2990
          src_sel1 = `OC8051_ASS_RAM;
2991
          src_sel2 = `OC8051_ASS_ACC;
2992
          alu_op = `OC8051_ALU_XOR;
2993
          wr = 1'b1;
2994
          psw_set = `OC8051_PS_NOT;
2995
          cy_sel = `OC8051_CY_0;
2996
          pc_wr = `OC8051_PCW_N;
2997
          pc_sel = `OC8051_PIS_DC;
2998
          imm_sel = `OC8051_IDS_DC;
2999
          src_sel3 = `OC8051_AS3_DC;
3000
          comp_sel = `OC8051_CSS_DC;
3001
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
3002
          wad2 = `OC8051_WAD_N;
3003
          rom_addr_sel = `OC8051_RAS_PC;
3004
 
3005
        end
3006
      `OC8051_XRL_CD : begin
3007
          ram_rd_sel = `OC8051_RRS_D;
3008
          ram_wr_sel = `OC8051_RWS_D;
3009
          src_sel1 = `OC8051_ASS_IMM;
3010
          src_sel2 = `OC8051_ASS_RAM;
3011
          alu_op = `OC8051_ALU_XOR;
3012
          wr = 1'b1;
3013
          psw_set = `OC8051_PS_NOT;
3014
          cy_sel = `OC8051_CY_0;
3015
          pc_wr = `OC8051_PCW_N;
3016
          pc_sel = `OC8051_PIS_DC;
3017
          imm_sel = `OC8051_IDS_OP3;
3018
          src_sel3 = `OC8051_AS3_DC;
3019
          comp_sel = `OC8051_CSS_DC;
3020
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
3021
          wad2 = `OC8051_WAD_N;
3022
          rom_addr_sel = `OC8051_RAS_PC;
3023
 
3024
        end
3025
      default: begin
3026
          ram_rd_sel = `OC8051_RRS_DC;
3027
          ram_wr_sel = `OC8051_RWS_DC;
3028
          src_sel1 = `OC8051_ASS_DC;
3029
          src_sel2 = `OC8051_ASS_DC;
3030
          alu_op = `OC8051_ALU_NOP;
3031
          imm_sel = `OC8051_IDS_DC;
3032
          wr = 1'b0;
3033
          psw_set = `OC8051_PS_NOT;
3034
          cy_sel = `OC8051_CY_0;
3035
          pc_wr = `OC8051_PCW_N;
3036
          pc_sel = `OC8051_PIS_DC;
3037
          src_sel3 = `OC8051_AS3_DC;
3038
          comp_sel = `OC8051_CSS_DC;
3039
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
3040
          wad2 = `OC8051_WAD_N;
3041
          rom_addr_sel = `OC8051_RAS_PC;
3042
 
3043
       end
3044
 
3045
    endcase
3046
    end
3047
    endcase
3048
  end
3049
end
3050
 
3051
//
3052
// remember current instruction
3053
always @(posedge clk or posedge rst)
3054
  if (rst) op <= #1 2'b00;
3055
  else if (state==2'b00) op <= #1 op_in;
3056
 
3057
//
3058
// in case of instructions that needs more than one clock set state
3059
always @(posedge clk or posedge rst)
3060
begin
3061
  if (rst)
3062
    state <= #1 2'b01;
3063 54 simont
  else if (istb_t && !iack) begin
3064
    state <= #1 2'b01;
3065
  end else begin
3066 40 simont
    case (state)
3067
      2'b10: state <= #1 2'b01;
3068
      2'b11: state <= #1 2'b10;
3069
      2'b00:
3070
        casex (op_in)
3071
          `OC8051_ACALL :state <= #1 2'b01;
3072
          `OC8051_AJMP : state <= #1 2'b01;
3073
          `OC8051_CJNE_R :state <= #1 2'b11;
3074
          `OC8051_CJNE_I :state <= #1 2'b11;
3075
          `OC8051_CJNE_D : state <= #1 2'b11;
3076
          `OC8051_CJNE_C : state <= #1 2'b11;
3077
          `OC8051_LJMP : state <= #1 2'b01;
3078
          `OC8051_DJNZ_R :state <= #1 2'b11;
3079
          `OC8051_DJNZ_D :state <= #1 2'b11;
3080
          `OC8051_LCALL :state <= #1 2'b01;
3081
          `OC8051_MOVC_DP :state <= #1 2'b10;
3082
          `OC8051_MOVC_PC :state <= #1 2'b10;
3083
          `OC8051_RET : state <= #1 2'b11;
3084
          `OC8051_RETI : state <= #1 2'b11;
3085
          `OC8051_SJMP : state <= #1 2'b10;
3086
          `OC8051_JB : state <= #1 2'b10;
3087
          `OC8051_JBC : state <= #1 2'b10;
3088
          `OC8051_JC : state <= #1 2'b10;
3089
          `OC8051_JMP : state <= #1 2'b10;
3090
          `OC8051_JNC : state <= #1 2'b10;
3091
          `OC8051_JNB : state <= #1 2'b10;
3092
          `OC8051_JNZ : state <= #1 2'b10;
3093
          `OC8051_JZ : state <= #1 2'b10;
3094
          `OC8051_DIV : state <= #1 2'b11;
3095
          `OC8051_MUL : state <= #1 2'b11;
3096
          default: state <= #1 2'b00;
3097
        endcase
3098
      default: state <= #1 2'b00;
3099
    endcase
3100
  end
3101
end
3102
 
3103
//
3104
//in case of reti
3105
always @(posedge clk or posedge rst)
3106
  if (rst) reti <= #1 1'b0;
3107
  else if (op==`OC8051_RETI) reti <= #1 1'b1;
3108
  else reti <= #1 1'b0;
3109
 
3110
//
3111
//in case of writing to external ram
3112
always @(op_in or rd)
3113
begin
3114
  if (rd)
3115
  begin
3116
    casex (op_in)
3117
      `OC8051_MOVX_AI : begin
3118
        stb = 1'b0;
3119
        write_x = 1'b1;
3120
      end
3121
      `OC8051_MOVX_AP : begin
3122
        stb = 1'b0;
3123
        write_x = 1'b1;
3124
      end
3125
      `OC8051_MOVX_IA : begin
3126
        stb = 1'b1;
3127
        write_x = 1'b0;
3128
      end
3129
      `OC8051_MOVX_PA : begin
3130
        stb = 1'b1;
3131
        write_x = 1'b0;
3132
      end
3133
      default : begin
3134
        stb = 1'b0;
3135
        write_x = 1'b0;
3136
      end
3137
    endcase
3138
  end else begin
3139
    write_x = 1'b0;
3140
    stb =1'b0;
3141
  end
3142
end
3143
 
3144
always @(op_in)
3145
begin
3146
  casex (op_in)
3147
    `OC8051_MOVX_AI : begin
3148
      ext_addr_sel = `OC8051_EAS_RI;
3149
      wr_xaddr = 1'b1;
3150
    end
3151
    `OC8051_MOVX_AP : begin
3152
      ext_addr_sel =  `OC8051_EAS_DPTR;
3153
      wr_xaddr = 1'b1;
3154
    end
3155
    `OC8051_MOVX_IA : begin
3156
      ext_addr_sel = `OC8051_EAS_RI;
3157
      wr_xaddr = 1'b1;
3158
    end
3159
    `OC8051_MOVX_PA : begin
3160
      ext_addr_sel = `OC8051_EAS_DPTR;
3161
      wr_xaddr = 1'b1;
3162
    end
3163
    default: begin
3164
      wr_xaddr = 1'b0;
3165
      ext_addr_sel = `OC8051_EAS_DPTR;
3166
    end
3167
  endcase
3168
end
3169
 
3170
 
3171
 
3172
always @(posedge clk or posedge rst)
3173
begin
3174
  if (rst) begin
3175
    stbw <= #1 1'b0;
3176
  end else
3177
    stbw <= #1 write_x;
3178
end
3179
 
3180
 
3181
always @(posedge clk or posedge rst)
3182
begin
3183
  if (rst) begin
3184
    stb_buff <= #1 1'b0;
3185
    we_buff <= #1 1'b0;
3186
  end else if (ack_i) begin
3187
    stb_buff <= #1 1'b0;
3188
    we_buff <= #1 1'b0;
3189
  end else if (stb || stbw) begin
3190
    stb_buff <= #1 1'b1;
3191
  end else if (write_x) begin
3192
    we_buff <= #1 1'b1;
3193
  end
3194
end
3195 54 simont
 
3196
 
3197
always @(posedge clk or posedge rst)
3198
begin
3199
  if (rst)
3200
    istb_t <= #1 1'b0;
3201
  else if (((op_in == `OC8051_MOVC_DP) || (op_in == `OC8051_MOVC_PC)) && !ea)
3202
    istb_t <= #1 1'b1;
3203
  else if (iack)
3204
    istb_t <= #1 1'b0;
3205
end
3206
 
3207 40 simont
endmodule
3208
 
3209
 

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