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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 2

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//
// version 1.0
//
 
 
 
//clk  clock (pin)
//rst  reset (pin)
//wr_addr  address for selecting different registers (input)
//data_in  data input (input)
//wr   read/write signal (input)
//tf0  signal for timer interrupt 0 (input)
//tf1  signal for timer interrupt 1 (input)
//ie0   signal for external interrupt 0 (input)
//ie1   signal for external interrupt 1 (input)
//reti  return from interrupt signal (input)
//int_src  describes interrupt source (output)
//ip  ip register (internal)
//ie  ie register (internal)
//tcon  tcon register (internal)
//id  id register (internal)
 
 
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, int, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);
input [7:0] wr_addr, data_in, rd_addr;
input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;
 
output tr0, tr1, int, bit_out;
output [7:0] int_vec, data_out;
 
reg [7:0] ip, ie, int_vec, id, data_out;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
wire [7:0] tcon;
 
//
// isrc_cur     current interrupt source
// isrc_w       waiting interrupt source
reg [2:0] isrc_cur, isrc_w;
 
//
// contains witch level of interrupts is running
reg [1:0] int_levl, int_levl_w;
 
//
// int_l0       waiting interrupts on level 0
// int_l1       waiting interrupts on level 1
wire [4:0] int_l0, int_l1;
wire il0, il1;
 
integer n;
 
 
//reg set_tf0, set_tf1, set_ie0, set_ie1;
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;
 
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign int = |int_vec;
 
assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
assign il0 = |int_l0;
assign il1 = |int_l1;
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ip <=#1 `OC8051_RST_IP;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
    ip <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
    ip[wr_addr[2:0]] <= #1 bit_in;
end
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ie <=#1 `OC8051_RST_IE;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
    ie <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
    ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
   tcon_s <=#1 4'b0000;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
   case (wr_addr[2:0])
     3'b000: tcon_s[0] <= #1 bit_in;
     3'b010: tcon_s[1] <= #1 bit_in;
     3'b100: tcon_s[2] <= #1 bit_in;
     3'b110: tcon_s[3] <= #1 bit_in;
   endcase
 end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_tf1 <=#1 `OC8051_RST_TCON[7];
   tcon_tf1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf1 <= #1 data_in[7];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
   tcon_tf1 <= #1 bit_in;
 end else if (!(tf1_buff) & (tf1)) begin
   tcon_tf1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
   tcon_tf1 <= #1 1'b0;
 end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_tf0 <=#1 `OC8051_RST_TCON[5];
   tcon_tf0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf0 <= #1 data_in[5];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
   tcon_tf0 <= #1 bit_in;
 end else if (!(tf0_buff) & (tf0)) begin
   tcon_tf0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
   tcon_tf0 <= #1 1'b0;
 end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_ie0 <=#1 `OC8051_RST_TCON[1];
   tcon_ie0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie0 <= #1 data_in[1];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
   tcon_ie0 <= #1 bit_in;
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
   tcon_ie0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
   tcon_ie0 <= #1 1'b0;
 end else if (!(tcon_s[0]) & (ie0)) begin
   tcon_ie0 <= #1 1'b0;
 end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_ie1 <=#1 `OC8051_RST_TCON[3];
   tcon_ie1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie1 <= #1 data_in[3];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
   tcon_ie1 <= #1 bit_in;
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
   tcon_ie1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
   tcon_ie1 <= #1 1'b0;
 end else if (!(tcon_s[1]) & (ie1)) begin
   tcon_ie1 <= #1 1'b0;
 end
end
 
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   int_vec <= #1 8'h00;
   isrc_cur <= #1 `OC8051_ISRC_NO;
   isrc_w <= #1 `OC8051_ISRC_NO;
   int_levl <= #1 `OC8051_ILEV_NO;
   int_levl_w <= #1 `OC8051_ILEV_NO;
 end else if (reti) begin  // return from interrupt
   isrc_cur <= #1 isrc_w;
   int_levl <= #1 int_levl_w;
 end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin  // interrupt on level 1
   isrc_w <= #1 isrc_cur;
   int_levl <= #1 `OC8051_ILEV_L1;
   int_levl_w <= #1 int_levl;
   if (int_l1[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc_cur <= #1 `OC8051_ISRC_IE0;
   end else if (int_l1[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc_cur <= #1 `OC8051_ISRC_TF0;
   end else if (int_l1[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc_cur <= #1 `OC8051_ISRC_IE1;
   end else if (int_l1[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc_cur <= #1 `OC8051_ISRC_TF1;
   end else if (int_l1[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc_cur <= #1 `OC8051_ISRC_UART;
   end
 end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin  // interrupt on level 0
   int_levl <= #1 `OC8051_ILEV_L0;
   if (int_l0[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc_cur <= #1 `OC8051_ISRC_IE0;
   end else if (int_l0[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc_cur <= #1 `OC8051_ISRC_TF0;
   end else if (int_l0[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc_cur <= #1 `OC8051_ISRC_IE1;
   end else if (int_l0[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc_cur <= #1 `OC8051_ISRC_TF1;
   end else if (int_l0[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc_cur <= #1 `OC8051_ISRC_UART;
   end
 end else begin
   int_vec <= #1 8'h00;
 end
end
 
 
always @(posedge clk)
begin
  if (wr & !wr_bit & (wr_addr==rd_addr) & (
     (wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_IP: data_out <= #1 ip;
      `OC8051_SFR_IE: data_out <= #1 ie;
      default: data_out <= #1 tcon;
    endcase
  end
end
 
always @(posedge clk)
  tf0_buff <= #1 tf0;
 
always @(posedge clk)
  tf1_buff <= #1 tf1;
 
always @(posedge clk)
  ie0_buff <= #1 ie0;
 
always @(posedge clk)
  ie1_buff <= #1 ie1;
 
always  @(posedge clk)
begin
  if (wr & wr_bit & (wr_addr==rd_addr) & ((wr_addr[7:3]==`OC8051_SFR_B_IP) |
     (wr_addr[7:3]==`OC8051_SFR_B_IE) | (wr_addr[7:3]==`OC8051_SFR_B_TCON))) begin
    bit_out <= #1 bit_in;
  end else begin
    case (rd_addr[7:3])
      `OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
      `OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
      default: bit_out <= #1 tcon[rd_addr[2:0]];
    endcase
  end
end
 
 
endmodule

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	simont	`//`
2			`// version 1.0`
3			`//`
4
5
6
7			`//clk clock (pin)`
8			`//rst reset (pin)`
9			`//wr_addr address for selecting different registers (input)`
10			`//data_in data input (input)`
11			`//wr read/write signal (input)`
12			`//tf0 signal for timer interrupt 0 (input)`
13			`//tf1 signal for timer interrupt 1 (input)`
14			`//ie0 signal for external interrupt 0 (input)`
15			`//ie1 signal for external interrupt 1 (input)`
16			`//reti return from interrupt signal (input)`
17			`//int_src describes interrupt source (output)`
18			`//ip ip register (internal)`
19			`//ie ie register (internal)`
20			`//tcon tcon register (internal)`
21			`//id id register (internal)`
22
23
24
25
26			`include "oc8051_defines.v"
27
28			`//synopsys translate_off`
29			`include "oc8051_timescale.v"
30			`//synopsys translate_on`
31
32
33
34			`module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, int, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);`
35			`input [7:0] wr_addr, data_in, rd_addr;`
36			`input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;`
37
38			`output tr0, tr1, int, bit_out;`
39			`output [7:0] int_vec, data_out;`
40
41			`reg [7:0] ip, ie, int_vec, id, data_out;`
42
43			`reg [3:0] tcon_s;`
44			`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;`
45			`wire [7:0] tcon;`
46
47			`//`
48			`// isrc_cur current interrupt source`
49			`// isrc_w waiting interrupt source`
50			`reg [2:0] isrc_cur, isrc_w;`
51
52			`//`
53			`// contains witch level of interrupts is running`
54			`reg [1:0] int_levl, int_levl_w;`
55
56			`//`
57			`// int_l0 waiting interrupts on level 0`
58			`// int_l1 waiting interrupts on level 1`
59			`wire [4:0] int_l0, int_l1;`
60			`wire il0, il1;`
61
62			`integer n;`
63
64
65			`//reg set_tf0, set_tf1, set_ie0, set_ie1;`
66			`reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;`
67			`//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;`
68
69			`assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};`
70			`assign tr0 = tcon_s[2];`
71			`assign tr1 = tcon_s[3];`
72			`assign int = \|int_vec;`
73
74			`assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
75			`assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
76			`assign il0 = \|int_l0;`
77			`assign il1 = \|int_l1;`
78
79			`always @(posedge clk or posedge rst)`
80			`begin`
81			`if (rst) begin`
82			ip <=#1 `OC8051_RST_IP;
83			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
84			`ip <= #1 data_in;`
85			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
86			`ip[wr_addr[2:0]] <= #1 bit_in;`
87			`end`
88
89			`always @(posedge clk or posedge rst)`
90			`begin`
91			`if (rst) begin`
92			ie <=#1 `OC8051_RST_IE;
93			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
94			`ie <= #1 data_in;`
95			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
96			`ie[wr_addr[2:0]] <= #1 bit_in;`
97			`end`
98
99			`//`
100			`// tcon_s`
101			`//`
102			`always @(posedge clk or posedge rst)`
103			`begin`
104			`if (rst) begin`
105			// tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
106			`tcon_s <=#1 4'b0000;`
107			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
108			`tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};`
109			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
110			`case (wr_addr[2:0])`
111			`3'b000: tcon_s[0] <= #1 bit_in;`
112			`3'b010: tcon_s[1] <= #1 bit_in;`
113			`3'b100: tcon_s[2] <= #1 bit_in;`
114			`3'b110: tcon_s[3] <= #1 bit_in;`
115			`endcase`
116			`end`
117			`end`
118
119			`//`
120			`// tf1 (tmod.7)`
121			`//`
122			`always @(posedge clk or posedge rst)`
123			`begin`
124			`if (rst) begin`
125			// tcon_tf1 <=#1 `OC8051_RST_TCON[7];
126			`tcon_tf1 <=#1 1'b0;`
127			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
128			`tcon_tf1 <= #1 data_in[7];`
129			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
130			`tcon_tf1 <= #1 bit_in;`
131			`end else if (!(tf1_buff) & (tf1)) begin`
132			`tcon_tf1 <= #1 1'b1;`
133			end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
134			`tcon_tf1 <= #1 1'b0;`
135			`end`
136			`end`
137
138			`//`
139			`// tf0 (tmod.5)`
140			`//`
141			`always @(posedge clk or posedge rst)`
142			`begin`
143			`if (rst) begin`
144			// tcon_tf0 <=#1 `OC8051_RST_TCON[5];
145			`tcon_tf0 <=#1 1'b0;`
146			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
147			`tcon_tf0 <= #1 data_in[5];`
148			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
149			`tcon_tf0 <= #1 bit_in;`
150			`end else if (!(tf0_buff) & (tf0)) begin`
151			`tcon_tf0 <= #1 1'b1;`
152			end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
153			`tcon_tf0 <= #1 1'b0;`
154			`end`
155			`end`
156
157
158			`//`
159			`// ie0 (tmod.1)`
160			`//`
161			`always @(posedge clk or posedge rst)`
162			`begin`
163			`if (rst) begin`
164			// tcon_ie0 <=#1 `OC8051_RST_TCON[1];
165			`tcon_ie0 <=#1 1'b0;`
166			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
167			`tcon_ie0 <= #1 data_in[1];`
168			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
169			`tcon_ie0 <= #1 bit_in;`
170			`end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) \| (!(tcon_s[0]) & !(ie0))) begin`
171			`tcon_ie0 <= #1 1'b1;`
172			end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
173			`tcon_ie0 <= #1 1'b0;`
174			`end else if (!(tcon_s[0]) & (ie0)) begin`
175			`tcon_ie0 <= #1 1'b0;`
176			`end`
177			`end`
178
179
180			`//`
181			`// ie1 (tmod.3)`
182			`//`
183			`always @(posedge clk or posedge rst)`
184			`begin`
185			`if (rst) begin`
186			// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
187			`tcon_ie1 <=#1 1'b0;`
188			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
189			`tcon_ie1 <= #1 data_in[3];`
190			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
191			`tcon_ie1 <= #1 bit_in;`
192			`end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) \| (!(tcon_s[1]) & !(ie1))) begin`
193			`tcon_ie1 <= #1 1'b1;`
194			end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
195			`tcon_ie1 <= #1 1'b0;`
196			`end else if (!(tcon_s[1]) & (ie1)) begin`
197			`tcon_ie1 <= #1 1'b0;`
198			`end`
199			`end`
200
201
202			`always @(posedge clk or posedge rst)`
203			`begin`
204			`if (rst) begin`
205			`int_vec <= #1 8'h00;`
206			isrc_cur <= #1 `OC8051_ISRC_NO;
207			isrc_w <= #1 `OC8051_ISRC_NO;
208			int_levl <= #1 `OC8051_ILEV_NO;
209			int_levl_w <= #1 `OC8051_ILEV_NO;
210			`end else if (reti) begin // return from interrupt`
211			`isrc_cur <= #1 isrc_w;`
212			`int_levl <= #1 int_levl_w;`
213			end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin // interrupt on level 1
214			`isrc_w <= #1 isrc_cur;`
215			int_levl <= #1 `OC8051_ILEV_L1;
216			`int_levl_w <= #1 int_levl;`
217			`if (int_l1[0]) begin`
218			int_vec <= #1 `OC8051_INT_X0;
219			isrc_cur <= #1 `OC8051_ISRC_IE0;
220			`end else if (int_l1[1]) begin`
221			int_vec <= #1 `OC8051_INT_T0;
222			isrc_cur <= #1 `OC8051_ISRC_TF0;
223			`end else if (int_l1[2]) begin`
224			int_vec <= #1 `OC8051_INT_X1;
225			isrc_cur <= #1 `OC8051_ISRC_IE1;
226			`end else if (int_l1[3]) begin`
227			int_vec <= #1 `OC8051_INT_T1;
228			isrc_cur <= #1 `OC8051_ISRC_TF1;
229			`end else if (int_l1[4]) begin`
230			int_vec <= #1 `OC8051_INT_UART;
231			isrc_cur <= #1 `OC8051_ISRC_UART;
232			`end`
233			end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin // interrupt on level 0
234			int_levl <= #1 `OC8051_ILEV_L0;
235			`if (int_l0[0]) begin`
236			int_vec <= #1 `OC8051_INT_X0;
237			isrc_cur <= #1 `OC8051_ISRC_IE0;
238			`end else if (int_l0[1]) begin`
239			int_vec <= #1 `OC8051_INT_T0;
240			isrc_cur <= #1 `OC8051_ISRC_TF0;
241			`end else if (int_l0[2]) begin`
242			int_vec <= #1 `OC8051_INT_X1;
243			isrc_cur <= #1 `OC8051_ISRC_IE1;
244			`end else if (int_l0[3]) begin`
245			int_vec <= #1 `OC8051_INT_T1;
246			isrc_cur <= #1 `OC8051_ISRC_TF1;
247			`end else if (int_l0[4]) begin`
248			int_vec <= #1 `OC8051_INT_UART;
249			isrc_cur <= #1 `OC8051_ISRC_UART;
250			`end`
251			`end else begin`
252			`int_vec <= #1 8'h00;`
253			`end`
254			`end`
255
256
257			`always @(posedge clk)`
258			`begin`
259			`if (wr & !wr_bit & (wr_addr==rd_addr) & (`
260			(wr_addr==`OC8051_SFR_IP) \| (wr_addr==`OC8051_SFR_IE) \| (wr_addr==`OC8051_SFR_TCON))) begin
261			`data_out <= #1 data_in;`
262			`end else begin`
263			`case (rd_addr)`
264			`OC8051_SFR_IP: data_out <= #1 ip;
265			`OC8051_SFR_IE: data_out <= #1 ie;
266			`default: data_out <= #1 tcon;`
267			`endcase`
268			`end`
269			`end`
270
271			`always @(posedge clk)`
272			`tf0_buff <= #1 tf0;`
273
274			`always @(posedge clk)`
275			`tf1_buff <= #1 tf1;`
276
277			`always @(posedge clk)`
278			`ie0_buff <= #1 ie0;`
279
280			`always @(posedge clk)`
281			`ie1_buff <= #1 ie1;`
282
283			`always @(posedge clk)`
284			`begin`
285			if (wr & wr_bit & (wr_addr==rd_addr) & ((wr_addr[7:3]==`OC8051_SFR_B_IP) \|
286			(wr_addr[7:3]==`OC8051_SFR_B_IE) \| (wr_addr[7:3]==`OC8051_SFR_B_TCON))) begin
287			`bit_out <= #1 bit_in;`
288			`end else begin`
289			`case (rd_addr[7:3])`
290			`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
291			`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
292			`default: bit_out <= #1 tcon[rd_addr[2:0]];`
293			`endcase`
294			`end`
295			`end`
296
297
298			`endmodule`