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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 46

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores interrupt control module                         ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   contains sfr's: tcon, ip, ie;                              ////
////   interrupt handling                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Jaka Simsic, jakas@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
 
 
//clk  clock (pin)
//rst  reset (pin)
//wr_addr  address for selecting different registers (input)
//data_in  data input (input)
//wr   read/write signal (input)
//tf0  signal for timer interrupt 0 (input)
//tf1  signal for timer interrupt 1 (input)
//ie0   signal for external interrupt 0 (input)
//ie1   signal for external interrupt 1 (input)
//reti  return from interrupt signal (input)
//int_src  describes interrupt source (output)
//ip  ip register (internal)
//ie  ie register (internal)
//tcon  tcon register (internal)
 
 
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, intr, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);
input [7:0] wr_addr, data_in, rd_addr;
input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;
 
output tr0, tr1, intr, bit_out;
output [7:0] int_vec, data_out;
 
reg [7:0] ip, ie, int_vec, data_out;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
wire [7:0] tcon;
 
//
// isrc_cur     current interrupt source
// isrc_w       waiting interrupt source
reg [2:0] isrc_cur, isrc_w;
 
//
// contains witch level of interrupts is running
reg [1:0] int_levl, int_levl_w;
 
//
// int_l0       waiting interrupts on level 0
// int_l1       waiting interrupts on level 1
wire [4:0] int_l0, int_l1;
wire il0, il1;
 
//reg set_tf0, set_tf1, set_ie0, set_ie1;
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;
 
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
assign il0 = |int_l0;
assign il1 = |int_l1;
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ip <=#1 `OC8051_RST_IP;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
    ip <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
    ip[wr_addr[2:0]] <= #1 bit_in;
end
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ie <=#1 `OC8051_RST_IE;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
    ie <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
    ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
   tcon_s <=#1 4'b0000;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
   case (wr_addr[2:0])
     3'b000: tcon_s[0] <= #1 bit_in;
     3'b010: tcon_s[1] <= #1 bit_in;
     3'b100: tcon_s[2] <= #1 bit_in;
     3'b110: tcon_s[3] <= #1 bit_in;
   endcase
 end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_tf1 <=#1 `OC8051_RST_TCON[7];
   tcon_tf1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf1 <= #1 data_in[7];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
   tcon_tf1 <= #1 bit_in;
 end else if (!(tf1_buff) & (tf1)) begin
   tcon_tf1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
   tcon_tf1 <= #1 1'b0;
 end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_tf0 <=#1 `OC8051_RST_TCON[5];
   tcon_tf0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf0 <= #1 data_in[5];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
   tcon_tf0 <= #1 bit_in;
 end else if (!(tf0_buff) & (tf0)) begin
   tcon_tf0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
   tcon_tf0 <= #1 1'b0;
 end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_ie0 <=#1 `OC8051_RST_TCON[1];
   tcon_ie0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie0 <= #1 data_in[1];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
   tcon_ie0 <= #1 bit_in;
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
   tcon_ie0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
   tcon_ie0 <= #1 1'b0;
 end else if (!(tcon_s[0]) & (ie0)) begin
   tcon_ie0 <= #1 1'b0;
 end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_ie1 <=#1 `OC8051_RST_TCON[3];
   tcon_ie1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie1 <= #1 data_in[3];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
   tcon_ie1 <= #1 bit_in;
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
   tcon_ie1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
   tcon_ie1 <= #1 1'b0;
 end else if (!(tcon_s[1]) & (ie1)) begin
   tcon_ie1 <= #1 1'b0;
 end
end
 
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   int_vec <= #1 8'h00;
   isrc_cur <= #1 `OC8051_ISRC_NO;
   isrc_w <= #1 `OC8051_ISRC_NO;
   int_levl <= #1 `OC8051_ILEV_NO;
   int_levl_w <= #1 `OC8051_ILEV_NO;
 end else if (reti) begin  // return from interrupt
   isrc_cur <= #1 isrc_w;
   int_levl <= #1 int_levl_w;
 end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin  // interrupt on level 1
   isrc_w <= #1 isrc_cur;
   int_levl <= #1 `OC8051_ILEV_L1;
   int_levl_w <= #1 int_levl;
   if (int_l1[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc_cur <= #1 `OC8051_ISRC_IE0;
   end else if (int_l1[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc_cur <= #1 `OC8051_ISRC_TF0;
   end else if (int_l1[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc_cur <= #1 `OC8051_ISRC_IE1;
   end else if (int_l1[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc_cur <= #1 `OC8051_ISRC_TF1;
   end else if (int_l1[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc_cur <= #1 `OC8051_ISRC_UART;
   end
 end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin  // interrupt on level 0
   int_levl <= #1 `OC8051_ILEV_L0;
   if (int_l0[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc_cur <= #1 `OC8051_ISRC_IE0;
   end else if (int_l0[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc_cur <= #1 `OC8051_ISRC_TF0;
   end else if (int_l0[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc_cur <= #1 `OC8051_ISRC_IE1;
   end else if (int_l0[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc_cur <= #1 `OC8051_ISRC_TF1;
   end else if (int_l0[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc_cur <= #1 `OC8051_ISRC_UART;
   end
 end else begin
   int_vec <= #1 8'h00;
 end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & (
     (wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_IP: data_out <= #1 ip;
      `OC8051_SFR_IE: data_out <= #1 ie;
      default: data_out <= #1 tcon;
    endcase
  end
end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    tf0_buff <= #1 1'b0;
    tf1_buff <= #1 1'b0;
    ie0_buff <= #1 1'b0;
    ie1_buff <= #1 1'b0;
  end else begin
    tf0_buff <= #1 tf0;
    tf1_buff <= #1 tf1;
    ie0_buff <= #1 ie0;
    ie1_buff <= #1 ie1;
  end
 
always @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (wr_addr==rd_addr)) begin
    bit_out <= #1 bit_in;
  end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
    bit_out <= #1 data_in[rd_addr[2:0]];
  end else begin
    case (rd_addr[7:3])
      `OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
      `OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
      default: bit_out <= #1 tcon[rd_addr[2:0]];
    endcase
  end
end
 
 
endmodule

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 46

Line No.	Rev	Author	Line
1	46	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores interrupt control module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// contains sfr's: tcon, ip, ie; ////`
10			`//// interrupt handling ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Teran, simont@opencores.org ////`
17			`//// - Jaka Simsic, jakas@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49			`//`
50
51
52
53			`//clk clock (pin)`
54			`//rst reset (pin)`
55			`//wr_addr address for selecting different registers (input)`
56			`//data_in data input (input)`
57			`//wr read/write signal (input)`
58			`//tf0 signal for timer interrupt 0 (input)`
59			`//tf1 signal for timer interrupt 1 (input)`
60			`//ie0 signal for external interrupt 0 (input)`
61			`//ie1 signal for external interrupt 1 (input)`
62			`//reti return from interrupt signal (input)`
63			`//int_src describes interrupt source (output)`
64			`//ip ip register (internal)`
65			`//ie ie register (internal)`
66			`//tcon tcon register (internal)`
67
68
69
70
71			`include "oc8051_defines.v"
72
73			`//synopsys translate_off`
74			`include "oc8051_timescale.v"
75			`//synopsys translate_on`
76
77
78
79			`module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, intr, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);`
80			`input [7:0] wr_addr, data_in, rd_addr;`
81			`input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;`
82
83			`output tr0, tr1, intr, bit_out;`
84			`output [7:0] int_vec, data_out;`
85
86			`reg [7:0] ip, ie, int_vec, data_out;`
87
88			`reg [3:0] tcon_s;`
89			`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;`
90			`wire [7:0] tcon;`
91
92			`//`
93			`// isrc_cur current interrupt source`
94			`// isrc_w waiting interrupt source`
95			`reg [2:0] isrc_cur, isrc_w;`
96
97			`//`
98			`// contains witch level of interrupts is running`
99			`reg [1:0] int_levl, int_levl_w;`
100
101			`//`
102			`// int_l0 waiting interrupts on level 0`
103			`// int_l1 waiting interrupts on level 1`
104			`wire [4:0] int_l0, int_l1;`
105			`wire il0, il1;`
106
107			`//reg set_tf0, set_tf1, set_ie0, set_ie1;`
108			`reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;`
109			`//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;`
110
111			`assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};`
112			`assign tr0 = tcon_s[2];`
113			`assign tr1 = tcon_s[3];`
114			`assign intr = \|int_vec;`
115
116			`assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
117			`assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
118			`assign il0 = \|int_l0;`
119			`assign il1 = \|int_l1;`
120
121			`always @(posedge clk or posedge rst)`
122			`begin`
123			`if (rst) begin`
124			ip <=#1 `OC8051_RST_IP;
125			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
126			`ip <= #1 data_in;`
127			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
128			`ip[wr_addr[2:0]] <= #1 bit_in;`
129			`end`
130
131			`always @(posedge clk or posedge rst)`
132			`begin`
133			`if (rst) begin`
134			ie <=#1 `OC8051_RST_IE;
135			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
136			`ie <= #1 data_in;`
137			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
138			`ie[wr_addr[2:0]] <= #1 bit_in;`
139			`end`
140
141			`//`
142			`// tcon_s`
143			`//`
144			`always @(posedge clk or posedge rst)`
145			`begin`
146			`if (rst) begin`
147			// tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
148			`tcon_s <=#1 4'b0000;`
149			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
150			`tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};`
151			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
152			`case (wr_addr[2:0])`
153			`3'b000: tcon_s[0] <= #1 bit_in;`
154			`3'b010: tcon_s[1] <= #1 bit_in;`
155			`3'b100: tcon_s[2] <= #1 bit_in;`
156			`3'b110: tcon_s[3] <= #1 bit_in;`
157			`endcase`
158			`end`
159			`end`
160
161			`//`
162			`// tf1 (tmod.7)`
163			`//`
164			`always @(posedge clk or posedge rst)`
165			`begin`
166			`if (rst) begin`
167			// tcon_tf1 <=#1 `OC8051_RST_TCON[7];
168			`tcon_tf1 <=#1 1'b0;`
169			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
170			`tcon_tf1 <= #1 data_in[7];`
171			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
172			`tcon_tf1 <= #1 bit_in;`
173			`end else if (!(tf1_buff) & (tf1)) begin`
174			`tcon_tf1 <= #1 1'b1;`
175			end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
176			`tcon_tf1 <= #1 1'b0;`
177			`end`
178			`end`
179
180			`//`
181			`// tf0 (tmod.5)`
182			`//`
183			`always @(posedge clk or posedge rst)`
184			`begin`
185			`if (rst) begin`
186			// tcon_tf0 <=#1 `OC8051_RST_TCON[5];
187			`tcon_tf0 <=#1 1'b0;`
188			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
189			`tcon_tf0 <= #1 data_in[5];`
190			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
191			`tcon_tf0 <= #1 bit_in;`
192			`end else if (!(tf0_buff) & (tf0)) begin`
193			`tcon_tf0 <= #1 1'b1;`
194			end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
195			`tcon_tf0 <= #1 1'b0;`
196			`end`
197			`end`
198
199
200			`//`
201			`// ie0 (tmod.1)`
202			`//`
203			`always @(posedge clk or posedge rst)`
204			`begin`
205			`if (rst) begin`
206			// tcon_ie0 <=#1 `OC8051_RST_TCON[1];
207			`tcon_ie0 <=#1 1'b0;`
208			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
209			`tcon_ie0 <= #1 data_in[1];`
210			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
211			`tcon_ie0 <= #1 bit_in;`
212			`end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) \| (!(tcon_s[0]) & !(ie0))) begin`
213			`tcon_ie0 <= #1 1'b1;`
214			end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
215			`tcon_ie0 <= #1 1'b0;`
216			`end else if (!(tcon_s[0]) & (ie0)) begin`
217			`tcon_ie0 <= #1 1'b0;`
218			`end`
219			`end`
220
221
222			`//`
223			`// ie1 (tmod.3)`
224			`//`
225			`always @(posedge clk or posedge rst)`
226			`begin`
227			`if (rst) begin`
228			// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
229			`tcon_ie1 <=#1 1'b0;`
230			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
231			`tcon_ie1 <= #1 data_in[3];`
232			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
233			`tcon_ie1 <= #1 bit_in;`
234			`end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) \| (!(tcon_s[1]) & !(ie1))) begin`
235			`tcon_ie1 <= #1 1'b1;`
236			end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
237			`tcon_ie1 <= #1 1'b0;`
238			`end else if (!(tcon_s[1]) & (ie1)) begin`
239			`tcon_ie1 <= #1 1'b0;`
240			`end`
241			`end`
242
243
244			`always @(posedge clk or posedge rst)`
245			`begin`
246			`if (rst) begin`
247			`int_vec <= #1 8'h00;`
248			isrc_cur <= #1 `OC8051_ISRC_NO;
249			isrc_w <= #1 `OC8051_ISRC_NO;
250			int_levl <= #1 `OC8051_ILEV_NO;
251			int_levl_w <= #1 `OC8051_ILEV_NO;
252			`end else if (reti) begin // return from interrupt`
253			`isrc_cur <= #1 isrc_w;`
254			`int_levl <= #1 int_levl_w;`
255			end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin // interrupt on level 1
256			`isrc_w <= #1 isrc_cur;`
257			int_levl <= #1 `OC8051_ILEV_L1;
258			`int_levl_w <= #1 int_levl;`
259			`if (int_l1[0]) begin`
260			int_vec <= #1 `OC8051_INT_X0;
261			isrc_cur <= #1 `OC8051_ISRC_IE0;
262			`end else if (int_l1[1]) begin`
263			int_vec <= #1 `OC8051_INT_T0;
264			isrc_cur <= #1 `OC8051_ISRC_TF0;
265			`end else if (int_l1[2]) begin`
266			int_vec <= #1 `OC8051_INT_X1;
267			isrc_cur <= #1 `OC8051_ISRC_IE1;
268			`end else if (int_l1[3]) begin`
269			int_vec <= #1 `OC8051_INT_T1;
270			isrc_cur <= #1 `OC8051_ISRC_TF1;
271			`end else if (int_l1[4]) begin`
272			int_vec <= #1 `OC8051_INT_UART;
273			isrc_cur <= #1 `OC8051_ISRC_UART;
274			`end`
275			end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin // interrupt on level 0
276			int_levl <= #1 `OC8051_ILEV_L0;
277			`if (int_l0[0]) begin`
278			int_vec <= #1 `OC8051_INT_X0;
279			isrc_cur <= #1 `OC8051_ISRC_IE0;
280			`end else if (int_l0[1]) begin`
281			int_vec <= #1 `OC8051_INT_T0;
282			isrc_cur <= #1 `OC8051_ISRC_TF0;
283			`end else if (int_l0[2]) begin`
284			int_vec <= #1 `OC8051_INT_X1;
285			isrc_cur <= #1 `OC8051_ISRC_IE1;
286			`end else if (int_l0[3]) begin`
287			int_vec <= #1 `OC8051_INT_T1;
288			isrc_cur <= #1 `OC8051_ISRC_TF1;
289			`end else if (int_l0[4]) begin`
290			int_vec <= #1 `OC8051_INT_UART;
291			isrc_cur <= #1 `OC8051_ISRC_UART;
292			`end`
293			`end else begin`
294			`int_vec <= #1 8'h00;`
295			`end`
296			`end`
297
298
299			`always @(posedge clk or posedge rst)`
300			`begin`
301			`if (rst) data_out <= #1 8'h0;`
302			`else if (wr & !wr_bit & (wr_addr==rd_addr) & (`
303			(wr_addr==`OC8051_SFR_IP) \| (wr_addr==`OC8051_SFR_IE) \| (wr_addr==`OC8051_SFR_TCON))) begin
304			`data_out <= #1 data_in;`
305			`end else begin`
306			`case (rd_addr)`
307			`OC8051_SFR_IP: data_out <= #1 ip;
308			`OC8051_SFR_IE: data_out <= #1 ie;
309			`default: data_out <= #1 tcon;`
310			`endcase`
311			`end`
312			`end`
313
314			`always @(posedge clk or posedge rst)`
315			`if (rst) begin`
316			`tf0_buff <= #1 1'b0;`
317			`tf1_buff <= #1 1'b0;`
318			`ie0_buff <= #1 1'b0;`
319			`ie1_buff <= #1 1'b0;`
320			`end else begin`
321			`tf0_buff <= #1 tf0;`
322			`tf1_buff <= #1 tf1;`
323			`ie0_buff <= #1 ie0;`
324			`ie1_buff <= #1 ie1;`
325			`end`
326
327			`always @(posedge clk or posedge rst)`
328			`begin`
329			`if (rst) bit_out <= #1 1'b0;`
330			`else if (wr & wr_bit & (wr_addr==rd_addr)) begin`
331			`bit_out <= #1 bit_in;`
332			`end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin`
333			`bit_out <= #1 data_in[rd_addr[2:0]];`
334			`end else begin`
335			`case (rd_addr[7:3])`
336			`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
337			`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
338			`default: bit_out <= #1 tcon[rd_addr[2:0]];`
339			`endcase`
340			`end`
341			`end`
342
343
344			`endmodule`