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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_psw.v] - Blame information for rev 76

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 program status word                                    ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   program status word                                        ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, bit_out, p, cy_in, ac_in, ov_in, set, bank_sel);
//
// clk          (in)  clock
// rst          (in)  reset
// addr         (in)  write address [oc8051_ram_wr_sel.out]
// data_in      (in)  data input [oc8051_alu.des1]
// wr           (in)  write [oc8051_decoder.wr -r]
// wr_bit       (in)  write bit addresable [oc8051_decoder.bit_addr -r]
// data_out     (out) data output [oc8051_ram_sel.psw]
// p            (in)  parity [oc8051_acc.p]
// cy_in        (in)  input bit data [oc8051_alu.desCy]
// ac_in        (in)  auxiliary carry input [oc8051_alu.desAc]
// ov_in        (in)  overflov input [oc8051_alu.desOv]
// set          (in)  set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]
//
 
 
input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;
input [1:0] set;
input [2:0] rd_addr;
input [7:0] wr_addr, data_in;
 
output bit_out;
output [1:0] bank_sel;
output [7:0] data_out;
 
reg bit_out;
reg [7:0] data;
wire wr_psw;
 
assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
 
assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
assign data_out = data;
 
//
//case writing to psw
always @(posedge clk or posedge rst)
begin
  if (rst)
    data <= #1 `OC8051_RST_PSW;
 
//
// write to psw (byte addressable)
  else begin
    if (wr & (wr_bit==1'b0) & (wr_addr==`OC8051_SFR_PSW))
      data[7:1] <= #1 data_in[7:1];
//
// write to psw (bit addressable)
    else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))
      data[wr_addr[2:0]] <= #1 cy_in;
    else begin
      case (set)
        `OC8051_PS_CY: begin
//
//write carry
          data[7] <= #1 cy_in;
        end
        `OC8051_PS_OV: begin
//
//write carry and overflov
          data[7] <= #1 cy_in;
          data[2] <= #1 ov_in;
        end
        `OC8051_PS_AC:begin
//
//write carry, overflov and ac
          data[7] <= #1 cy_in;
          data[6] <= #1 ac_in;
          data[2] <= #1 ov_in;
 
        end
      endcase
    end
    data[0] <= #1 p;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
      bit_out <= #1 cy_in;
  end else if ((wr_addr==`OC8051_SFR_PSW) & wr & !wr_bit) begin
      bit_out <= #1 data_in[rd_addr];
  end else bit_out <= #1 data_out[rd_addr];
end
 
endmodule

Line No.	Rev	Author	Line
1	76	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 program status word ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// program status word ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.7 2002/09/30 17:33:59 simont`
48			`// prepared header`
49			`//`
50			`//`
51
52
53			`// synopsys translate_off`
54			`include "oc8051_timescale.v"
55			`// synopsys translate_on`
56
57			`include "oc8051_defines.v"
58
59
60			`module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, bit_out, p, cy_in, ac_in, ov_in, set, bank_sel);`
61			`//`
62			`// clk (in) clock`
63			`// rst (in) reset`
64			`// addr (in) write address [oc8051_ram_wr_sel.out]`
65			`// data_in (in) data input [oc8051_alu.des1]`
66			`// wr (in) write [oc8051_decoder.wr -r]`
67			`// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]`
68			`// data_out (out) data output [oc8051_ram_sel.psw]`
69			`// p (in) parity [oc8051_acc.p]`
70			`// cy_in (in) input bit data [oc8051_alu.desCy]`
71			`// ac_in (in) auxiliary carry input [oc8051_alu.desAc]`
72			`// ov_in (in) overflov input [oc8051_alu.desOv]`
73			`// set (in) set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]`
74			`//`
75
76
77			`input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;`
78			`input [1:0] set;`
79			`input [2:0] rd_addr;`
80			`input [7:0] wr_addr, data_in;`
81
82			`output bit_out;`
83			`output [1:0] bank_sel;`
84			`output [7:0] data_out;`
85
86			`reg bit_out;`
87			`reg [7:0] data;`
88			`wire wr_psw;`
89
90			assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
91
92			`assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];`
93			`assign data_out = data;`
94
95			`//`
96			`//case writing to psw`
97			`always @(posedge clk or posedge rst)`
98			`begin`
99			`if (rst)`
100			data <= #1 `OC8051_RST_PSW;
101
102			`//`
103			`// write to psw (byte addressable)`
104			`else begin`
105			if (wr & (wr_bit==1'b0) & (wr_addr==`OC8051_SFR_PSW))
106			`data[7:1] <= #1 data_in[7:1];`
107			`//`
108			`// write to psw (bit addressable)`
109			else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))
110			`data[wr_addr[2:0]] <= #1 cy_in;`
111			`else begin`
112			`case (set)`
113			`OC8051_PS_CY: begin
114			`//`
115			`//write carry`
116			`data[7] <= #1 cy_in;`
117			`end`
118			`OC8051_PS_OV: begin
119			`//`
120			`//write carry and overflov`
121			`data[7] <= #1 cy_in;`
122			`data[2] <= #1 ov_in;`
123			`end`
124			`OC8051_PS_AC:begin
125			`//`
126			`//write carry, overflov and ac`
127			`data[7] <= #1 cy_in;`
128			`data[6] <= #1 ac_in;`
129			`data[2] <= #1 ov_in;`
130
131			`end`
132			`endcase`
133			`end`
134			`data[0] <= #1 p;`
135			`end`
136			`end`
137
138			`always @(posedge clk or posedge rst)`
139			`begin`
140			`if (rst) bit_out <= #1 1'b0;`
141			`else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin`
142			`bit_out <= #1 cy_in;`
143			end else if ((wr_addr==`OC8051_SFR_PSW) & wr & !wr_bit) begin
144			`bit_out <= #1 data_in[rd_addr];`
145			`end else bit_out <= #1 data_out[rd_addr];`
146			`end`
147
148			`endmodule`

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_psw.v] - Blame information for rev 76