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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_sp.v] - Blame information for rev 82

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 stack pointer                                          ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   8051 special function register: stack pointer.             ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.3  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
 
module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, data_out, sp_out, sp_w);
 
 
input clk, rst, wr, wr_bit;
input [2:0] ram_rd_sel, ram_wr_sel;
input [7:0] data_in, wr_addr;
output [7:0] data_out;
output [7:0] sp_out, sp_w;
 
reg [7:0] sp_out, sp_w;
reg pop;
wire write;
wire [7:0] sp_t;
 
reg [7:0] sp;
 
 
assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
 
assign sp_t= write ? data_in : sp;
 
assign data_out = sp;
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    sp <= #1 `OC8051_RST_SP;
  else if (write)
    sp <= #1 data_in;
  else
    sp <= #1 sp_out;
end
 
 
always @(sp or ram_wr_sel)
begin
//
// push
  if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
  else sp_w = sp;
 
end
 
 
always @(sp_t or ram_wr_sel or pop or write)
begin
//
// push
  if (write) sp_out = sp_t;
  else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
  else sp_out = sp_t - {7'b0, pop};
 
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    pop <= #1 1'b0;
  else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
  else pop <= #1 1'b0;
end
 
endmodule

Line No.	Rev	Author	Line
1	76	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 stack pointer ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 special function register: stack pointer. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	82	simont	`// Revision 1.4 2002/11/05 17:23:54 simont`
48			`// add module oc8051_sfr, 256 bytes internal ram`
49			`//`
50	76	simont	`// Revision 1.3 2002/09/30 17:33:59 simont`
51			`// prepared header`
52			`//`
53			`//`
54
55			`// synopsys translate_off`
56			`include "oc8051_timescale.v"
57			`// synopsys translate_on`
58
59			`include "oc8051_defines.v"
60
61
62
63	82	simont	`module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, data_out, sp_out, sp_w);`
64	76	simont
65
66			`input clk, rst, wr, wr_bit;`
67	82	simont	`input [2:0] ram_rd_sel, ram_wr_sel;`
68	76	simont	`input [7:0] data_in, wr_addr;`
69			`output [7:0] data_out;`
70	82	simont	`output [7:0] sp_out, sp_w;`
71	76	simont
72	82	simont	`reg [7:0] sp_out, sp_w;`
73			`reg pop;`
74			`wire write;`
75			`wire [7:0] sp_t;`
76	76	simont
77	82	simont	`reg [7:0] sp;`
78	76	simont
79
80	82	simont	assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
81
82			`assign sp_t= write ? data_in : sp;`
83
84			`assign data_out = sp;`
85
86	76	simont	`always @(posedge clk or posedge rst)`
87			`begin`
88			`if (rst)`
89	82	simont	sp <= #1 `OC8051_RST_SP;
90			`else if (write)`
91			`sp <= #1 data_in;`
92	76	simont	`else`
93	82	simont	`sp <= #1 sp_out;`
94	76	simont	`end`
95
96	82	simont
97			`always @(sp or ram_wr_sel)`
98	76	simont	`begin`
99			`//`
100			`// push`
101	82	simont	if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
102			`else sp_w = sp;`
103	76	simont
104			`end`
105
106
107	82	simont	`always @(sp_t or ram_wr_sel or pop or write)`
108			`begin`
109			`//`
110			`// push`
111			`if (write) sp_out = sp_t;`
112			else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
113			`else sp_out = sp_t - {7'b0, pop};`
114
115			`end`
116
117
118	76	simont	`always @(posedge clk or posedge rst)`
119			`begin`
120			`if (rst)`
121			`pop <= #1 1'b0;`
122			else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
123			`else pop <= #1 1'b0;`
124			`end`
125
126			`endmodule`

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_sp.v] - Blame information for rev 82