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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_tc.v] - Blame information for rev 112

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1 82 simont 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  8051 cores timer/counter control                            ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////   timers and counters handling for 8051 core                 ////
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////                                                              ////
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////  To Do:                                                      ////
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////   Nothing                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
47 112 simont 
// Revision 1.5  2003/01/13 14:14:41  simont
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// replace some modules
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//
50 82 simont 
// Revision 1.4  2002/09/30 17:33:59  simont
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// prepared header
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//
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//
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`include "oc8051_defines.v"
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//synopsys translate_off
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`include "oc8051_timescale.v"
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//synopsys translate_on
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63 112 simont 
module oc8051_tc (clk, rst,
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            wr_addr, rd_addr,
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            data_in, data_out,
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            wr, wr_bit,
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            ie0, ie1,
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            tr0, tr1,
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            t0, t1,
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            tf0, tf1,
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            pres_ow);
72 82 simont 
 
73 112 simont 
input [7:0]  wr_addr,
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             data_in,
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             rd_addr;
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input        clk,
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             rst,
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             wr,
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             wr_bit,
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             ie0,
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             ie1,
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             tr0,
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             tr1,
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             t0,
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             t1;
86 82 simont 
output [7:0] data_out;
87 112 simont 
output       tf0,
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             tf1,
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             pres_ow;
90 82 simont 
 
91 112 simont 
 
92 82 simont 
reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
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reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
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95 112 simont 
reg pres_ow;
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reg [3:0] prescaler;
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98 82 simont 
wire tc0_add, tc1_add;
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100 112 simont 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & ((!tmod[2] & pres_ow) | (tmod[2] & !t0 & t0_buff)));
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assign tc1_add = (tr1 & (!tmod[7] | !ie1) & ((!tmod[6] & pres_ow) | (tmod[6] & !t1 & t1_buff)));
102 82 simont 
assign tf1= tf1_0 | tf1_1;
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//
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// read or write from one of the addresses in tmod
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//
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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   tmod <=#1 `OC8051_RST_TMOD;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
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    tmod <= #1 data_in;
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end
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//
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// TIMER COUNTER 0
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//
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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   tl0 <=#1 `OC8051_RST_TL0;
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   th0 <=#1 `OC8051_RST_TH0;
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   tf0 <= #1 1'b0;
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   tf1_0 <= #1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
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   tl0 <= #1 data_in;
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   tf0 <= #1 1'b0;
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   tf1_0 <= #1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
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   th0 <= #1 data_in;
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   tf0 <= #1 1'b0;
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   tf1_0 <= #1 1'b0;
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 end else begin
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     case (tmod[1:0])
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      `OC8051_MODE0: begin                       // mode 0
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        tf1_0 <= #1 1'b0;
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        if (tc0_add)
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          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
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      end
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      `OC8051_MODE1: begin                       // mode 1
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        tf1_0 <= #1 1'b0;
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        if (tc0_add)
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          {tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
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      end
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      `OC8051_MODE2: begin                       // mode 2
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        tf1_0 <= #1 1'b0;
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        if (tc0_add) begin
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          if (tl0 == 8'b1111_1111) begin
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            tf0 <=#1 1'b1;
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            tl0 <=#1 th0;
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           end
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          else begin
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            tl0 <=#1 tl0 + 8'h1;
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            tf0 <= #1 1'b0;
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          end
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        end
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      end
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      `OC8051_MODE3: begin                       // mode 3
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         if (tc0_add)
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           {tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
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164 112 simont 
         if (tr1 & pres_ow)
165 82 simont 
           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
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      end
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      default:begin
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        tf0 <= #1 1'b0;
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        tf1_0 <= #1 1'b0;
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      end
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    endcase
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 end
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end
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//
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// TIMER COUNTER 1
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//
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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   tl1 <=#1 `OC8051_RST_TL1;
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   th1 <=#1 `OC8051_RST_TH1;
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   tf1_1 <= #1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
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   tl1 <= #1 data_in;
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   tf1_1 <= #1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
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   th1 <= #1 data_in;
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   tf1_1 <= #1 1'b0;
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 end else begin
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     case (tmod[5:4])
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      `OC8051_MODE0: begin                       // mode 0
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        if (tc1_add)
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          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
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      end
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      `OC8051_MODE1: begin                       // mode 1
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        if (tc1_add)
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          {tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
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      end
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      `OC8051_MODE2: begin                       // mode 2
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        if (tc1_add) begin
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          if (tl1 == 8'b1111_1111) begin
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            tf1_1 <=#1 1'b1;
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            tl1 <=#1 th1;
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           end
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          else begin
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            tl1 <=#1 tl1 + 8'h1;
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            tf1_1 <= #1 1'b0;
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          end
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        end
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      end
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      default:begin
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        tf1_1 <= #1 1'b0;
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      end
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    endcase
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 end
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end
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always @(posedge clk or posedge rst)
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begin
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  if (rst) data_out <= #1 8'h0;
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  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) |
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     (wr_addr==`OC8051_SFR_TH1)|(wr_addr==`OC8051_SFR_TL0)|(wr_addr==`OC8051_SFR_TL1)|
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     (wr_addr==`OC8051_SFR_TMOD))) begin
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    data_out <= #1 data_in;
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  end else begin
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    case (rd_addr)
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      `OC8051_SFR_TH0: data_out <= #1 th0;
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      `OC8051_SFR_TH1: data_out <= #1 th1;
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      `OC8051_SFR_TL0: data_out <= #1 tl0;
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      `OC8051_SFR_TL1: data_out <= #1 tl1;
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      default: data_out <= #1 tmod;
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    endcase
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  end
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end
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239 112 simont 
always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    prescaler <= #1 4'h0;
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    pres_ow <= #1 1'b0;
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  end else if (prescaler==4'b1011) begin
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    prescaler <= #1 4'h0;
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    pres_ow <= #1 1'b1;
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  end else begin
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    prescaler <= #1 prescaler + 4'h1;
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    pres_ow <= #1 1'b0;
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  end
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end
252 82 simont 
 
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always @(posedge clk or posedge rst)
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  if (rst) begin
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    t0_buff <= #1 1'b0;
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    t1_buff <= #1 1'b0;
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  end else begin
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    t0_buff <= #1 t0;
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    t1_buff <= #1 t1;
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  end
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endmodule

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