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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 10

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1 8 markom
// synopsys translate_off
2
`include "oc8051_timescale.v"
3
// synopsys translate_on
4
 
5
`include "oc8051_defines.v"
6
 
7 2 simont
module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
8 4 markom
                   rxd, txd, intr, t1_ow);
9 2 simont
 
10
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
11
input [7:0] rd_addr, data_in, wr_addr;
12
 
13 4 markom
output txd, intr, bit_out;
14 2 simont
output [7:0] data_out;
15
 
16
reg txd, bit_out;
17
reg [7:0] data_out;
18
 
19
reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;
20
reg receive, receive_buf, rxd_buf, r_int;
21
//
22
// mode 2 counter
23
reg [2:0] mode2_count;
24
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
25
reg [10:0] sbuf_rxd_tmp;
26
//
27
//tr_count      trancive counter
28
//re_count      receive counter
29
reg [3:0] tr_count, re_count;
30
 
31
//
32
// sam_cnt      sample counter
33
reg [2:0] sam_cnt, sample;
34
 
35 4 markom
assign intr = scon[1] | scon [0];
36 2 simont
 
37
//
38
//serial port control register
39
//
40
always @(posedge clk or posedge rst)
41
begin
42
  if (rst)
43
    scon <= #1 `OC8051_RST_SCON;
44
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
45
    scon <= #1 data_in;
46
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
47
    scon[wr_addr[2:0]] <= #1 bit_in;
48
  else if ((trans_buf) & !(trans))
49
    scon[1] <= #1 1'b1;
50
  else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
51
    case (scon[7:6])
52
      2'b00: scon[0] <= #1 1'b1;
53
      default: begin
54
        if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
55
        scon[2] <= #1 sbuf_rxd_tmp[9];
56
      end
57
    endcase
58
  end
59
 
60
end
61
 
62
//
63
//serial port buffer (transmit)
64
//
65
always @(posedge clk or posedge rst)
66
begin
67
  if (rst) begin
68
    sbuf_txd <= #1 `OC8051_RST_SBUF;
69 4 markom
    tr_start <= #1 1'b0;
70 2 simont
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
71
    sbuf_txd <= #1 data_in;
72
    tr_start <= #1 1'b1;
73 5 markom
  end else tr_start <= #1 1'b0;
74 2 simont
end
75
 
76
//
77
// transmit
78
//
79
always @(posedge clk or posedge rst)
80
begin
81
  if (rst) begin
82
    txd <= #1 1'b1;
83
    tr_count <= #1 4'd0;
84
    trans <= #1 1'b0;
85
    smod_cnt_t <= #1 1'b0;
86
//
87
// start transmiting
88
//
89
  end else if (tr_start) begin
90
    case (scon[7:6])
91
      2'b00: begin  // mode 0
92
        txd <= #1 sbuf_txd[0];
93
        tr_count <= #1 4'd1;
94
      end
95
      2'b10: begin
96
        txd <= #1 1'b0;
97
        tr_count <= #1 4'd0;
98
      end
99
      default: begin  // mode 1 and mode 3
100
        tr_count <= #1 4'b1111;
101
      end
102
    endcase
103
    trans <= #1 1'b1;
104
    smod_cnt_t <= #1 1'b0;
105
    mode2_count <= #1 3'b000;
106
//
107
// transmiting
108
//
109
  end else if (trans)
110
  begin
111
    case (scon[7:6])
112
      2'b00: begin //mode 0
113 4 markom
        if (tr_count==4'd8)
114 2 simont
        begin
115
          trans <= #1 1'b0;
116
          txd <= #1 1'b1;
117
        end else begin
118
          txd <= #1 sbuf_txd[tr_count];
119 4 markom
          tr_count <= #1 tr_count + 4'b1;
120 2 simont
        end
121
      end
122
      2'b01: begin // mode 1
123
        if ((t1_ow) & !(t1_ow_buf))
124
        begin
125
          if ((pcon[7]) | (smod_cnt_t))
126
          begin
127
            case (tr_count)
128
              4'd8: txd <= #1 1'b1;  // stop bit
129
              4'd9: trans <= #1 1'b0;
130
              4'b1111: txd <= #1 1'b0; //start bit
131
              default: txd <= #1 sbuf_txd[tr_count];
132
            endcase
133 4 markom
            tr_count <= #1 tr_count + 4'b1;
134 2 simont
            smod_cnt_t <= #1 1'b0;
135
          end else smod_cnt_t <= #1 1'b1;
136
        end
137
      end
138
      2'b10: begin // mode 2
139
//
140
// if smod (pcon[7]) is 1 count to 4 else count to 6
141
//
142
        if (((pcon[7]) & (mode2_count==3'b011)) | (!(pcon[7]) & (mode2_count==3'b101))) begin
143
          case (tr_count)
144
            4'd8: begin
145
              txd <= #1 scon[3];
146
            end
147
            4'd9: begin
148
              txd <= #1 1'b1; //stop bit
149
              trans <= #1 1'b0;
150
            end
151
            default: begin
152
              txd <= #1 sbuf_txd[tr_count];
153
            end
154
          endcase
155
          tr_count <= #1 tr_count+1'b1;
156 4 markom
          mode2_count <= #1 3'd0;
157 2 simont
        end else begin
158 4 markom
          mode2_count <= #1 mode2_count + 3'b1;
159 2 simont
        end
160
      end
161
      default: begin // mode 3
162
        if ((t1_ow) & !(t1_ow_buf))
163
        begin
164
          if ((pcon[7]) | (smod_cnt_t))
165
          begin
166
            case (tr_count)
167
              4'd8: begin
168
                txd <= #1 scon[3];
169
              end
170
              4'd9: begin
171
                txd <= #1 1'b1; //stop bit
172
              end
173
              4'd10: begin
174
          trans <= #1 1'b0;
175
        end
176
              4'b1111: txd <= #1 1'b0; //start bit
177
              default: begin
178
                txd <= #1 sbuf_txd[tr_count];
179
              end
180
            endcase
181
            tr_count <= #1 tr_count+1'b1;
182
            smod_cnt_t <= #1 1'b0;
183
          end else smod_cnt_t <= #1 1'b1;
184
        end
185
      end
186
    endcase
187
  end else
188
    txd <= #1 1'b1;
189
end
190
 
191
//
192
//power control register
193
//
194
always @(posedge clk or posedge rst)
195
begin
196
  if (rst)
197
  begin
198
    pcon <= #1 `OC8051_RST_PCON;
199
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
200
    pcon <= #1 data_in;
201
end
202
 
203
//
204 4 markom
//serial port buffer (receive)
205 2 simont
//
206
always @(posedge clk or posedge rst)
207
begin
208
  if (rst) begin
209
    sample <= #1 3'b000;
210
    sam_cnt <= #1 3'b000;
211
    re_count <= #1 4'd0;
212
    receive <= #1 1'b0;
213
    sbuf_rxd <= #1 8'h00;
214
    sbuf_rxd_tmp <= #1 11'd0;
215
    smod_cnt_r <= #1 1'b0;
216
    r_int <= #1 1'b0;
217
    re_start <= #1 1'b0;
218
  end else if (receive) begin
219
    case (scon[7:6])
220
      2'b00: begin // mode 0
221
        if (re_count==4'd8) begin
222
          receive <= #1 1'b0;
223
          r_int <= #1 1'b1;
224
          sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
225
        end else begin
226 5 markom
          sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
227 2 simont
          r_int <= #1 1'b0;
228
        end
229 5 markom
        re_count <= #1 re_count + 4'd1;
230 2 simont
      end
231
      2'b01: begin // mode 1
232
        if ((t1_ow) & !(t1_ow_buf))
233
        begin
234
          if ((pcon[7]) | (smod_cnt_r))
235
          begin
236
            sam_cnt <= #1 3'b000;
237
            r_int <= #1 1'b0;
238
 
239 5 markom
            re_count <= #1 re_count + 4'd1;
240 2 simont
            smod_cnt_r <= #1 1'b0;
241
          end else smod_cnt_r <= #1 1'b1;
242
        end else begin
243
          if (sam_cnt==3'b011) begin
244 10 markom
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
245 2 simont
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
246
            else
247
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
248 5 markom
            if (re_count == 4'd9)
249 2 simont
            begin
250
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
251
              receive <= #1 1'b0;
252
              r_int <= #1 1'b1;
253
            end else r_int <= #1 1'b0;
254
          end else begin
255
            sample[sam_cnt[1:0]] <= #1 rxd;
256
            sam_cnt <= #1 sam_cnt +1'b1;
257
            r_int <= #1 1'b0;
258
          end
259
        end
260
      end
261
      2'b10: begin // mode 2
262
        if (((pcon[7]) & (sam_cnt==3'b100)) | (!(pcon[7]) & (sam_cnt==3'b110))) begin
263
          if (re_count==4'd11) begin
264
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
265
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
266
              receive <= #1 1'b0;
267
          end else begin
268
            sam_cnt <= #1 3'b001;
269
            sample[0] <= #1 rxd;
270
            r_int <= #1 1'b0;
271
          end
272 5 markom
    re_count <= #1 re_count + 4'd1;
273 2 simont
        end else begin
274
          r_int <= #1 1'b0;
275
 
276
          if (sam_cnt==3'b011) begin
277 10 markom
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
278 2 simont
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
279
            else
280
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
281
          end else begin
282
            sample[sam_cnt[1:0]] <= #1 rxd;
283
          end
284
    sam_cnt <= #1 sam_cnt + 1'b1;
285
        end
286
      end
287
      default: begin // mode 3
288
        if ((t1_ow) & !(t1_ow_buf))
289
        begin
290
          if ((pcon[7]) | (smod_cnt_r))
291
          begin
292
            sam_cnt <= #1 3'b000;
293
 
294
            if (re_count==4'd11) begin
295
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
296
              receive <= #1 1'b0;
297
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
298
            end else begin
299
              sam_cnt <= #1 3'b000;
300
              r_int <= #1 1'b0;
301
            end
302
 
303 5 markom
            re_count <= #1 re_count + 4'd1;
304 2 simont
            smod_cnt_r <= #1 1'b0;
305
          end else smod_cnt_r <= #1 1'b1;
306
        end else begin
307
          r_int <= #1 1'b0;
308
          if (sam_cnt==3'b011)
309 10 markom
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
310 2 simont
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
311
            else
312
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
313
          else begin
314
            sample[sam_cnt[1:0]] <= #1 rxd;
315 10 markom
            sam_cnt <= #1 sam_cnt + 1'b1;
316 2 simont
          end
317
        end
318
      end
319
    endcase
320
  end else begin
321
    case (scon[7:6])
322
      2'b00: begin
323
        if ((scon[4]) & !(scon[0]) & !(r_int)) begin
324
          receive <= #1 1'b1;
325
        end
326
      end
327
      2'b10: begin
328
        if ((rxd_buf) & !(rxd)) begin
329
          receive <= #1 1'b1;
330
        end
331
      end
332
      default: begin
333
        if ((rxd_buf) & !(rxd)) begin
334
          re_start <= #1 1'b1;
335
        end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin
336
          re_start <= #1 1'b0;
337
          receive <= 1'b1;
338
        end
339
      end
340
    endcase
341
 
342
    sample <= #1 3'b000;
343
    sam_cnt <= #1 3'b000;
344
    re_count <= #1 4'd0;
345
    sbuf_rxd_tmp <= #1 11'd0;
346
    r_int <= #1 1'b0;
347
  end
348
end
349
 
350
//
351
//
352
//
353 4 markom
always @(posedge clk or posedge rst)
354 2 simont
begin
355 4 markom
  if (rst) data_out <= #1 8'h0;
356
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
357 2 simont
     (wr_addr==`OC8051_SFR_SCON))) begin
358
    data_out <= #1 data_in;
359
  end else begin
360
    case (rd_addr)
361
      `OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
362
      `OC8051_SFR_PCON: data_out <= #1 pcon;
363
      default: data_out <= #1 scon;
364
    endcase
365
  end
366
end
367
 
368
 
369 4 markom
always @(posedge clk or posedge rst)
370 2 simont
begin
371 4 markom
  if (rst) begin
372
    trans_buf <= #1 1'b0;
373
    receive_buf <= #1 1'b0;
374
    t1_ow_buf <= #1 1'b0;
375
    rxd_buf <= #1 1'b0;
376
  end else begin
377
    trans_buf <= #1 trans;
378
    receive_buf <= #1 receive;
379
    t1_ow_buf <= #1 t1_ow;
380
    rxd_buf <= #1 rxd;
381
  end
382 2 simont
end
383
 
384 4 markom
always  @(posedge clk or posedge rst)
385 2 simont
begin
386 4 markom
  if (rst) bit_out <= #1 1'b0;
387
  else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
388 2 simont
    bit_out <= #1 bit_in;
389
  end else
390
    bit_out <= #1 scon[rd_addr[2:0]];
391
end
392
 
393
endmodule

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