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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 36

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// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
                   rxd, txd, intr, t1_ow);
 
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
input [7:0] rd_addr, data_in, wr_addr;
 
output txd, intr, bit_out;
output [7:0] data_out;
 
reg txd, bit_out;
reg [7:0] data_out;
 
reg tr_start, trans, trans_buf, t1_ow_buf;
reg [5:0] smod_cnt_r, smod_cnt_t;
reg receive, receive_buf, rxd_buf, r_int;
//
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
reg [10:0] sbuf_rxd_tmp;
//
//tr_count      trancive counter
//re_count      receive counter
reg [3:0] tr_count, re_count, re_count_buff;
 
 
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if ((trans_buf) & !(trans))
    scon[1] <= #1 1'b1;
  else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
    case (scon[7:6])
      2'b00: scon[0] <= #1 1'b1;
      default: begin
        if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
        scon[2] <= #1 sbuf_rxd_tmp[9];
      end
    endcase
  end
 
end
 
//
//serial port buffer (transmit)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sbuf_txd <= #1 `OC8051_RST_SBUF;
    tr_start <= #1 1'b0;
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
    sbuf_txd <= #1 data_in;
    tr_start <= #1 1'b1;
  end else tr_start <= #1 1'b0;
end
 
//
// transmit
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans <= #1 1'b0;
    smod_cnt_t <= #1 6'h0;
//
// start transmiting
//
  end else if (tr_start) begin
    case (scon[7:6])
      2'b00: begin  // mode 0
        txd <= #1 sbuf_txd[0];
        tr_count <= #1 4'd1;
      end
      2'b10: begin
        txd <= #1 1'b0;
        tr_count <= #1 4'd0;
      end
      default: begin  // mode 1 and mode 3
        tr_count <= #1 4'b1111;
      end
    endcase
    trans <= #1 1'b1;
    smod_cnt_t <= #1 6'h0;
//
// transmiting/
//
  end else if (trans)
  begin
    case (scon[7:6])
      2'b00: begin //mode 0
        if (smod_cnt_t == 6'd12) begin
          if (tr_count==4'd8)
          begin
                  trans <= #1 1'b0;
                  txd <= #1 1'b1;
                end else begin
            txd <= #1 sbuf_txd[tr_count];
                  tr_count <= #1 tr_count + 4'b1;
                end
          smod_cnt_t <= #1 6'h0;
              end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
                if (((pcon[7]) &  (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
                begin
            case (tr_count)
              4'd8: txd <= #1 1'b1;  // stop bit
                    4'd9: trans <= #1 1'b0;
                    4'b1111: txd <= #1 1'b0; //start bit
                    default: txd <= #1 sbuf_txd[tr_count];
                  endcase
            tr_count <= #1 tr_count + 4'b1;
                  smod_cnt_t <= #1 6'h0;
                end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
              end
      end
      2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
        if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
            case (tr_count)
            4'd8: begin
                    txd <= #1 scon[3];
                  end
            4'd9: begin
                    txd <= #1 1'b1; //stop bit
                  end
            4'd10: begin
                    trans <= #1 1'b0;
                  end
 
                  default: begin
                    txd <= #1 sbuf_txd[tr_count];
                  end
                endcase
          tr_count <= #1 tr_count+1'b1;
                smod_cnt_t <= #1 6'h00;
              end else begin
          smod_cnt_t <= #1 smod_cnt_t + 6'h01;
              end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
      if (((pcon[7]) &  (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
          begin
            case (tr_count)
              4'd8: begin
                txd <= #1 scon[3];
              end
              4'd9: begin
                txd <= #1 1'b1; //stop bit
              end
              4'd10: begin
          trans <= #1 1'b0;
        end
              4'b1111: txd <= #1 1'b0; //start bit
              default: begin
                txd <= #1 sbuf_txd[tr_count];
              end
            endcase
            tr_count <= #1 tr_count+1'b1;
            smod_cnt_t <= #1 6'h00;
          end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
        end
      end
    endcase
  end else
    txd <= #1 1'b1;
end
 
//
//power control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    re_count <= #1 4'd0;
    receive <= #1 1'b0;
    sbuf_rxd <= #1 8'h00;
    sbuf_rxd_tmp <= #1 11'd0;
    smod_cnt_r <= #1 6'h00;
    r_int <= #1 1'b0;
  end else if (receive) begin
    case (scon[7:6])
      2'b00: begin // mode 0
        if (smod_cnt_r==6'd12) begin
          if (re_count==4'd8) begin
                  receive <= #1 1'b0;
                  r_int <= #1 1'b1;
                  sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              end else begin
            sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
                  r_int <= #1 1'b0;
                end
          re_count <= #1 re_count + 4'd1;
          smod_cnt_r <= #1 6'h00;
        end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if (((pcon[7]) &  (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
                begin
            r_int <= #1 1'b0;
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 6'h00;
            sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
            if ((re_count==4'd0) && (rxd))
              receive <= #1 1'b0;
 
                end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
              end else begin
              r_int <= #1 1'b1;
            if (re_count == 4'd10)
          begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
            receive <= #1 1'b0;
              r_int <= #1 1'b1;
          end else r_int <= #1 1'b0;
        end
      end
      2'b10: begin // mode 2
        if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
          r_int <= #1 1'b0;
            re_count <= #1 re_count + 4'd1;
          smod_cnt_r <= #1 6'h00;
          sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
          re_count <= #1 re_count + 4'd1;
              end else begin
          smod_cnt_r <= #1 smod_cnt_r + 6'h1;
                if (re_count==4'd11) begin
                  sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
                  r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
                  receive <= #1 1'b0;
                end else
                  r_int <= #1 1'b0;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if (((pcon[7]) &  (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
                begin
            sbuf_rxd_tmp[re_count] <= #1 rxd;
                  r_int <= #1 1'b0;
                re_count <= #1 re_count + 4'd1;
                  smod_cnt_r <= #1 6'h00;
                end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
              end else begin
          if (re_count==4'd11) begin
            sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
            receive <= #1 1'b0;
                  r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
                end else begin
            r_int <= #1 1'b0;
          end
              end
      end
    endcase
  end else begin
    case (scon[7:6])
      2'b00: begin
        if ((scon[4]) && !(scon[0]) && !(r_int)) begin
          receive <= #1 1'b1;
          smod_cnt_r <= #1 6'h6;
        end
      end
      2'b10: begin
        if ((scon[4]) && !(rxd)) begin
          receive <= #1 1'b1;
          if (pcon[7])
            smod_cnt_r <= #1 6'd15;
          else smod_cnt_r <= #1 6'd31;
        end
      end
      default: begin
        if ((scon[4]) && (!rxd)) begin
          if (pcon[7])
            smod_cnt_r <= #1 6'd7;
          else smod_cnt_r <= #1 6'd15;
          receive <= #1 1'b1;
        end
      end
    endcase
 
    sbuf_rxd_tmp <= #1 11'd0;
    re_count <= #1 4'd0;
    r_int <= #1 1'b0;
  end
end
 
//
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
     (wr_addr==`OC8051_SFR_SCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
      `OC8051_SFR_PCON: data_out <= #1 pcon;
      default: data_out <= #1 scon;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    trans_buf <= #1 1'b0;
    receive_buf <= #1 1'b0;
    t1_ow_buf <= #1 1'b0;
    rxd_buf <= #1 1'b0;
  end else begin
    trans_buf <= #1 trans;
    receive_buf <= #1 receive;
    t1_ow_buf <= #1 t1_ow;
    rxd_buf <= #1 rxd;
  end
end
 
always  @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
    bit_out <= #1 bit_in;
  end else
    bit_out <= #1 scon[rd_addr[2:0]];
end
 
always @(posedge clk or posedge rst)
  if (rst)
    re_count_buff <= #1 4'h4;
  else re_count_buff <= #1 re_count;
 
endmodule
 

Line No.	Rev	Author	Line
1	8	markom	`// synopsys translate_off`
2			`include "oc8051_timescale.v"
3			`// synopsys translate_on`
4
5			`include "oc8051_defines.v"
6
7	2	simont	`module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,`
8	4	markom	`rxd, txd, intr, t1_ow);`
9	2	simont
10			`input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;`
11			`input [7:0] rd_addr, data_in, wr_addr;`
12
13	4	markom	`output txd, intr, bit_out;`
14	2	simont	`output [7:0] data_out;`
15
16			`reg txd, bit_out;`
17			`reg [7:0] data_out;`
18
19	30	simont	`reg tr_start, trans, trans_buf, t1_ow_buf;`
20			`reg [5:0] smod_cnt_r, smod_cnt_t;`
21	2	simont	`reg receive, receive_buf, rxd_buf, r_int;`
22			`//`
23			`reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;`
24			`reg [10:0] sbuf_rxd_tmp;`
25			`//`
26			`//tr_count trancive counter`
27			`//re_count receive counter`
28	30	simont	`reg [3:0] tr_count, re_count, re_count_buff;`
29	2	simont
30
31	4	markom	`assign intr = scon[1] \| scon [0];`
32	2	simont
33			`//`
34			`//serial port control register`
35			`//`
36			`always @(posedge clk or posedge rst)`
37			`begin`
38			`if (rst)`
39			scon <= #1 `OC8051_RST_SCON;
40			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
41			`scon <= #1 data_in;`
42			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
43			`scon[wr_addr[2:0]] <= #1 bit_in;`
44			`else if ((trans_buf) & !(trans))`
45			`scon[1] <= #1 1'b1;`
46			`else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin`
47			`case (scon[7:6])`
48			`2'b00: scon[0] <= #1 1'b1;`
49			`default: begin`
50			`if ((sbuf_rxd_tmp[9]) \| !(scon[5])) scon[0] <= #1 1'b1;`
51			`scon[2] <= #1 sbuf_rxd_tmp[9];`
52			`end`
53			`endcase`
54			`end`
55
56			`end`
57
58			`//`
59			`//serial port buffer (transmit)`
60			`//`
61			`always @(posedge clk or posedge rst)`
62			`begin`
63			`if (rst) begin`
64			sbuf_txd <= #1 `OC8051_RST_SBUF;
65	4	markom	`tr_start <= #1 1'b0;`
66	2	simont	end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
67			`sbuf_txd <= #1 data_in;`
68			`tr_start <= #1 1'b1;`
69	5	markom	`end else tr_start <= #1 1'b0;`
70	2	simont	`end`
71
72			`//`
73			`// transmit`
74			`//`
75			`always @(posedge clk or posedge rst)`
76			`begin`
77			`if (rst) begin`
78			`txd <= #1 1'b1;`
79			`tr_count <= #1 4'd0;`
80			`trans <= #1 1'b0;`
81	30	simont	`smod_cnt_t <= #1 6'h0;`
82	2	simont	`//`
83			`// start transmiting`
84			`//`
85			`end else if (tr_start) begin`
86			`case (scon[7:6])`
87			`2'b00: begin // mode 0`
88			`txd <= #1 sbuf_txd[0];`
89			`tr_count <= #1 4'd1;`
90			`end`
91			`2'b10: begin`
92			`txd <= #1 1'b0;`
93			`tr_count <= #1 4'd0;`
94			`end`
95			`default: begin // mode 1 and mode 3`
96			`tr_count <= #1 4'b1111;`
97			`end`
98			`endcase`
99			`trans <= #1 1'b1;`
100	30	simont	`smod_cnt_t <= #1 6'h0;`
101	2	simont	`//`
102	30	simont	`// transmiting/`
103	2	simont	`//`
104			`end else if (trans)`
105			`begin`
106			`case (scon[7:6])`
107			`2'b00: begin //mode 0`
108	36	simont	`if (smod_cnt_t == 6'd12) begin`
109			`if (tr_count==4'd8)`
110			`begin`
111			`trans <= #1 1'b0;`
112			`txd <= #1 1'b1;`
113			`end else begin`
114			`txd <= #1 sbuf_txd[tr_count];`
115			`tr_count <= #1 tr_count + 4'b1;`
116			`end`
117			`smod_cnt_t <= #1 6'h0;`
118			`end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
119	2	simont	`end`
120			`2'b01: begin // mode 1`
121			`if ((t1_ow) & !(t1_ow_buf))`
122	30	simont	`begin`
123			`if (((pcon[7]) & (smod_cnt_t == 6'd15))\| (!(pcon[7]) & (smod_cnt_t==6'd31)))`
124			`begin`
125	2	simont	`case (tr_count)`
126			`4'd8: txd <= #1 1'b1; // stop bit`
127	30	simont	`4'd9: trans <= #1 1'b0;`
128			`4'b1111: txd <= #1 1'b0; //start bit`
129			`default: txd <= #1 sbuf_txd[tr_count];`
130			`endcase`
131	4	markom	`tr_count <= #1 tr_count + 4'b1;`
132	30	simont	`smod_cnt_t <= #1 6'h0;`
133			`end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
134			`end`
135	2	simont	`end`
136			`2'b10: begin // mode 2`
137			`//`
138			`// if smod (pcon[7]) is 1 count to 4 else count to 6`
139			`//`
140	30	simont	`if (((pcon[7]) & (smod_cnt_t==6'd31)) \| (!(pcon[7]) & (smod_cnt_t==6'd63))) begin`
141			`case (tr_count)`
142	2	simont	`4'd8: begin`
143	30	simont	`txd <= #1 scon[3];`
144			`end`
145	2	simont	`4'd9: begin`
146	30	simont	`txd <= #1 1'b1; //stop bit`
147			`end`
148			`4'd10: begin`
149			`trans <= #1 1'b0;`
150			`end`
151
152			`default: begin`
153			`txd <= #1 sbuf_txd[tr_count];`
154			`end`
155			`endcase`
156	2	simont	`tr_count <= #1 tr_count+1'b1;`
157	30	simont	`smod_cnt_t <= #1 6'h00;`
158			`end else begin`
159			`smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
160			`end`
161	2	simont	`end`
162			`default: begin // mode 3`
163			`if ((t1_ow) & !(t1_ow_buf))`
164			`begin`
165	30	simont	`if (((pcon[7]) & (smod_cnt_t == 6'd15))\| (!(pcon[7]) & (smod_cnt_t==6'd31)))`
166	2	simont	`begin`
167			`case (tr_count)`
168			`4'd8: begin`
169			`txd <= #1 scon[3];`
170			`end`
171			`4'd9: begin`
172			`txd <= #1 1'b1; //stop bit`
173			`end`
174			`4'd10: begin`
175			`trans <= #1 1'b0;`
176			`end`
177			`4'b1111: txd <= #1 1'b0; //start bit`
178			`default: begin`
179			`txd <= #1 sbuf_txd[tr_count];`
180			`end`
181			`endcase`
182			`tr_count <= #1 tr_count+1'b1;`
183	30	simont	`smod_cnt_t <= #1 6'h00;`
184			`end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
185	2	simont	`end`
186			`end`
187			`endcase`
188			`end else`
189			`txd <= #1 1'b1;`
190			`end`
191
192			`//`
193			`//power control register`
194			`//`
195			`always @(posedge clk or posedge rst)`
196			`begin`
197			`if (rst)`
198			`begin`
199			pcon <= #1 `OC8051_RST_PCON;
200			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
201			`pcon <= #1 data_in;`
202			`end`
203
204			`//`
205	4	markom	`//serial port buffer (receive)`
206	2	simont	`//`
207			`always @(posedge clk or posedge rst)`
208			`begin`
209			`if (rst) begin`
210			`re_count <= #1 4'd0;`
211			`receive <= #1 1'b0;`
212			`sbuf_rxd <= #1 8'h00;`
213			`sbuf_rxd_tmp <= #1 11'd0;`
214	30	simont	`smod_cnt_r <= #1 6'h00;`
215	2	simont	`r_int <= #1 1'b0;`
216			`end else if (receive) begin`
217			`case (scon[7:6])`
218			`2'b00: begin // mode 0`
219	36	simont	`if (smod_cnt_r==6'd12) begin`
220			`if (re_count==4'd8) begin`
221			`receive <= #1 1'b0;`
222			`r_int <= #1 1'b1;`
223			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
224			`end else begin`
225			`sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;`
226			`r_int <= #1 1'b0;`
227			`end`
228			`re_count <= #1 re_count + 4'd1;`
229			`smod_cnt_r <= #1 6'h00;`
230			`end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;`
231	2	simont	`end`
232			`2'b01: begin // mode 1`
233			`if ((t1_ow) & !(t1_ow_buf))`
234	30	simont	`begin`
235			`if (((pcon[7]) & (smod_cnt_r == 6'd15))\| (!(pcon[7]) & (smod_cnt_r==6'd31)))`
236			`begin`
237	2	simont	`r_int <= #1 1'b0;`
238	30	simont	`re_count <= #1 re_count + 4'd1;`
239			`smod_cnt_r <= #1 6'h00;`
240			`sbuf_rxd_tmp[re_count_buff] <= #1 rxd;`
241			`if ((re_count==4'd0) && (rxd))`
242			`receive <= #1 1'b0;`
243	2	simont
244	30	simont	`end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;`
245			`end else begin`
246			`r_int <= #1 1'b1;`
247			`if (re_count == 4'd10)`
248			`begin`
249			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
250			`receive <= #1 1'b0;`
251			`r_int <= #1 1'b1;`
252			`end else r_int <= #1 1'b0;`
253			`end`
254	2	simont	`end`
255			`2'b10: begin // mode 2`
256	30	simont	`if (((pcon[7]) & (smod_cnt_r==6'd31)) \| (!(pcon[7]) & (smod_cnt_r==6'd63))) begin`
257			`r_int <= #1 1'b0;`
258			`re_count <= #1 re_count + 4'd1;`
259			`smod_cnt_r <= #1 6'h00;`
260			`sbuf_rxd_tmp[re_count_buff] <= #1 rxd;`
261			`re_count <= #1 re_count + 4'd1;`
262			`end else begin`
263			`smod_cnt_r <= #1 smod_cnt_r + 6'h1;`
264			`if (re_count==4'd11) begin`
265			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
266			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
267			`receive <= #1 1'b0;`
268			`end else`
269			`r_int <= #1 1'b0;`
270			`end`
271	2	simont	`end`
272			`default: begin // mode 3`
273			`if ((t1_ow) & !(t1_ow_buf))`
274	30	simont	`begin`
275			`if (((pcon[7]) & (smod_cnt_r == 6'd15))\| (!(pcon[7]) & (smod_cnt_r==6'd31)))`
276			`begin`
277			`sbuf_rxd_tmp[re_count] <= #1 rxd;`
278			`r_int <= #1 1'b0;`
279			`re_count <= #1 re_count + 4'd1;`
280			`smod_cnt_r <= #1 6'h00;`
281			`end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;`
282			`end else begin`
283			`if (re_count==4'd11) begin`
284			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
285			`receive <= #1 1'b0;`
286			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
287			`end else begin`
288			`r_int <= #1 1'b0;`
289			`end`
290			`end`
291	2	simont	`end`
292			`endcase`
293			`end else begin`
294			`case (scon[7:6])`
295			`2'b00: begin`
296	30	simont	`if ((scon[4]) && !(scon[0]) && !(r_int)) begin`
297	2	simont	`receive <= #1 1'b1;`
298	36	simont	`smod_cnt_r <= #1 6'h6;`
299	2	simont	`end`
300			`end`
301			`2'b10: begin`
302	30	simont	`if ((scon[4]) && !(rxd)) begin`
303	2	simont	`receive <= #1 1'b1;`
304	30	simont	`if (pcon[7])`
305			`smod_cnt_r <= #1 6'd15;`
306			`else smod_cnt_r <= #1 6'd31;`
307	2	simont	`end`
308			`end`
309			`default: begin`
310	30	simont	`if ((scon[4]) && (!rxd)) begin`
311			`if (pcon[7])`
312			`smod_cnt_r <= #1 6'd7;`
313			`else smod_cnt_r <= #1 6'd15;`
314			`receive <= #1 1'b1;`
315	2	simont	`end`
316			`end`
317			`endcase`
318
319	30	simont	`sbuf_rxd_tmp <= #1 11'd0;`
320	2	simont	`re_count <= #1 4'd0;`
321			`r_int <= #1 1'b0;`
322			`end`
323			`end`
324
325			`//`
326			`//`
327			`//`
328	4	markom	`always @(posedge clk or posedge rst)`
329	2	simont	`begin`
330	4	markom	`if (rst) data_out <= #1 8'h0;`
331			else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) \|
332	2	simont	(wr_addr==`OC8051_SFR_SCON))) begin
333			`data_out <= #1 data_in;`
334			`end else begin`
335			`case (rd_addr)`
336			`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
337			`OC8051_SFR_PCON: data_out <= #1 pcon;
338			`default: data_out <= #1 scon;`
339			`endcase`
340			`end`
341			`end`
342
343
344	4	markom	`always @(posedge clk or posedge rst)`
345	2	simont	`begin`
346	4	markom	`if (rst) begin`
347			`trans_buf <= #1 1'b0;`
348			`receive_buf <= #1 1'b0;`
349			`t1_ow_buf <= #1 1'b0;`
350			`rxd_buf <= #1 1'b0;`
351			`end else begin`
352			`trans_buf <= #1 trans;`
353			`receive_buf <= #1 receive;`
354			`t1_ow_buf <= #1 t1_ow;`
355			`rxd_buf <= #1 rxd;`
356			`end`
357	2	simont	`end`
358
359	4	markom	`always @(posedge clk or posedge rst)`
360	2	simont	`begin`
361	4	markom	`if (rst) bit_out <= #1 1'b0;`
362			else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
363	2	simont	`bit_out <= #1 bit_in;`
364			`end else`
365			`bit_out <= #1 scon[rd_addr[2:0]];`
366			`end`
367
368	30	simont	`always @(posedge clk or posedge rst)`
369			`if (rst)`
370			`re_count_buff <= #1 4'h4;`
371			`else re_count_buff <= #1 re_count;`
372
373	2	simont	`endmodule`
374	30	simont

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 36