1 |
70 |
simont |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// 8051 data ram ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// This file is part of the 8051 cores project ////
|
6 |
|
|
//// http://www.opencores.org/cores/8051/ ////
|
7 |
|
|
//// ////
|
8 |
|
|
//// Description ////
|
9 |
|
|
//// data ram for virtex ////
|
10 |
|
|
//// ////
|
11 |
|
|
//// To Do: ////
|
12 |
|
|
//// nothing ////
|
13 |
|
|
//// ////
|
14 |
|
|
//// Author(s): ////
|
15 |
|
|
//// - Simon Teran, simont@opencores.org ////
|
16 |
|
|
//// ////
|
17 |
|
|
//////////////////////////////////////////////////////////////////////
|
18 |
|
|
//// ////
|
19 |
|
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
20 |
|
|
//// ////
|
21 |
|
|
//// This source file may be used and distributed without ////
|
22 |
|
|
//// restriction provided that this copyright statement is not ////
|
23 |
|
|
//// removed from the file and that any derivative work contains ////
|
24 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
25 |
|
|
//// ////
|
26 |
|
|
//// This source file is free software; you can redistribute it ////
|
27 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
28 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
29 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
30 |
|
|
//// later version. ////
|
31 |
|
|
//// ////
|
32 |
|
|
//// This source is distributed in the hope that it will be ////
|
33 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
34 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
35 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
36 |
|
|
//// details. ////
|
37 |
|
|
//// ////
|
38 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
39 |
|
|
//// Public License along with this source; if not, download it ////
|
40 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
41 |
|
|
//// ////
|
42 |
|
|
//////////////////////////////////////////////////////////////////////
|
43 |
|
|
//
|
44 |
|
|
// CVS Revision History
|
45 |
|
|
//
|
46 |
|
|
// $Log: not supported by cvs2svn $
|
47 |
|
|
// Revision 1.2 2002/09/30 17:34:02 simont
|
48 |
|
|
// prepared header
|
49 |
|
|
//
|
50 |
|
|
//
|
51 |
|
|
|
52 |
|
|
// synopsys translate_off
|
53 |
|
|
`include "oc8051_timescale.v"
|
54 |
|
|
// synopsys translate_on
|
55 |
|
|
module oc8051_cache_ram (clk, rst, addr0, data0, addr1, data1_i, data1_o, wr1);
|
56 |
|
|
//
|
57 |
|
|
// this module is part of oc8051_icache
|
58 |
|
|
// it's tehnology dependent
|
59 |
|
|
//
|
60 |
|
|
// clk (in) clock
|
61 |
|
|
// addr0 (in) addres port 0
|
62 |
|
|
// data0 (out) data output port 0
|
63 |
|
|
// addr1 (in) address port 1
|
64 |
|
|
// data1_i (in) data input port 1
|
65 |
|
|
// data1_o (out) data output port 1
|
66 |
|
|
// wr1 (in) write port 1
|
67 |
|
|
//
|
68 |
|
|
|
69 |
|
|
parameter ADR_WIDTH = 7; // cache address wihth
|
70 |
|
|
parameter CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
|
71 |
|
|
|
72 |
|
|
input clk, wr1, rst;
|
73 |
|
|
input [ADR_WIDTH-1:0] addr0, addr1;
|
74 |
|
|
input [31:0] data1_i;
|
75 |
|
|
output [31:0] data0, data1_o;
|
76 |
|
|
|
77 |
|
|
|
78 |
|
|
//
|
79 |
|
|
|
80 |
|
|
|
81 |
|
|
wire [7:0] dob;
|
82 |
|
|
RAMB4_S8_S8 ram1(.DOA(data0), .DOB(data1_o), .ADDRA({1'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
|
83 |
|
|
.RSTA(rst), .ADDRB({1'b0, addr1}), .DIB(data1_i), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
|
84 |
|
|
|
85 |
|
|
|
86 |
|
|
endmodule
|