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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [sim/] [rtl_sim/] [run/] [make_verilog] - Blame information for rev 185

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Line No. Rev Author Line
1 100 simont 
verilog                                                 \
2 
../../../bench/verilog/oc8051_tb.v                      \
3 
../../../bench/verilog/oc8051_xram.v                    \
4 
../../../bench/verilog/oc8051_uart_test.v               \
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../../../bench/verilog/oc8051_xrom.v                    \
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../../../rtl/verilog/oc8051_top.v                       \
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../../../rtl/verilog/oc8051_alu_src_sel.v               \
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../../../rtl/verilog/oc8051_alu.v                       \
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../../../rtl/verilog/oc8051_decoder.v                   \
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../../../rtl/verilog/oc8051_divide.v                    \
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../../../rtl/verilog/oc8051_multiply.v                  \
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../../../rtl/verilog/oc8051_memory_interface.v          \
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../../../rtl/verilog/oc8051_ram_top.v                   \
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../../../rtl/verilog/oc8051_acc.v                       \
15 
../../../rtl/verilog/oc8051_comp.v                      \
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../../../rtl/verilog/oc8051_sp.v                        \
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../../../rtl/verilog/oc8051_dptr.v                      \
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../../../rtl/verilog/oc8051_cy_select.v                 \
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../../../rtl/verilog/oc8051_psw.v                       \
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../../../rtl/verilog/oc8051_indi_addr.v                 \
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../../../rtl/verilog/oc8051_ports.v                     \
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../../../rtl/verilog/oc8051_b_register.v                \
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../../../rtl/verilog/oc8051_uart.v                      \
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../../../rtl/verilog/oc8051_int.v                       \
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../../../rtl/verilog/oc8051_tc.v                        \
26 
../../../rtl/verilog/oc8051_tc2.v                       \
27 
../../../rtl/verilog/oc8051_icache.v                    \
28 
../../../rtl/verilog/oc8051_wb_iinterface.v             \
29 
../../../rtl/verilog/oc8051_sfr.v                       \
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../../../rtl/verilog/oc8051_rom.v                       \
31 
../../../rtl/verilog/oc8051_cache_ram.v                 \
32 106 simont 
../../../../common/generic_memories/rtl/verilog/generic_dpram.v

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