URL
https://opencores.org/ocsvn/8051/8051/trunk
Go to most recent revision |
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
83 |
simont |
verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_memory_interface.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../sim/rtl_sim/src/verilog/oc8051_xram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../../../sim/rtl_sim/src/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_tc2.v ../../../rtl/verilog/oc8051_icache.v ../../../sim/rtl_sim/src/verilog/oc8051_cache_ram.v ../../../rtl/verilog/oc8051_wb_iinterface.v ../../../rtl/verilog/oc8051_sfr.v
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.