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//////////////////////////////////////////////////////////////////////
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//// ////
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//// 8051 cores Definitions ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// Description ////
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//// 8051 definitions. ////
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//// ////
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//// To Do: ////
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//// Nothing ////
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//// ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Jaka Simsic, jakas@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// ver: 1
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//
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//
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// operation codes for alu
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//
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`define OC8051_ALU_NOP 4'b0000
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`define OC8051_ALU_ADD 4'b0001
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`define OC8051_ALU_SUB 4'b0010
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`define OC8051_ALU_MUL 4'b0011
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`define OC8051_ALU_DIV 4'b0100
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`define OC8051_ALU_DA 4'b0101
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`define OC8051_ALU_NOT 4'b0110
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`define OC8051_ALU_AND 4'b0111
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`define OC8051_ALU_XOR 4'b1000
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`define OC8051_ALU_OR 4'b1001
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`define OC8051_ALU_RL 4'b1010
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`define OC8051_ALU_RLC 4'b1011
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`define OC8051_ALU_RR 4'b1100
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`define OC8051_ALU_RRC 4'b1101
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`define OC8051_ALU_PCS 4'b1110
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`define OC8051_ALU_XCH 4'b1111
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//
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// sfr addresses
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//
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`define OC8051_SFR_ACC 8'he0 //accumulator
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`define OC8051_SFR_B 8'hf0 //b register
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`define OC8051_SFR_PSW 8'hd0 //program status word
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`define OC8051_SFR_P0 8'h80 //port 0
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`define OC8051_SFR_P1 8'h90 //port 1
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`define OC8051_SFR_P2 8'ha0 //port 2
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`define OC8051_SFR_P3 8'hb0 //port 3
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`define OC8051_SFR_DPTR_LO 8'h82 // data pointer high bits
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`define OC8051_SFR_DPTR_HI 8'h83 // data pointer low bits
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`define OC8051_SFR_IP 8'hb8 // interrupt priority control
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`define OC8051_SFR_IE 8'ha8 // interrupt enable control
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`define OC8051_SFR_TMOD 8'h89 // timer/counter mode
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`define OC8051_SFR_TCON 8'h88 // timer/counter control
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`define OC8051_SFR_TH0 8'h8c // timer/counter 0 high bits
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`define OC8051_SFR_TL0 8'h8a // timer/counter 0 low bits
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`define OC8051_SFR_TH1 8'h8d // timer/counter 1 high bits
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`define OC8051_SFR_TL1 8'h8b // timer/counter 1 low bits
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`define OC8051_SFR_SCON 8'h98 // serial control
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`define OC8051_SFR_SBUF 8'h99 // serial data buffer
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`define OC8051_SFR_PCON 8'h87 // power control
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`define OC8051_SFR_SP 8'h81 // stack pointer
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//
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// sfr bit addresses
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//
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`define OC8051_SFR_B_ACC 5'b11100 //accumulator
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`define OC8051_SFR_B_PSW 5'b11010 //program status word
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`define OC8051_SFR_B_P0 5'b10000 //port 0
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`define OC8051_SFR_B_P1 5'b10010 //port 1
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`define OC8051_SFR_B_P2 5'b10100 //port 2
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`define OC8051_SFR_B_P3 5'b10110 //port 3
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`define OC8051_SFR_B_B 5'b11110 // b register
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`define OC8051_SFR_B_IP 5'b10111 // interrupt priority control
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`define OC8051_SFR_B_IE 5'b10101 // interrupt enable control
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`define OC8051_SFR_B_SCON 5'b10011 // serial control
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`define OC8051_SFR_B_TCON 5'b10001 // timer/counter control
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//
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// alu source select
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//
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`define OC8051_ASS_RAM 2'b00 // RAM
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`define OC8051_ASS_ACC 2'b01 // accumulator
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`define OC8051_ASS_XRAM 2'b10 // external RAM -- source1
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`define OC8051_ASS_ZERO 2'b10 // 8'h00 -- source2
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`define OC8051_ASS_IMM 2'b11 // immediate data -- source1
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`define OC8051_ASS_DC 2'b00 //
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//
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// alu source 3 select
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//
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`define OC8051_AS3_PC 1'b1 // program clunter
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`define OC8051_AS3_DP 1'b0 // data pointer
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`define OC8051_AS3_DC 1'b0 //
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//
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//carry input in alu
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//
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`define OC8051_CY_0 2'b00 // 1'b0;
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`define OC8051_CY_PSW 2'b01 // carry from psw
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`define OC8051_CY_RAM 2'b10 // carry from ram
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`define OC8051_CY_1 2'b11 // 1'b1;
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`define OC8051_CY_DC 2'b00 // carry from psw
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//
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// instruction set
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//
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//op_code [4:0]
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`define OC8051_ACALL 8'bxxx1_0001 // absolute call
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`define OC8051_AJMP 8'bxxx0_0001 // absolute jump
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//op_code [7:3]
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`define OC8051_ADD_R 8'b0010_1xxx // add A=A+Rx
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`define OC8051_ADDC_R 8'b0011_1xxx // add A=A+Rx+c
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`define OC8051_ANL_R 8'b0101_1xxx // and A=A^Rx
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`define OC8051_CJNE_R 8'b1011_1xxx // compare and jump if not equal; Rx<>constant
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`define OC8051_DEC_R 8'b0001_1xxx // decrement reg Rn=Rn-1
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`define OC8051_DJNZ_R 8'b1101_1xxx // decrement and jump if not zero
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`define OC8051_INC_R 8'b0000_1xxx // increment Rn
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`define OC8051_MOV_R 8'b1110_1xxx // move A=Rn
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`define OC8051_MOV_AR 8'b1111_1xxx // move Rn=A
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`define OC8051_MOV_DR 8'b1010_1xxx // move Rn=(direct)
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`define OC8051_MOV_CR 8'b0111_1xxx // move Rn=constant
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`define OC8051_MOV_RD 8'b1000_1xxx // move (direct)=Rn
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`define OC8051_ORL_R 8'b0100_1xxx // or A=A or Rn
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`define OC8051_SUBB_R 8'b1001_1xxx // substract with borrow A=A-c-Rn
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`define OC8051_XCH_R 8'b1100_1xxx // exchange A<->Rn
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`define OC8051_XRL_R 8'b0110_1xxx // XOR A=A XOR Rn
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//op_code [7:1]
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`define OC8051_ADD_I 8'b0010_011x // add A=A+@Ri
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`define OC8051_ADDC_I 8'b0011_011x // add A=A+@Ri+c
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`define OC8051_ANL_I 8'b0101_011x // and A=A^@Ri
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`define OC8051_CJNE_I 8'b1011_011x // compare and jump if not equal; @Ri<>constant
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`define OC8051_DEC_I 8'b0001_011x // decrement indirect @Ri=@Ri-1
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`define OC8051_INC_I 8'b0000_011x // increment @Ri
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`define OC8051_MOV_I 8'b1110_011x // move A=@Ri
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`define OC8051_MOV_ID 8'b1000_011x // move (direct)=@Ri
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`define OC8051_MOV_AI 8'b1111_011x // move @Ri=A
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`define OC8051_MOV_DI 8'b1010_011x // move @Ri=(direct)
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`define OC8051_MOV_CI 8'b0111_011x // move @Ri=constant
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`define OC8051_MOVX_IA 8'b1110_001x // move A=(@Ri)
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`define OC8051_MOVX_AI 8'b1111_001x // move (@Ri)=A
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`define OC8051_ORL_I 8'b0100_011x // or A=A or @Ri
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`define OC8051_SUBB_I 8'b1001_011x // substract with borrow A=A-c-@Ri
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`define OC8051_XCH_I 8'b1100_011x // exchange A<->@Ri
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`define OC8051_XCHD 8'b1101_011x // exchange digit A<->Ri
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`define OC8051_XRL_I 8'b0110_011x // XOR A=A XOR @Ri
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//op_code [7:0]
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`define OC8051_ADD_D 8'b0010_0101 // add A=A+(direct)
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`define OC8051_ADD_C 8'b0010_0100 // add A=A+constant
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`define OC8051_ADDC_D 8'b0011_0101 // add A=A+(direct)+c
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`define OC8051_ADDC_C 8'b0011_0100 // add A=A+constant+c
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`define OC8051_ANL_D 8'b0101_0101 // and A=A^(direct)
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`define OC8051_ANL_C 8'b0101_0100 // and A=A^constant
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`define OC8051_ANL_DD 8'b0101_0010 // and (direct)=(direct)^A
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`define OC8051_ANL_DC 8'b0101_0011 // and (direct)=(direct)^constant
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`define OC8051_ANL_B 8'b1000_0010 // and c=c^bit
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`define OC8051_ANL_NB 8'b1011_0000 // and c=c^!bit
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`define OC8051_CJNE_D 8'b1011_0101 // compare and jump if not equal; a<>(direct)
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`define OC8051_CJNE_C 8'b1011_0100 // compare and jump if not equal; a<>constant
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`define OC8051_CLR_A 8'b1110_0100 // clear accumulator
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`define OC8051_CLR_C 8'b1100_0011 // clear carry
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`define OC8051_CLR_B 8'b1100_0010 // clear bit
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`define OC8051_CPL_A 8'b1111_0100 // complement accumulator
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`define OC8051_CPL_C 8'b1011_0011 // complement carry
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`define OC8051_CPL_B 8'b1011_0010 // complement bit
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`define OC8051_DA 8'b1101_0100 // decimal adjust (A)
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`define OC8051_DEC_A 8'b0001_0100 // decrement accumulator a=a-1
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`define OC8051_DEC_D 8'b0001_0101 // decrement direct (direct)=(direct)-1
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`define OC8051_DIV 8'b1000_0100 // divide
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`define OC8051_DJNZ_D 8'b1101_0101 // decrement and jump if not zero (direct)
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`define OC8051_INC_A 8'b0000_0100 // increment accumulator
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`define OC8051_INC_D 8'b0000_0101 // increment (direct)
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`define OC8051_INC_DP 8'b1010_0011 // increment data pointer
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`define OC8051_JB 8'b0010_0000 // jump if bit set
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`define OC8051_JBC 8'b0001_0000 // jump if bit set and clear bit
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`define OC8051_JC 8'b0100_0000 // jump if carry is set
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`define OC8051_JMP 8'b0111_0011 // jump indirect
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`define OC8051_JNB 8'b0011_0000 // jump if bit not set
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`define OC8051_JNC 8'b0101_0000 // jump if carry not set
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`define OC8051_JNZ 8'b0111_0000 // jump if accumulator not zero
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`define OC8051_JZ 8'b0110_0000 // jump if accumulator zero
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`define OC8051_LCALL 8'b0001_0010 // long call
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`define OC8051_LJMP 8'b0000_0010 // long jump
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`define OC8051_MOV_D 8'b1110_0101 // move A=(direct)
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`define OC8051_MOV_C 8'b0111_0100 // move A=constant
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`define OC8051_MOV_DA 8'b1111_0101 // move (direct)=A
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`define OC8051_MOV_DD 8'b1000_0101 // move (direct)=(direct)
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`define OC8051_MOV_CD 8'b0111_0101 // move (direct)=constant
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`define OC8051_MOV_BC 8'b1010_0010 // move c=bit
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`define OC8051_MOV_CB 8'b1001_0010 // move bit=c
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`define OC8051_MOV_DP 8'b1001_0000 // move dptr=constant(16 bit)
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`define OC8051_MOVC_DP 8'b1001_0011 // move A=dptr+A
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`define OC8051_MOVC_PC 8'b1000_0011 // move A=pc+A
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`define OC8051_MOVX_PA 8'b1110_0000 // move A=(dptr)
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`define OC8051_MOVX_AP 8'b1111_0000 // move (dptr)=A
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`define OC8051_MUL 8'b1010_0100 // multiply a*b
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`define OC8051_NOP 8'b0000_0000 // no operation
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`define OC8051_ORL_D 8'b0100_0101 // or A=A or (direct)
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`define OC8051_ORL_C 8'b0100_0100 // or A=A or constant
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`define OC8051_ORL_AD 8'b0100_0010 // or (direct)=(direct) or A
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`define OC8051_ORL_CD 8'b0100_0011 // or (direct)=(direct) or constant
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`define OC8051_ORL_B 8'b0111_0010 // or c = c or bit
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`define OC8051_ORL_NB 8'b1010_0000 // or c = c or !bit
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`define OC8051_POP 8'b1101_0000 // stack pop
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`define OC8051_PUSH 8'b1100_0000 // stack push
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`define OC8051_RET 8'b0010_0010 // return from subrutine
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`define OC8051_RETI 8'b0011_0010 // return from interrupt
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`define OC8051_RL 8'b0010_0011 // rotate left
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`define OC8051_RLC 8'b0011_0011 // rotate left thrugh carry
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`define OC8051_RR 8'b0000_0011 // rotate right
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`define OC8051_RRC 8'b0001_0011 // rotate right thrugh carry
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`define OC8051_SETB_C 8'b1101_0011 // set carry
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`define OC8051_SETB_B 8'b1101_0010 // set bit
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`define OC8051_SJMP 8'b1000_0000 // short jump
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`define OC8051_SUBB_D 8'b1001_0101 // substract with borrow A=A-c-(direct)
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`define OC8051_SUBB_C 8'b1001_0100 // substract with borrow A=A-c-constant
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`define OC8051_SWAP 8'b1100_0100 // swap A(0-3) <-> A(4-7)
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`define OC8051_XCH_D 8'b1100_0101 // exchange A<->(direct)
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`define OC8051_XRL_D 8'b0110_0101 // XOR A=A XOR (direct)
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`define OC8051_XRL_C 8'b0110_0100 // XOR A=A XOR constant
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`define OC8051_XRL_AD 8'b0110_0010 // XOR (direct)=(direct) XOR A
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`define OC8051_XRL_CD 8'b0110_0011 // XOR (direct)=(direct) XOR constant
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//
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// default values (used after reset)
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//
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`define OC8051_RST_PC 16'h0000 // program counter
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`define OC8051_RST_ACC 8'h00 // accumulator
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`define OC8051_RST_B 8'h00 // b register
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268 |
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`define OC8051_RST_PSW 8'h00 // program status word
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269 |
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`define OC8051_RST_SP 8'b0000_0111 // stack pointer
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270 |
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`define OC8051_RST_DPH 8'h00 // data pointer (high)
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`define OC8051_RST_DPL 8'h00 // data pointer (low)
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`define OC8051_RST_P0 8'b1111_1111 // port 0
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`define OC8051_RST_P1 8'b1111_1111 // port 1
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`define OC8051_RST_P2 8'b1111_1111 // port 2
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`define OC8051_RST_P3 8'b1111_1111 // port 3
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`define OC8051_RST_IP 8'b0000_0000 // interrupt priority
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`define OC8051_RST_IE 8'b0000_0000 // interrupt enable
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`define OC8051_RST_TMOD 8'b0000_0000 // timer/counter mode control
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`define OC8051_RST_TCON 8'b0000_0000 // timer/counter control
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280 |
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`define OC8051_RST_TH0 8'b0000_0000 // timer/counter 0 high bits
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`define OC8051_RST_TL0 8'b0000_0000 // timer/counter 0 low bits
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`define OC8051_RST_TH1 8'b0000_0000 // timer/counter 1 high bits
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`define OC8051_RST_TL1 8'b0000_0000 // timer/counter 1 low bits
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`define OC8051_RST_SCON 8'b0000_0000 // serial control
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`define OC8051_RST_SBUF 8'b0000_0000 // serial data buffer
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`define OC8051_RST_PCON 8'b0000_0000 // power control register
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288 |
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//
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289 |
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// ram read select
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290 |
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//
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291 |
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292 |
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`define OC8051_RRS_RN 2'b00 // registers
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293 |
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`define OC8051_RRS_I 2'b01 // indirect addressing
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`define OC8051_RRS_D 2'b10 // direct addressing
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`define OC8051_RRS_SP 2'b11 // stack pointer
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`define OC8051_RRS_DC 2'b00 // don't c
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//
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299 |
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// ram write select
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//
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301 |
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302 |
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`define OC8051_RWS_RN 3'b000 // registers
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`define OC8051_RWS_D 3'b001 // direct addressing
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`define OC8051_RWS_I 3'b010 // indirect addressing
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`define OC8051_RWS_SP 3'b011 // stack pointer
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`define OC8051_RWS_ACC 3'b100 // accumulator
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`define OC8051_RWS_D3 3'b101 // direct address (op3)
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`define OC8051_RWS_DPTR 3'b110 // data pointer (high + low)
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309 |
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`define OC8051_RWS_B 3'b111 // b register
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`define OC8051_RWS_DC 3'b000 //
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311 |
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312 |
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//
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313 |
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// immediate data select
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//
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315 |
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316 |
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`define OC8051_IDS_OP2 3'b000 // operand 2
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`define OC8051_IDS_OP3 3'b001 // operand 3
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`define OC8051_IDS_PCH 3'b010 // pc high
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`define OC8051_IDS_PCL 3'b011 // pc low
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`define OC8051_IDS_OP3_PCL 3'b100 // op3 and pc low
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321 |
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`define OC8051_IDS_OP3_OP2 3'b101 // op3 and op2
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`define OC8051_IDS_OP2_PCL 3'b110 // op2 and PC LOW
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`define OC8051_IDS_OP1 3'b111 // operand 1
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`define OC8051_IDS_DC 3'b000 //
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325 |
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326 |
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327 |
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//
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328 |
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// pc in select
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329 |
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//
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330 |
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`define OC8051_PIS_DC 2'b00 // dont c
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`define OC8051_PIS_SP 2'b00 // stack ( des1 -- serial)
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`define OC8051_PIS_ALU 2'b01 // alu {des1, des2}
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`define OC8051_PIS_I11 2'b10 // 11 bit immediate
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`define OC8051_PIS_I16 2'b11 // 16 bit immediate
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336 |
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//
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337 |
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// compare source select
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338 |
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//
|
339 |
41 |
simont |
`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero
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340 |
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`define OC8051_CSS_DES 2'b01 // eq = destination == zero
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341 |
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`define OC8051_CSS_CY 2'b10 // eq = cy
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342 |
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`define OC8051_CSS_BIT 2'b11 // eq = b_in
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`define OC8051_CSS_DC 2'b00 // don't care
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344 |
2 |
simont |
|
345 |
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|
346 |
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//
|
347 |
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// pc Write
|
348 |
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//
|
349 |
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`define OC8051_PCW_N 1'b0 // not
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350 |
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`define OC8051_PCW_Y 1'b1 // yes
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351 |
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|
352 |
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//
|
353 |
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//psw set
|
354 |
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//
|
355 |
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`define OC8051_PS_NOT 2'b00 // DONT
|
356 |
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`define OC8051_PS_CY 2'b01 // only carry
|
357 |
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`define OC8051_PS_OV 2'b10 // carry and overflov
|
358 |
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`define OC8051_PS_AC 2'b11 // carry, overflov an ac...
|
359 |
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|
360 |
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//
|
361 |
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// rom address select
|
362 |
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//
|
363 |
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`define OC8051_RAS_PC 1'b0 // program counter
|
364 |
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`define OC8051_RAS_DES 1'b1 // alu destination
|
365 |
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|
366 |
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//
|
367 |
|
|
// write accumulator
|
368 |
|
|
//
|
369 |
|
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`define OC8051_WA_N 1'b0 // not
|
370 |
|
|
`define OC8051_WA_Y 1'b1 // yes
|
371 |
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|
372 |
|
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|
373 |
|
|
//
|
374 |
|
|
//external ram address select
|
375 |
|
|
//
|
376 |
|
|
`define OC8051_EAS_DPTR 1'b0 // data pointer
|
377 |
|
|
`define OC8051_EAS_RI 1'b1 // register R0 or R1
|
378 |
|
|
`define OC8051_EAS_DC 1'b0
|
379 |
|
|
|
380 |
|
|
//
|
381 |
|
|
//write ac from des2
|
382 |
|
|
//
|
383 |
|
|
`define OC8051_WAD_N 1'b0 //
|
384 |
|
|
`define OC8051_WAD_Y 1'b1 //
|
385 |
|
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|
386 |
|
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|
387 |
|
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|
388 |
|
|
////////////////////////////////////////////////////
|
389 |
|
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|
390 |
|
|
//
|
391 |
|
|
// Timer/Counter modes
|
392 |
|
|
//
|
393 |
|
|
|
394 |
|
|
`define OC8051_MODE0 2'b00 // mode 0
|
395 |
|
|
`define OC8051_MODE1 2'b01 // mode 0
|
396 |
|
|
`define OC8051_MODE2 2'b10 // mode 0
|
397 |
|
|
`define OC8051_MODE3 2'b11 // mode 0
|
398 |
|
|
|
399 |
|
|
|
400 |
|
|
//
|
401 |
|
|
// Interrupt numbers (vectors)
|
402 |
|
|
//
|
403 |
|
|
|
404 |
|
|
`define OC8051_INT_T0 8'h0b // T/C 0 owerflow interrupt
|
405 |
|
|
`define OC8051_INT_T1 8'h1b // T/C 1 owerflow interrupt
|
406 |
|
|
`define OC8051_INT_X0 8'h03 // external interrupt 0
|
407 |
|
|
`define OC8051_INT_X1 8'h13 // external interrupt 1
|
408 |
|
|
`define OC8051_INT_UART 8'h23 // interrupt from uart
|
409 |
|
|
|
410 |
|
|
//
|
411 |
|
|
// interrupt levels
|
412 |
|
|
//
|
413 |
|
|
|
414 |
|
|
`define OC8051_ILEV_NO 2'b00 // no interrupts
|
415 |
|
|
`define OC8051_ILEV_L0 2'b01 // interrupt on level 0
|
416 |
|
|
`define OC8051_ILEV_L1 2'b10 // interrupt on level 1
|
417 |
|
|
|
418 |
|
|
//
|
419 |
|
|
// interrupt sources
|
420 |
|
|
//
|
421 |
|
|
`define OC8051_ISRC_NO 3'b000 // no interrupts
|
422 |
|
|
`define OC8051_ISRC_IE0 3'b001 // EXTERNAL INTERRUPT 0
|
423 |
|
|
`define OC8051_ISRC_TF0 3'b010 // t/c owerflov 0
|
424 |
|
|
`define OC8051_ISRC_IE1 3'b011 // EXTERNAL INTERRUPT 1
|
425 |
|
|
`define OC8051_ISRC_TF1 3'b100 // t/c owerflov 1
|
426 |
|
|
`define OC8051_ISRC_UART 3'b101 // UART Interrupt
|
427 |
|
|
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
//
|
431 |
|
|
// miscellaneus
|
432 |
|
|
//
|
433 |
|
|
|
434 |
|
|
`define OC8051_RW0 1'b1
|
435 |
|
|
`define OC8051_RW1 1'b0
|
436 |
|
|
|
437 |
|
|
|
438 |
|
|
//
|
439 |
|
|
// read modify write instruction
|
440 |
|
|
//
|
441 |
|
|
|
442 |
|
|
`define OC8051_RMW_Y 1'b1 // yes
|
443 |
|
|
`define OC8051_RMW_N 1'b0 // no
|