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[/] [8051/] [trunk/] [asm/] [counter_test.asm] - Blame information for rev 2

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Line No. Rev Author Line
1 2 simont
; r0: counter 0 owerflov counter
2
; r1: counter 1 owerflov counter
3
; r2: error code
4
; r3: counter high expected value
5
; r4: counter low expected value
6
; r5: owerflov counter expected value
7
 
8
        ajmp start;
9
 
10
        .org 03h        ;external interrupt 0
11
        reti;
12
 
13
        .org 0bh        ;t/c 0 interrupt
14
        inc r0;
15
        reti;
16
 
17
        .org 13h        ;external interrupt 1
18
        reti;
19
 
20
        .org 1bh        ;t/c 1 interrupt
21
        inc r1;
22
        reti;
23
 
24
        .org 23h        ;serial interface interrupt
25
        reti;
26
 
27
 
28
test0:
29
        mov a, th0      ;
30
        subb a, r3      ;
31
        jnz error       ;
32
        inc r2          ;
33
        mov a,tl0       ;
34
        subb a, r4      ;
35
        jnz error       ;
36
        inc r2          ;
37
        mov a, r0       ;
38
        subb a, r5      ;
39
        jnz error       ;
40
        ret;
41
 
42
test1:
43
        mov a, th1      ;
44
        subb a, r3      ;
45
        jnz error       ;
46
        inc r2          ;
47
        mov a,tl1       ;
48
        subb a, r4      ;
49
        jnz error       ;
50
        inc r2          ;
51
        mov a, r1       ;
52
        subb a, r5      ;
53
        jnz error       ;
54
        ret;
55
 
56
 
57
error:
58
        mov p0, r2;
59
        nop;
60
        ajmp error;
61
 
62
 
63
start:
64
        clr a;
65
        mov r0, a;
66
        mov r1, a;
67
        mov ie, #08ah   ;enable interrupts
68
        clr c;
69
 
70
;
71
; timer 0 test
72
;
73
; mode 0
74
;
75
        mov tmod, #004h ;t/c 0 and t/c 1 in counter mode 0
76
        mov th0, #000h  ;load counter 0
77
        mov tl0, #000h  ;
78
        mov tcon, #010h ;start counter 0;
79
        cpl p3.5;
80
        cpl p3.5;
81
        cpl p3.5;
82
        cpl p3.5;
83
        cpl p3.5;
84
        cpl p3.5;
85
        clr tcon.4      ;stop counter 0
86
        mov r2, #010h   ;
87
        mov r3, #000h   ;
88
        mov r4, #003h   ;
89
        mov r5, #000h   ;
90
        acall test0     ;
91
 
92
        mov tl0, #01ch  ; load counter 0
93
        setb tcon.4     ;start counter0
94
        cpl p3.5;
95
        cpl p3.5;
96
        cpl p3.5;
97
        cpl p3.5;
98
        cpl p3.5;
99
        cpl p3.5;
100
        cpl p3.5;
101
        cpl p3.5;
102
        clr tcon.4      ;stop counter 0
103
        mov r2, #020h   ;
104
        mov r3, #001h   ;
105
        mov r4, #000h   ;
106
        mov r5, #000h   ;
107
        acall test0     ;
108
 
109
        mov tl0, #01ch  ;
110
        mov th0, #0ffh  ;
111
        setb tcon.4     ;start counter 0
112
        cpl p3.5;
113
        cpl p3.5;
114
        cpl p3.5;
115
        cpl p3.5;
116
        cpl p3.5;
117
        cpl p3.5;
118
        cpl p3.5;
119
        cpl p3.5;
120
        cpl p3.5;
121
        cpl p3.5;
122
        clr tcon.4      ;stop counter 0
123
        mov r2, #030h   ;
124
        mov r3, #000h   ;
125
        mov r4, #001h   ;
126
        mov r5, #001h   ;
127
        acall test0     ;
128
;
129
; mode 1
130
;
131
        mov tmod, #005h ; t/c 0 in mode 1
132
        mov th0, #000h  ;load counter 0
133
        mov tl0, #000h  ;
134
        setb tcon.4     ;start counter 0;
135
        cpl p3.5;
136
        cpl p3.5;
137
        cpl p3.5;
138
        cpl p3.5;
139
        cpl p3.5;
140
        cpl p3.5;
141
        cpl p3.5;
142
        cpl p3.5;
143
        clr tcon.4      ;stop counter 0
144
        mov r2, #040h   ;
145
        mov r3, #000h   ;
146
        mov r4, #004h   ;
147
        mov r5, #001h   ;
148
        acall test0     ;
149
 
150
        mov tl0, #0fch  ; load counter 0
151
        setb tcon.4     ;start counter 0;
152
        cpl p3.5;
153
        cpl p3.5;
154
        cpl p3.5;
155
        cpl p3.5;
156
        cpl p3.5;
157
        cpl p3.5;
158
        cpl p3.5;
159
        cpl p3.5;
160
        cpl p3.5;
161
        cpl p3.5;
162
        clr tcon.4      ;stop counter 0;
163
        mov r2, #050h   ;
164
        mov r3, #001h   ;
165
        mov r4, #001h   ;
166
        mov r5, #001h   ;
167
        acall test0     ;
168
 
169
        mov tl0, #0fch  ;
170
        mov th0, #0ffh  ;
171
        setb tcon.4     ;start counter 0
172
        cpl p3.5;
173
        cpl p3.5;
174
        cpl p3.5;
175
        cpl p3.5;
176
        cpl p3.5;
177
        cpl p3.5;
178
        cpl p3.5;
179
        cpl p3.5;
180
        cpl p3.5;
181
        cpl p3.5;
182
        cpl p3.5;
183
        cpl p3.5;
184
        clr tcon.4      ;stop counter 0
185
        mov r2, #060h   ;
186
        mov r3, #000h   ;
187
        mov r4, #002h   ;
188
        mov r5, #002h   ;
189
        acall test0     ;
190
;
191
; mode 2
192
;
193
        mov tmod, #006h ; t/c 0 in mode 2
194
        mov th0, #000h  ;load counter 0
195
        mov tl0, #005h  ;
196
        setb tcon.4     ;start counter 0;
197
        cpl p3.5;
198
        cpl p3.5;
199
        cpl p3.5;
200
        cpl p3.5;
201
        cpl p3.5;
202
        cpl p3.5;
203
        cpl p3.5;
204
        cpl p3.5;
205
        clr tcon.4      ;stop counter 0
206
        mov r2, #070h   ;
207
        mov r3, #000h   ;
208
        mov r4, #009h   ;
209
        mov r5, #002h   ;
210
        acall test0     ;
211
 
212
        mov tl0, #0fch  ; load counter 0
213
        mov th0, #050h  ;
214
        setb tcon.4     ;start counter 0;
215
        cpl p3.5;
216
        cpl p3.5;
217
        cpl p3.5;
218
        cpl p3.5;
219
        cpl p3.5;
220
        cpl p3.5;
221
        cpl p3.5;
222
        cpl p3.5;
223
        cpl p3.5;
224
        cpl p3.5;
225
        clr tcon.4      ;stop counter 0;
226
        mov r2, #080h   ;
227
        mov r3, #050h   ;
228
        mov r4, #051h   ;
229
        mov r5, #003h   ;
230
        acall test0     ;
231
;
232
; mode 3
233
;
234
        mov tmod, #007h ; t/c 0 in mode 3
235
        mov th0, #000h  ;load counter 0
236
        mov tl0, #000h  ;
237
        setb tcon.4     ;start counter 0;
238
        cpl p3.5;
239
        cpl p3.5;
240
        cpl p3.5;
241
        cpl p3.5;
242
        cpl p3.5;
243
        cpl p3.5;
244
        cpl p3.5;
245
        cpl p3.5;
246
        clr tcon.4      ;stop counter 0
247
        mov r2, #090h   ;
248
        mov r3, #000h   ;
249
        mov r4, #004h   ;
250
        mov r5, #003h   ;
251
        acall test0     ;
252
 
253
        mov tl0, #0fch  ; load counter 0
254
        mov th0, #000h  ;
255
        setb tcon.4     ;start counter 0
256
        cpl p3.5;
257
        cpl p3.5;
258
        cpl p3.5;
259
        cpl p3.5;
260
        cpl p3.5;
261
        cpl p3.5;
262
        cpl p3.5;
263
        cpl p3.5;
264
        cpl p3.5;
265
        cpl p3.5;
266
        cpl p3.5;
267
        cpl p3.5;
268
        clr tcon.4      ;stop counter 0
269
        mov r2, #0a0h   ;
270
        mov r3, #000h   ;
271
        mov r4, #002h   ;
272
        mov r5, #004h   ;
273
        acall test0     ;
274
 
275
        mov tl0, #000h  ; load counter 0
276
        mov th0, #000h  ;
277
        setb tcon.6     ; start counter 1
278
        nop;
279
        nop;
280
        nop;
281
        clr tcon.6      ; stop counter 1
282
        mov r2, #0b0h   ;
283
        mov r3, #004h   ;
284
        mov r4, #000h   ;
285
        mov r5, #004h   ;
286
        acall test0     ;
287
 
288
        mov tl0, #000h  ; load counter 0
289
        mov th0, #0fch  ;
290
        setb tcon.6     ;start counter 1
291
        nop;
292
        nop;
293
        nop;
294
        nop;
295
        nop;
296
        clr tcon.6      ;stop counter 1
297
        mov r2, #0c0h   ;
298
        mov r3, #002h   ;
299
        mov r4, #000h   ;
300
        mov r5, #001h   ;
301
        mov r0, 01h     ;
302
        acall test0     ;
303
 
304
        mov p0, #001h   ; test counter 0 done!
305
        mov r1, #000h   ;
306
 
307
;
308
; timer 1 test
309
;
310
; mode 0
311
;
312
        mov tmod, #040h ;t/c 0 and t/c 1 in counter mode 0
313
        mov th1, #000h  ;load counter 1
314
        mov tl1, #000h  ;
315
        mov tcon, #040h ;start counter 1;
316
        cpl p3.6;
317
        cpl p3.6;
318
        cpl p3.6;
319
        cpl p3.6;
320
        cpl p3.6;
321
        cpl p3.6;
322
        cpl p3.6;
323
        cpl p3.6;
324
        clr tcon.6      ;stop counter 1
325
        mov r2, #018h   ;
326
        mov r3, #000h   ;
327
        mov r4, #004h   ;
328
        mov r5, #000h   ;
329
        acall test1     ;
330
 
331
        mov tl1, #01ch  ; load counter 1
332
        setb tcon.6     ;start counter 1
333
        cpl p3.6;
334
        cpl p3.6;
335
        cpl p3.6;
336
        cpl p3.6;
337
        cpl p3.6;
338
        cpl p3.6;
339
        cpl p3.6;
340
        cpl p3.6;
341
        cpl p3.6;
342
        cpl p3.6;
343
        clr tcon.6      ;stop counter 1
344
        mov r2, #028h   ;
345
        mov r3, #001h   ;
346
        mov r4, #001h   ;
347
        mov r5, #000h   ;
348
        acall test1     ;
349
 
350
        mov tl1, #01ch  ;
351
        mov th1, #0ffh  ;
352
        setb tcon.6     ;start counter 1
353
        cpl p3.6;
354
        cpl p3.6;
355
        cpl p3.6;
356
        cpl p3.6;
357
        cpl p3.6;
358
        cpl p3.6;
359
        cpl p3.6;
360
        cpl p3.6;
361
        cpl p3.6;
362
        cpl p3.6;
363
        cpl p3.6;
364
        cpl p3.6;
365
        clr tcon.6      ;stop counter 1
366
        mov r2, #038h   ;
367
        mov r3, #000h   ;
368
        mov r4, #002h   ;
369
        mov r5, #001h   ;
370
        acall test1     ;
371
;
372
; mode 1
373
;
374
        mov tmod, #050h ; t/c 1 in counter 1
375
        mov th1, #000h  ;load counter 1
376
        mov tl1, #000h  ;
377
        setb tcon.6     ;start counter 1
378
        cpl p3.6;
379
        cpl p3.6;
380
        cpl p3.6;
381
        cpl p3.6;
382
        cpl p3.6;
383
        cpl p3.6;
384
        cpl p3.6;
385
        cpl p3.6;
386
        clr tcon.6      ;stop counter 1
387
        mov r2, #048h   ;
388
        mov r3, #000h   ;
389
        mov r4, #004h   ;
390
        mov r5, #001h   ;
391
        acall test1     ;
392
 
393
        mov tl1, #0fch  ; load counter 1
394
        setb tcon.6     ; start counter 1
395
        cpl p3.6;
396
        cpl p3.6;
397
        cpl p3.6;
398
        cpl p3.6;
399
        cpl p3.6;
400
        cpl p3.6;
401
        cpl p3.6;
402
        cpl p3.6;
403
        cpl p3.6;
404
        cpl p3.6;
405
        clr tcon.6      ;stop counter 1
406
        mov r2, #058h   ;
407
        mov r3, #001h   ;
408
        mov r4, #001h   ;
409
        mov r5, #001h   ;
410
        acall test1     ;
411
 
412
        mov tl1, #0fch  ;
413
        mov th1, #0ffh  ;
414
        setb tcon.6     ;start counter 1
415
        cpl p3.6;
416
        cpl p3.6;
417
        cpl p3.6;
418
        cpl p3.6;
419
        cpl p3.6;
420
        cpl p3.6;
421
        cpl p3.6;
422
        cpl p3.6;
423
        cpl p3.6;
424
        cpl p3.6;
425
        cpl p3.6;
426
        cpl p3.6;
427
        clr tcon.6      ;stop counter 1
428
        mov r2, #068h   ;
429
        mov r3, #000h   ;
430
        mov r4, #002h   ;
431
        mov r5, #002h   ;
432
        acall test1     ;
433
;
434
; mode 2
435
;
436
        mov tmod, #060h ; t/c 1 in mode 2
437
        mov th1, #000h  ;load counter 1
438
        mov tl1, #005h  ;
439
        setb tcon.6     ;start counter 1
440
        cpl p3.6;
441
        cpl p3.6;
442
        cpl p3.6;
443
        cpl p3.6;
444
        cpl p3.6;
445
        cpl p3.6;
446
        cpl p3.6;
447
        cpl p3.6;
448
        clr tcon.6      ;stop counter 1
449
        mov r2, #078h   ;
450
        mov r3, #000h   ;
451
        mov r4, #009h   ;
452
        mov r5, #002h   ;
453
        acall test1     ;
454
 
455
        mov tl1, #0fch  ; load counter 1
456
        mov th1, #050h  ;
457
        setb tcon.6     ;start counter 1
458
        cpl p3.6;
459
        cpl p3.6;
460
        cpl p3.6;
461
        cpl p3.6;
462
        cpl p3.6;
463
        cpl p3.6;
464
        cpl p3.6;
465
        cpl p3.6;
466
        cpl p3.6;
467
        cpl p3.6;
468
        clr tcon.6      ;stop counter 1
469
        mov r2, #088h   ;
470
        mov r3, #050h   ;
471
        mov r4, #051h   ;
472
        mov r5, #003h   ;
473
        acall test1     ;
474
;
475
; mode 3
476
;
477
        mov tmod, #070h ; t/c 1 in mode 3
478
        mov th1, #000h  ;load counter 1
479
        mov tl1, #000h  ;
480
        setb tcon.6     ;start counter 1
481
        cpl p3.6;
482
        cpl p3.6;
483
        cpl p3.6;
484
        cpl p3.6;
485
        cpl p3.6;
486
        cpl p3.6;
487
        cpl p3.6;
488
        cpl p3.6;
489
        clr tcon.6      ;stop counter 1
490
        mov r2, #098h   ;
491
        mov r3, #000h   ;
492
        mov r4, #000h   ;
493
        mov r5, #003h   ;
494
        acall test1     ;
495
 
496
        mov tl1, #0fch  ; load counter 1
497
        mov th1, #0ffh  ;
498
        setb tcon.6     ;start counter 1
499
        cpl p3.6;
500
        cpl p3.6;
501
        cpl p3.6;
502
        cpl p3.6;
503
        cpl p3.6;
504
        cpl p3.6;
505
        cpl p3.6;
506
        cpl p3.6;
507
        cpl p3.6;
508
 
509
        cpl p3.6;
510
        cpl p3.6;
511
        cpl p3.6;
512
        clr tcon.6      ;stop counter 1
513
        mov r2, #0a8h   ;
514
        mov r3, #0ffh   ;
515
        mov r4, #0fch   ;
516
        mov r5, #003h   ;
517
        acall test1     ;
518
 
519
        mov p0, #002h   ; test counter 1 done!
520
 
521
 
522
 

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