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[/] [8051/] [trunk/] [asm/] [v/] [div16u.v] - Blame information for rev 186

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1 2 simont
 
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///
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/// created by oc8051 rom maker
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/// author: Simon Teran (simont@opencores.org)
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///
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/// source file: D:\tmp\asm\div16u.hex
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/// date: 5.7.02
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/// time: 13:28:06
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///
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module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
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parameter INT_ROM_WID= 7;
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input rst, clk;
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input [15:0] addr;
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output ea_int;
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output [7:0] data1, data2, data3;
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reg [7:0] data1, data2, data3;
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reg [7:0] buff [65535:0];
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integer i;
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wire ea;
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assign ea = | addr[15:INT_ROM_WID];
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assign ea_int = ! ea;
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initial
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begin
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    for (i=0; i<65536; i=i+1)
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      buff [i] = 8'h00;
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#2
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    buff [16'h00_00] = 8'h7D;
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    buff [16'h00_01] = 8'hA1;
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    buff [16'h00_02] = 8'h7C;
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    buff [16'h00_03] = 8'h54;
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    buff [16'h00_04] = 8'h79;
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    buff [16'h00_05] = 8'h01;
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    buff [16'h00_06] = 8'h78;
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    buff [16'h00_07] = 8'h70;
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    buff [16'h00_08] = 8'h12;
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    buff [16'h00_09] = 8'h00;
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    buff [16'h00_0a] = 8'h13;
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    buff [16'h00_0b] = 8'h8D;
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    buff [16'h00_0c] = 8'h80;
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    buff [16'h00_0d] = 8'h8C;
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    buff [16'h00_0e] = 8'h80;
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    buff [16'h00_0f] = 8'h89;
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    buff [16'h00_10] = 8'h80;
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    buff [16'h00_11] = 8'h88;
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    buff [16'h00_12] = 8'h80;
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    buff [16'h00_13] = 8'hE4;
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    buff [16'h00_14] = 8'hFA;
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    buff [16'h00_15] = 8'hFB;
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    buff [16'h00_16] = 8'h75;
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    buff [16'h00_17] = 8'hF0;
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    buff [16'h00_18] = 8'h01;
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    buff [16'h00_19] = 8'hE9;
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    buff [16'h00_1a] = 8'h48;
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    buff [16'h00_1b] = 8'h60;
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    buff [16'h00_1c] = 8'h53;
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    buff [16'h00_1d] = 8'hED;
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    buff [16'h00_1e] = 8'h4C;
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    buff [16'h00_1f] = 8'h70;
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    buff [16'h00_20] = 8'h04;
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    buff [16'h00_21] = 8'hFF;
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    buff [16'h00_22] = 8'hFE;
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    buff [16'h00_23] = 8'h01;
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    buff [16'h00_24] = 8'h6E;
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    buff [16'h00_25] = 8'hE9;
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    buff [16'h00_26] = 8'h33;
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    buff [16'h00_27] = 8'h40;
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    buff [16'h00_28] = 8'h16;
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    buff [16'h00_29] = 8'hC3;
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    buff [16'h00_2a] = 8'hED;
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    buff [16'h00_2b] = 8'h99;
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    buff [16'h00_2c] = 8'h40;
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    buff [16'h00_2d] = 8'h11;
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    buff [16'h00_2e] = 8'h70;
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    buff [16'h00_2f] = 8'h04;
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    buff [16'h00_30] = 8'hEC;
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    buff [16'h00_31] = 8'h98;
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    buff [16'h00_32] = 8'h40;
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    buff [16'h00_33] = 8'h0B;
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    buff [16'h00_34] = 8'hC3;
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    buff [16'h00_35] = 8'hE8;
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    buff [16'h00_36] = 8'h33;
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    buff [16'h00_37] = 8'hF8;
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    buff [16'h00_38] = 8'hE9;
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    buff [16'h00_39] = 8'h33;
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    buff [16'h00_3a] = 8'hF9;
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    buff [16'h00_3b] = 8'h05;
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    buff [16'h00_3c] = 8'hF0;
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    buff [16'h00_3d] = 8'h80;
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    buff [16'h00_3e] = 8'hE6;
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    buff [16'h00_3f] = 8'hC3;
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    buff [16'h00_40] = 8'hED;
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    buff [16'h00_41] = 8'h99;
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    buff [16'h00_42] = 8'h40;
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    buff [16'h00_43] = 8'h11;
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    buff [16'h00_44] = 8'h70;
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    buff [16'h00_45] = 8'h04;
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    buff [16'h00_46] = 8'hEC;
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    buff [16'h00_47] = 8'h98;
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    buff [16'h00_48] = 8'h40;
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    buff [16'h00_49] = 8'h0B;
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    buff [16'h00_4a] = 8'hEC;
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    buff [16'h00_4b] = 8'hC3;
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    buff [16'h00_4c] = 8'h98;
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    buff [16'h00_4d] = 8'hFC;
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    buff [16'h00_4e] = 8'hED;
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    buff [16'h00_4f] = 8'h99;
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    buff [16'h00_50] = 8'hFD;
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    buff [16'h00_51] = 8'hC3;
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    buff [16'h00_52] = 8'hB3;
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    buff [16'h00_53] = 8'h80;
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    buff [16'h00_54] = 8'h01;
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    buff [16'h00_55] = 8'hC3;
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    buff [16'h00_56] = 8'hEA;
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    buff [16'h00_57] = 8'h33;
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    buff [16'h00_58] = 8'hFA;
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    buff [16'h00_59] = 8'hEB;
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    buff [16'h00_5a] = 8'h33;
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    buff [16'h00_5b] = 8'hFB;
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    buff [16'h00_5c] = 8'hC3;
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    buff [16'h00_5d] = 8'hE9;
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    buff [16'h00_5e] = 8'h13;
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    buff [16'h00_5f] = 8'hF9;
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    buff [16'h00_60] = 8'hE8;
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    buff [16'h00_61] = 8'h13;
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    buff [16'h00_62] = 8'hF8;
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    buff [16'h00_63] = 8'hD5;
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    buff [16'h00_64] = 8'hF0;
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    buff [16'h00_65] = 8'hD9;
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    buff [16'h00_66] = 8'hED;
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    buff [16'h00_67] = 8'hFF;
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    buff [16'h00_68] = 8'hEC;
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    buff [16'h00_69] = 8'hFE;
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    buff [16'h00_6a] = 8'hEB;
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    buff [16'h00_6b] = 8'hFD;
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    buff [16'h00_6c] = 8'hEA;
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    buff [16'h00_6d] = 8'hFC;
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    buff [16'h00_6e] = 8'hC3;
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    buff [16'h00_6f] = 8'h22;
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    buff [16'h00_70] = 8'hC3;
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    buff [16'h00_71] = 8'hB3;
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    buff [16'h00_72] = 8'h22;
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end
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always @(posedge clk)
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begin
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  data1 <= #1 buff [addr];
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  data2 <= #1 buff [addr+1];
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  data3 <= #1 buff [addr+2];
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end
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endmodule

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