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simont |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// 8051 top level test bench ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// Description ////
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//// top level test bench. ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// ver: 1
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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module oc8051_tb;
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reg rst, clk, ea;
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reg [15:0] pc_in;
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reg [7:0] p0_in, p1_in, p2_in, op1, op2, op3;
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wire [15:0] ext_addr, rom_addr;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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///
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/// buffer for test vectors
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///
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//
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// buffer
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reg [23:0] buff [255:0];
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integer num;
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oc8051_top oc8051_top_1(.rst(rst), .clk(clk), .int0(int0), .int1(int1),
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.data_in(data_in), .data_out(data_out),
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.ext_addr(ext_addr), .rom_addr(rom_addr), .write(write), .p0_in(p0_in),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p2_out(p2_out), .p3_out(p3_out), .op1(op1), .op2(op2), .op3(op3), .ea(ea),
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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oc8051_xram oc8051_xram1 (.clk(clk), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram));
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart));
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assign write_xram = p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign p3_in = {7'b000000, bit_out, int_uart};
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assign t0 = p3_out[5];
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assign t1 = p3_out[6];
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assign int0 = p3_out[3];
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assign int1 = p3_out[4];
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initial begin
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clk= 1'b0;
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rst= 1'b1;
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// int0= 1'b1;
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// int1= 1'b1;
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pc_in = 16'h0000;
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p0_in = 8'h00;
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p1_in = 8'h00;
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p2_in = 8'h00;
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op1 = 8'h00;
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op2 = 8'h00;
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op3 = 8'h00;
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ea =1'b1;
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#22
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rst = 1'b0;
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#2000000
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//#500000
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$display("time ",$time, "\n faulire: end of time\n \n");
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$finish;
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end
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/*initial begin
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#222
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int= 1'b1;
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int_v= 8'h50;
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#20
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int= 1'b0;
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end*/
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always clk = #5 ~clk;
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initial
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$readmemh("../src/oc8051_test.vec", buff);
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initial num= 0;
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always @(p0_out or p1_out or p2_out)
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begin
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if ({p0_out, p1_out, p2_out} != buff[num])
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begin
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$display("time ",$time, " faulire: mismatch on ports in step %d", num);
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$display(" p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out);
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$display(" testvecp %h", buff[num]);
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$display(" p_out %h%h%h", p0_out, p1_out, p2_out);
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#22
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$finish;
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end
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else begin
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$display("time ",$time, " step %d", num, ": pass");
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num = num+1;
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if (buff[num]===24'hxxxxxx)
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begin
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$display("");
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$display(" Done!");
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$finish;
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end
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end
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end
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initial $dumpvars;
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//initial $monitor("time ",$time," acc %h", data_out, " dptr %h", ext_addr, " write ", write, " p0_out %h", p0_out, " p1_out %h", p1_out);
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//initial $monitor("time ",$time," write ", write, " p0_out ", p0_out, " p1_out ", p1_out, " p2_out ", p2_out, " p3_out ", p3_out);
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//initial $monitor("time ",$time," write ", write, " p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out, " p3_out %h", p3_out);
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endmodule
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