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[/] [8051/] [trunk/] [bench/] [verilog/] [oc8051_uart_test.v] - Blame information for rev 186

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1 97 simont
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  8051 uart test                                              ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////   submodul of oc8051_tb, used to comunicate with 8051        ////
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////   serial potr                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   nothing                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
48 125 simont
// Revision 1.1  2003/04/02 11:38:40  simont
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// initial inport
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//
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// Revision 1.4  2002/09/30 17:34:01  simont
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// prepared header
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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module oc8051_uart_test (clk, rst, addr, wr, wr_bit, data_in, data_out, bit_out, rxd, txd, ow, intr, ack, stb);
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//
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// serial interface simulation. part of oc8051_tb
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//
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// clk          (in)  clock
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// rst          (in)  reset
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// addr         (in)  addres [oc8051.ext_addr]
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// wr           (in)  write [oc8051.write]
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// wr_bit       (in) write bit addresable [oc8051.p3_out.0]
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// data_in      (out) data input [oc8051.data_out]
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// data_out     (in)  data output [oc8051.data_in]
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// rxd          (in)  receive data [oc8051.txd]
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// txd          (out) transmit data [oc8051.rxd]
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// ow           (in)  owerflov (used in mode 1 and 3) [oc8051.p3_out.1]
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// intr         (out) interrupt request [oc8051.p3_in.0]
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//
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input clk, rst, wr, wr_bit, rxd, ow, stb;
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input [7:0] addr, data_in;
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output txd, intr, bit_out, ack;
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output [7:0] data_out;
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reg [7:0] data_out;
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wire syn;
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reg wr_r, ack;
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reg [7:0] addr_r, data_in_r;
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wire tclk, rclk, brate2;
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assign tclk   = 0;
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assign rclk   = 0;
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assign brate2 = 0;
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reg       pres_ow;
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reg [3:0] prescaler;
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wire [7:0] scon, pcon, sbuf;
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oc8051_uart oc8051_uart_test(.rst(rst), .clk(clk), .bit_in(data_in[0]),
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             .data_in(data_in_r), .wr(wr_r), .wr_bit(wr_bit), .wr_addr(addr_r),
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             .rxd(rxd), .txd(txd), .intr(intr), .t1_ow(ow),
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             .rclk(rclk), .tclk(tclk),
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             .pres_ow(pres_ow), .brate2(brate2),
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             .scon(scon), .pcon(pcon), .sbuf(sbuf));
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always @(posedge clk)
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begin
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  if (ack) ack <= #1 1'b0;
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  else
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    ack <= #1 stb;
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end
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always @(posedge clk)
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begin
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  wr_r <= #1 wr;
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  addr_r <= #1 addr;
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  data_in_r <= #1 data_in;
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end
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    prescaler <= #1 4'h5;
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    pres_ow <= #1 1'b0;
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  end else if (prescaler==4'b1011) begin
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    prescaler <= #1 4'h0;
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    pres_ow <= #1 1'b1;
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  end else begin
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    prescaler <= #1 prescaler + 4'h1;
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    pres_ow <= #1 1'b0;
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  end
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end
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always @(addr or
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// serial interface
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         scon or pcon or sbuf)
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begin
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    case (addr)
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      `OC8051_SFR_SCON:         data_out = scon;
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      `OC8051_SFR_SBUF:         data_out = sbuf;
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      `OC8051_SFR_PCON:         data_out = pcon;
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      default:                  data_out = 8'h00;
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    endcase
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end
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assign bit_out = scon[addr[2:0]];
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endmodule

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