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[/] [8051/] [trunk/] [bench/] [verilog/] [oc8051_xrom.v] - Blame information for rev 186

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1 97 simont
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  8051 exteranl program rom                                   ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////   external program rom for 8051 core                         ////
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////                                                              ////
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////  To Do:                                                      ////
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////   Nothing                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
47 157 simont
// Revision 1.1  2003/04/02 11:38:40  simont
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// initial inport
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//
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// Revision 1.1  2002/10/17 18:56:13  simont
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// initial CVS input
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//
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//
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module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o);
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parameter DELAY=5;
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input rst, clk, stb_i, cyc_i;
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input [15:0] addr;
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output ack_o;
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output [31:0] data;
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reg ack_o;
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reg [31:0] data;
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reg [7:0] buff [0:65535];
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//reg [7:0] buff [8388607:0];
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reg [2:0] cnt;
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integer i;
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initial
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begin
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//  for (i=0; i<65536; i=i+1)
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//    buff [i] = 8'h00;
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  $readmemh("../../../bench/in/oc8051_xrom.in", buff);
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end
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    data <= #1 31'h0;
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    ack_o <= #1 1'b0;
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  end else if (stb_i && ((DELAY==3'b000) || (cnt==3'b000))) begin
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    data <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
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    ack_o <= #1 1'b1;
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  end else
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    ack_o <= #1 1'b0;
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end
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always @(posedge clk or posedge rst)
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begin
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  if (rst)
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    cnt <= #1 DELAY;
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  else if (cnt == 3'b000)
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    cnt <= #1 DELAY;
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  else if (stb_i)
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    cnt <= #1 cnt - 3'b001;
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  else cnt <= #1 DELAY;
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end
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endmodule
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