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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu_src_sel.v] - Blame information for rev 179

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 alu source select module                               ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   Multiplexer wiht whitch we select data on alu sources      ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2003/06/03 17:13:57  simont
// remove pc_r register.
//
// Revision 1.2  2003/05/06 09:41:35  simont
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
//
// Revision 1.1  2003/01/13 14:13:12  simont
// initial import
//
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_alu_src_sel (clk, rst, rd, sel1, sel2, sel3,
                     acc, ram, pc, dptr,
 
                     op1, op2, op3,
 
                     src1, src2, src3);
 
 
input clk, rst, rd, sel3;
input [1:0] sel2;
input [2:0] sel1;
input [7:0] acc, ram;
input [15:0] dptr;
input [15:0] pc;
 
 
input [7:0] op1, op2, op3;
 
output [7:0] src1, src2, src3;
 
reg [7:0] src1, src2, src3;
 
reg [7:0] op1_r, op2_r, op3_r;
 
///////
//
// src1
//
///////
always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)
begin
  case (sel1) /* synopsys full_case parallel_case */
    `OC8051_AS1_RAM: src1 = ram;
    `OC8051_AS1_ACC: src1 = acc;
    `OC8051_AS1_OP1: src1 = op1_r;
    `OC8051_AS1_OP2: src1 = op2_r;
    `OC8051_AS1_OP3: src1 = op3_r;
    `OC8051_AS1_PCH: src1 = pc[15:8];
    `OC8051_AS1_PCL: src1 = pc[7:0];
//    default: src1 = 8'h00;
  endcase
end
 
///////
//
// src2
//
///////
always @(sel2 or op2_r or acc or ram or op1_r)
begin
  case (sel2) /* synopsys full_case parallel_case */
    `OC8051_AS2_ACC: src2= acc;
    `OC8051_AS2_ZERO: src2= 8'h00;
    `OC8051_AS2_RAM: src2= ram;
    `OC8051_AS2_OP2: src2= op2_r;
//    default: src2= 8'h00;
  endcase
end
 
///////
//
// src3
//
///////
 
always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)
begin
  case (sel3) /* synopsys full_case parallel_case */
    `OC8051_AS3_DP:   src3= dptr[15:8];
    `OC8051_AS3_PC:   src3= pc[15:8];
//    default: src3= 16'h0;
  endcase
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    op1_r <= #1 8'h00;
    op2_r <= #1 8'h00;
    op3_r <= #1 8'h00;
  end else begin
    op1_r <= #1 op1;
    op2_r <= #1 op2;
    op3_r <= #1 op3;
  end
 
endmodule

Line No.	Rev	Author	Line
1	81	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 alu source select module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Multiplexer wiht whitch we select data on alu sources ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	179	simont	`// Revision 1.3 2003/06/03 17:13:57 simont`
48			`// remove pc_r register.`
49			`//`
50	151	simont	`// Revision 1.2 2003/05/06 09:41:35 simont`
51			`// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.`
52			`//`
53	141	simont	`// Revision 1.1 2003/01/13 14:13:12 simont`
54			`// initial import`
55	81	simont	`//`
56			`//`
57	141	simont	`//`
58	81	simont
59			`// synopsys translate_off`
60			`include "oc8051_timescale.v"
61			`// synopsys translate_on`
62
63			`include "oc8051_defines.v"
64
65
66			`module oc8051_alu_src_sel (clk, rst, rd, sel1, sel2, sel3,`
67			`acc, ram, pc, dptr,`
68
69			`op1, op2, op3,`
70
71			`src1, src2, src3);`
72
73
74			`input clk, rst, rd, sel3;`
75	141	simont	`input [1:0] sel2;`
76			`input [2:0] sel1;`
77	81	simont	`input [7:0] acc, ram;`
78			`input [15:0] dptr;`
79			`input [15:0] pc;`
80
81
82			`input [7:0] op1, op2, op3;`
83
84			`output [7:0] src1, src2, src3;`
85
86			`reg [7:0] src1, src2, src3;`
87
88			`reg [7:0] op1_r, op2_r, op3_r;`
89
90			`///////`
91			`//`
92			`// src1`
93			`//`
94			`///////`
95	151	simont	`always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)`
96	81	simont	`begin`
97	179	simont	`case (sel1) /* synopsys full_case parallel_case */`
98	81	simont	`OC8051_AS1_RAM: src1 = ram;
99			`OC8051_AS1_ACC: src1 = acc;
100			`OC8051_AS1_OP1: src1 = op1_r;
101			`OC8051_AS1_OP2: src1 = op2_r;
102			`OC8051_AS1_OP3: src1 = op3_r;
103	151	simont	`OC8051_AS1_PCH: src1 = pc[15:8];
104			`OC8051_AS1_PCL: src1 = pc[7:0];
105	179	simont	`// default: src1 = 8'h00;`
106	81	simont	`endcase`
107			`end`
108
109			`///////`
110			`//`
111			`// src2`
112			`//`
113			`///////`
114	151	simont	`always @(sel2 or op2_r or acc or ram or op1_r)`
115	81	simont	`begin`
116	179	simont	`case (sel2) /* synopsys full_case parallel_case */`
117	81	simont	`OC8051_AS2_ACC: src2= acc;
118			`OC8051_AS2_ZERO: src2= 8'h00;
119			`OC8051_AS2_RAM: src2= ram;
120			`OC8051_AS2_OP2: src2= op2_r;
121	179	simont	`// default: src2= 8'h00;`
122	81	simont	`endcase`
123			`end`
124
125			`///////`
126			`//`
127			`// src3`
128			`//`
129			`///////`
130
131			`always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)`
132			`begin`
133	179	simont	`case (sel3) /* synopsys full_case parallel_case */`
134	81	simont	`OC8051_AS3_DP: src3= dptr[15:8];
135			`OC8051_AS3_PC: src3= pc[15:8];
136	179	simont	`// default: src3= 16'h0;`
137	81	simont	`endcase`
138			`end`
139
140
141			`always @(posedge clk or posedge rst)`
142			`if (rst) begin`
143			`op1_r <= #1 8'h00;`
144			`op2_r <= #1 8'h00;`
145			`op3_r <= #1 8'h00;`
146			`end else begin`
147			`op1_r <= #1 op1;`
148			`op2_r <= #1 op2;`
149			`op3_r <= #1 op3;`
150			`end`
151
152			`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu_src_sel.v] - Blame information for rev 179