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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_b_register.v] - Blame information for rev 82

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores b register                                       ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   b register for 8051 core                                   ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit,
              wr_addr, rd_addr, data_out, wr_sfr);
//
// clk          (in)  clock
// rst          (in)  reset
// bit_in       (in)  bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
// data_in      (in)  data input - used to write to b register [oc8051_alu.des1]
// wr           (in)  write - actine high [oc8051_decoder.wr -r]
// wr_bit       (in)  write bit addresable - actine high [oc8051_decoder.bit_addr -r]
// wr_addr      (in)  write address [oc8051_ram_wr_sel.out]
// data_out     (out) data output [oc8051_ram_sel.b_reg]
// wr_sfr
//
 
 
input clk, rst, wr, wr_bit, bit_in;
input [2:0] rd_addr, wr_sfr;
input [7:0] wr_addr, data_in;
 
output bit_out;
output [7:0] data_out;
 
reg bit_out;
reg [7:0] data_out;
 
//
//writing to b
//must check if write high and correct address
always @(posedge clk or posedge rst)
begin
  if (rst)
    data_out <= #1 `OC8051_RST_B;
  else if (wr_sfr==`OC8051_WRS_BA)
    data_out <= #1 data_in;
  else if (wr) begin
    if (!wr_bit) begin
      if (wr_addr==`OC8051_SFR_B)
        data_out <= #1 data_in;
    end else begin
      if (wr_addr[7:3]==`OC8051_SFR_B_B)
        data_out[wr_addr[2:0]] <= #1 bit_in;
    end
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
    bit_out <= #1 bit_in;
  end else if ((wr_addr==`OC8051_SFR_B) & wr & !wr_bit) begin
    bit_out <= #1 data_in[rd_addr];
  end else bit_out <= #1 data_out[rd_addr];
end
 
endmodule

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores b register ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// b register for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.6 2002/09/30 17:33:59 simont`
48			`// prepared header`
49			`//`
50			`//`
51
52			`// synopsys translate_off`
53			`include "oc8051_timescale.v"
54			`// synopsys translate_on`
55
56			`include "oc8051_defines.v"
57
58
59			`module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit,`
60			`wr_addr, rd_addr, data_out, wr_sfr);`
61			`//`
62			`// clk (in) clock`
63			`// rst (in) reset`
64			`// bit_in (in) bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]`
65			`// data_in (in) data input - used to write to b register [oc8051_alu.des1]`
66			`// wr (in) write - actine high [oc8051_decoder.wr -r]`
67			`// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]`
68			`// wr_addr (in) write address [oc8051_ram_wr_sel.out]`
69			`// data_out (out) data output [oc8051_ram_sel.b_reg]`
70			`// wr_sfr`
71			`//`
72
73
74			`input clk, rst, wr, wr_bit, bit_in;`
75			`input [2:0] rd_addr, wr_sfr;`
76			`input [7:0] wr_addr, data_in;`
77
78			`output bit_out;`
79			`output [7:0] data_out;`
80
81			`reg bit_out;`
82			`reg [7:0] data_out;`
83
84			`//`
85			`//writing to b`
86			`//must check if write high and correct address`
87			`always @(posedge clk or posedge rst)`
88			`begin`
89			`if (rst)`
90			data_out <= #1 `OC8051_RST_B;
91			else if (wr_sfr==`OC8051_WRS_BA)
92			`data_out <= #1 data_in;`
93			`else if (wr) begin`
94			`if (!wr_bit) begin`
95			if (wr_addr==`OC8051_SFR_B)
96			`data_out <= #1 data_in;`
97			`end else begin`
98			if (wr_addr[7:3]==`OC8051_SFR_B_B)
99			`data_out[wr_addr[2:0]] <= #1 bit_in;`
100			`end`
101			`end`
102			`end`
103
104			`always @(posedge clk or posedge rst)`
105			`begin`
106			`if (rst) bit_out <= #1 1'b0;`
107			`else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin`
108			`bit_out <= #1 bit_in;`
109			end else if ((wr_addr==`OC8051_SFR_B) & wr & !wr_bit) begin
110			`bit_out <= #1 data_in[rd_addr];`
111			`end else bit_out <= #1 data_out[rd_addr];`
112			`end`
113
114			`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_b_register.v] - Blame information for rev 82